File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- CAN top level
71: --
72: -- Sub-modules:
73: -- 1. Memory registers
74: -- 2. Interrupt manager
75: -- 3. Prescaler (v3)
76: -- 4. Bus sampling
77: -- 5. RX Buffer
78: -- 6. TXT Buffers
79: -- 7. TX Arbitrator
80: -- 8. Frame filters
81: -- 9. Reset synchroniser
82: --------------------------------------------------------------------------------
83:
84: Library ieee;
85: use ieee.std_logic_1164.all;
86: use ieee.numeric_std.ALL;
87: use ieee.math_real.ALL;
88:
89: Library ctu_can_fd_rtl;
90: use ctu_can_fd_rtl.can_constants_pkg.all;
91: use ctu_can_fd_rtl.can_types_pkg.all;
92: use ctu_can_fd_rtl.can_config_pkg.all;
93:
94: use ctu_can_fd_rtl.CAN_FD_register_map.all;
95: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
96:
97: use ctu_can_fd_rtl.can_registers_pkg.all;
98:
99: entity can_top_level is
100: generic (
101: -- RX Buffer RAM size (32 bit words)
102: rx_buffer_size : natural range 32 to 4096 := 32;
103:
104: -- Number of supported TXT buffers
105: txt_buffer_count : natural range 2 to 8 := C_TXT_BUFFER_COUNT;
106:
107: -- Synthesize Filter A
108: sup_filtA : boolean := false;
109:
110: -- Synthesize Filter B
111: sup_filtB : boolean := false;
112:
113: -- Synthesize Filter C
114: sup_filtC : boolean := false;
115:
116: -- Synthesize Range Filter
117: sup_range : boolean := false;
118:
119: -- Synthesize Test registers
120: sup_test_registers : boolean := true;
121:
122: -- Insert Traffic counters
123: sup_traffic_ctrs : boolean := false;
124:
125: -- Add parity bit to TXT Buffer and RX Buffer RAMs
126: sup_parity : boolean := false;
127:
128: -- Number of active timestamp bits
129: active_timestamp_bits : natural range 0 to 63 := 63;
130:
131: -- Reset TXT / RX Buffer RAMs
132: reset_buffer_rams : boolean := false;
133:
134: -- Target technology (ASIC or FPGA)
135: target_technology : natural := C_TECH_FPGA
136: );
137: port(
138: -----------------------------------------------------------------------
139: -- Clock and Asynchronous reset
140: -----------------------------------------------------------------------
141: -- System clock
142: clk_sys : in std_logic;
143:
144: -- Asynchronous reset
145: res_n : in std_logic;
146:
147: -- Synchronized reset
148: res_n_out : out std_logic;
149:
150: -----------------------------------------------------------------------
151: -- DFT support
152: -----------------------------------------------------------------------
153: scan_enable : in std_logic;
154:
155: -----------------------------------------------------------------------
156: -- Memory interface
157: -----------------------------------------------------------------------
158: -- Input data
159: data_in : in std_logic_vector(31 downto 0);
160:
161: -- Output data
162: data_out : out std_logic_vector(31 downto 0);
163:
164: -- Address
165: adress : in std_logic_vector(15 downto 0);
166:
167: -- Chip select
168: scs : in std_logic;
169:
170: -- Read indication
171: srd : in std_logic;
172:
173: -- Write indication
174: swr : in std_logic;
175:
176: -- Byte enable
177: sbe : in std_logic_vector(3 downto 0);
178:
179: -----------------------------------------------------------------------
180: -- Interrupt Interface
181: -----------------------------------------------------------------------
182: -- Interrupt output
183: int : out std_logic;
184:
185: -----------------------------------------------------------------------
186: -- CAN Bus Interface
187: -----------------------------------------------------------------------
188: -- TX signal to CAN bus
189: can_tx : out std_logic;
190:
191: -- RX signal from CAN bus
192: can_rx : in std_logic;
193:
194: -----------------------------------------------------------------------
195: -- Debug signals for testbench
196: -----------------------------------------------------------------------
197: test_probe : out t_ctu_can_fd_test_probe;
198:
199: -----------------------------------------------------------------------
200: -- Timestamp for time based transmission / reception
201: -----------------------------------------------------------------------
202: timestamp : in std_logic_vector(63 downto 0)
203: );
204: end entity can_top_level;
205:
206: architecture rtl of can_top_level is
207:
208: -----------------------------------------------------------------------------------------------
209: -----------------------------------------------------------------------------------------------
210: ---- Internal constants
211: -----------------------------------------------------------------------------------------------
212: -----------------------------------------------------------------------------------------------
213: -- Width of RX Buffer pointers
214: constant C_RX_BUFF_PTR_WIDTH : natural range 5 to 12 :=
215: integer(ceil(log2(real(rx_buffer_size))));
216:
217: -- Width of RX Buffer frame counter
218: -- Minimal sized frame is 4 words. At e.g. rx_buffer_size = 256 (8 bits for pointers),
219: -- we get maximum 64 frames stored in RX Buffer (inclusive) -> 7 bits for frame counter.
220: constant C_RX_BUF_FRAME_CNT_WIDTH : natural range 3 to 11 :=
221: integer(ceil(log2(real(rx_buffer_size)))) - 1;
222:
223: -----------------------------------------------------------------------------------------------
224: -----------------------------------------------------------------------------------------------
225: ---- Internal signals
226: -----------------------------------------------------------------------------------------------
227: -----------------------------------------------------------------------------------------------
228:
229: -----------------------------------------------------------------------------------------------
230: -- Common signals
231: -----------------------------------------------------------------------------------------------
232:
233: -- Synchronised reset
234: signal res_n_sync : std_logic;
235:
236: -- Core reset (Synchronised reset + Soft Reset + Active when disabled)
237: signal res_core_n : std_logic;
238:
239: -- Soft reset ((Synchronised reset + Soft Reset)
240: signal res_soft_n : std_logic;
241:
242: -- Sample control (Nominal, Data, Secondary)
243: signal sp_control : std_logic_vector(1 downto 0);
244:
245: -----------------------------------------------------------------------------------------------
246: -- RX Buffer <-> Memory registers Interface
247: -----------------------------------------------------------------------------------------------
248: -- Signal whenever buffer is full (no free memory words)
249: signal rx_full : std_logic;
250:
251: -- Signal whenever buffer is empty (no frame (message) is stored)
252: signal rx_empty : std_logic;
253:
254: -- Number of frames stored in recieve buffer
255: signal rx_frame_count : std_logic_vector(C_RX_BUF_FRAME_CNT_WIDTH - 1 downto 0);
256:
257: -- Number of free 32 bit wide words
258: signal rx_mem_free : std_logic_vector(C_RX_BUFF_PTR_WIDTH downto 0);
259:
260: -- Position of read pointer
261: signal rx_read_pointer : std_logic_vector(C_RX_BUFF_PTR_WIDTH - 1 downto 0);
262:
263: -- Position of write pointer
264: signal rx_write_pointer : std_logic_vector(C_RX_BUFF_PTR_WIDTH - 1 downto 0);
265:
266: -- Overrun occurred, data were discarded!
267: -- (This is a flag and persists until it is cleared by SW)!
268: signal rx_data_overrun : std_logic;
269:
270: -- RX buffer middle of frame
271: signal rx_mof : std_logic;
272:
273: -- RX Buffer parity error flag
274: signal rx_parity_error : std_logic;
275:
276: -----------------------------------------------------------------------------------------------
277: -- TXT Buffer <-> Memory registers Interface
278: -----------------------------------------------------------------------------------------------
279:
280: -- TXT Buffer RAM - Data input
281: signal txtb_port_a_data_in : std_logic_vector(31 downto 0);
282:
283: -- TXT Buffer RAM - Parity input
284: signal txtb_port_a_parity : std_logic;
285:
286: -- TXT Buffer RAM - Address
287: signal txtb_port_a_address : std_logic_vector(4 downto 0);
288:
289: -- TXT Buffer chip select
290: signal txtb_port_a_cs : std_logic_vector(txt_buffer_count - 1 downto 0);
291:
292: -- TXT Buffer Port A byte enable
293: signal txtb_port_a_be : std_logic_vector(3 downto 0);
294:
295: -- TXT Buffer status
296: signal txtb_state : t_txt_bufs_state(txt_buffer_count - 1 downto 0);
297:
298: -- TXT Buffer is operating in Backup buffer
299: signal txtb_is_bb : std_logic_vector(txt_buffer_count / 2 - 1 downto 0);
300:
301: -----------------------------------------------------------------------------------------------
302: -- RX Buffer <-> CAN Core Interface
303: -----------------------------------------------------------------------------------------------
304: -- Frame Identifier
305: signal rec_ident : std_logic_vector(28 downto 0);
306:
307: -- Data length code
308: signal rec_dlc : std_logic_vector(3 downto 0);
309:
310: -- Recieved identifier type (0-BASE Format, 1-Extended Format);
311: signal rec_ident_type : std_logic;
312:
313: -- Recieved frame type (0-Normal CAN, 1- CAN FD)
314: signal rec_frame_type : std_logic;
315:
316: -- Received Loopback frame
317: signal rec_lbpf : std_logic;
318:
319: -- Recieved frame is RTR Frame(0-No, 1-Yes)
320: signal rec_is_rtr : std_logic;
321:
322: -- Whenever frame was recieved with BIT Rate shift
323: signal rec_brs : std_logic;
324:
325: -- Recieved error state indicator
326: signal rec_esi : std_logic;
327:
328: -- Received Identifier is valid
329: signal rec_ivld : std_logic;
330:
331: -- Data word which should be stored when "store_data" is active!
332: signal store_data_word : std_logic_vector(31 downto 0);
333:
334: -- Signals start of frame. If timestamp on RX frame should be captured
335: -- in the beginning of the frame, this pulse captures the timestamp!
336: signal sof_pulse : std_logic;
337:
338: -----------------------------------------------------------------------------------------------
339: -- Frame filters <-> CAN Core Interface (Commands for RX Buffer)
340: -----------------------------------------------------------------------------------------------
341: -- After control field of CAN frame, metadata are valid and can be stored.
342: -- This command starts the RX FSM for storing.
343: signal store_metadata : std_logic;
344:
345: -- Signal that one word of data can be stored (TX_DATA_X_W). This signal
346: -- is active when 4 bytes were received or data reception has finished
347: -- on 4 byte unaligned number of frames! (Thus allowing to store also
348: -- data which are not 4 byte aligned!
349: signal store_data : std_logic;
350:
351: -- Received frame valid (commit RX Frame)
352: signal rec_valid : std_logic;
353:
354: -- Abort storing of RX Frame to RX Buffer.
355: signal rec_abort : std_logic;
356:
357: -- Filtered version of RX Buffer commands
358: signal store_metadata_f : std_logic;
359: signal store_data_f : std_logic;
360: signal rec_valid_f : std_logic;
361: signal rec_abort_f : std_logic;
362:
363: -----------------------------------------------------------------------------------------------
364: -- TXT Buffers <-> Interrrupt Manager Interface
365: -----------------------------------------------------------------------------------------------
366: -- TXT HW Commands Applied Interrupt
367: signal txtb_hw_cmd_int : std_logic_vector(txt_buffer_count - 1 downto 0);
368:
369: -----------------------------------------------------------------------------------------------
370: -- TXT Buffers <-> CAN Core Interface
371: -----------------------------------------------------------------------------------------------
372: -- HW Commands
373: signal txtb_hw_cmd : t_txtb_hw_cmd;
374:
375: -----------------------------------------------------------------------------------------------
376: -- TXT Buffers <-> TX Arbitrator
377: -----------------------------------------------------------------------------------------------
378: -- Index of TXT Buffer for which HW commands is valid
379: signal txtb_hw_cmd_cs : std_logic_vector(txt_buffer_count - 1 downto 0);
380:
381: -- TXT Buffers are available, can be selected by TX Arbitrator
382: signal txtb_available : std_logic_vector(txt_buffer_count - 1 downto 0);
383:
384: -- TXT Buffer is in state for which its backup buffer can be used
385: signal txtb_allow_bb : std_logic_vector(txt_buffer_count - 1 downto 0);
386:
387: -- Pointer to TXT Buffer
388: signal txtb_ptr : natural range 0 to 20;
389:
390: -- TXT Buffer RAM data outputs
391: signal txtb_port_b_data_out : t_txt_bufs_output(txt_buffer_count - 1 downto 0);
392:
393: -- TXT Buffer RAM address
394: signal txtb_port_b_address : std_logic_vector(4 downto 0);
395:
396: -- Clock enable to TXT Buffer port B
397: signal txtb_port_b_clk_en : std_logic;
398:
399: -- Parity check valid
400: signal txtb_parity_check_valid : std_logic;
401:
402: -- Parity mismatch
403: signal txtb_parity_mismatch : std_logic_vector(txt_buffer_count - 1 downto 0);
404:
405: -- Parity error valid
406: signal txtb_parity_error_valid : std_logic_vector(txt_buffer_count - 1 downto 0);
407:
408: -- TXT Buffer
409: signal txtb_bb_parity_error : std_logic_vector(txt_buffer_count / 2 - 1 downto 0);
410:
411: -- TXT Buffer index selected by TX Arbitrator of CAN Core
412: signal txtb_index_muxed : natural range 0 to txt_buffer_count - 1;
413:
414: -----------------------------------------------------------------------------------------------
415: -- CAN Core <-> TX Arbitrator
416: -----------------------------------------------------------------------------------------------
417: -- TX Data length code
418: signal tran_dlc : std_logic_vector(3 downto 0);
419:
420: -- TX Remote transmission request flag
421: signal tran_is_rtr : std_logic;
422:
423: -- TX Identifier type (0-Basic,1-Extended);
424: signal tran_ident_type : std_logic;
425:
426: -- TX Frame type (0-CAN 2.0, 1-CAN FD)
427: signal tran_frame_type : std_logic;
428:
429: -- TX Frame Bit rate shift Flag
430: signal tran_brs : std_logic;
431:
432: -- TX Identifier
433: signal tran_identifier : std_logic_vector(28 downto 0);
434:
435: -- TX Frame test word
436: signal tran_frame_test : t_frame_test_w;
437:
438: -- Word from TXT Buffer RAM selected by TX Arbitrator
439: signal tran_word : std_logic_vector(31 downto 0);
440:
441: -- Valid frame is selected from transmission on output of TX Arbitrator.
442: -- CAN Core may lock TXT Buffer for transmission!
443: signal tran_frame_valid : std_logic;
444:
445: -- Parity error occured in TXT Buffer RAM during transmission of data words.
446: signal tran_frame_parity_error : std_logic;
447:
448: -- Selected TXT Buffer index changed
449: signal txtb_changed : std_logic;
450:
451: -- TXT Buffer clock enable
452: signal txtb_clk_en : std_logic;
453:
454: -----------------------------------------------------------------------------------------------
455: -- RX Buffer <-> TX Arbitrator
456: -----------------------------------------------------------------------------------------------
457:
458: -- TXT Buffer index that is:
459: -- - Currently validated (when no transmission is in progress)
460: -- - Used for transmission (when transmission is in progress)
461: signal curr_txtb_index : std_logic_vector(2 downto 0);
462:
463: -----------------------------------------------------------------------------------------------
464: -- CAN Core <-> Interrupt manager
465: -----------------------------------------------------------------------------------------------
466: -- Error appeared
467: signal err_detected : std_logic;
468:
469: -- Fault confinement state functionality changed
470: signal fcs_changed : std_logic;
471:
472: -- Error warning limit reached
473: signal err_warning_limit_pulse : std_logic;
474:
475: -- Arbitration was lost input
476: signal arbitration_lost : std_logic;
477:
478: -- Transmitted frame is valid
479: signal tran_valid : std_logic;
480:
481: -- Bit Rate Was Shifted
482: signal br_shifted : std_logic;
483:
484: -----------------------------------------------------------------------------------------------
485: -- CAN Core <-> Prescaler Interface
486: -----------------------------------------------------------------------------------------------
487: -- RX Triggers (Sample)
488: signal rx_triggers : std_logic_vector(C_SAMPLE_TRIGGER_COUNT - 1 downto 0);
489:
490: -- TX Trigger (Sync)
491: signal tx_trigger : std_logic;
492:
493: -- Synchronisation control (No synchronisation, Hard Synchronisation,
494: -- Resynchronisation
495: signal sync_control : std_logic_vector(1 downto 0);
496:
497: -- No positive resynchronisation
498: signal no_pos_resync : std_logic;
499:
500: -- Enable Nominal Bit time counters.
501: signal nbt_ctrs_en : std_logic;
502:
503: -- Enable Data Bit time counters.
504: signal dbt_ctrs_en : std_logic;
505:
506: -----------------------------------------------------------------------------------------------
507: -- Bus Sampling <-> Memory Registers Interface
508: -----------------------------------------------------------------------------------------------
509: -- Measured Transceiver delay
510: signal trv_delay : std_logic_vector(C_TRV_CTR_WIDTH - 1 downto 0);
511:
512: -----------------------------------------------------------------------------------------------
513: -- Bus Sampling <-> CAN Core Interface
514: -----------------------------------------------------------------------------------------------
515: -- RX Data With Bit Stuffing
516: signal rx_data_wbs : std_logic;
517:
518: -- TX Data With Bit Stuffing
519: signal tx_data_wbs : std_logic;
520:
521: -- Secondary sample point reset
522: signal ssp_reset : std_logic;
523:
524: -- Enable measurement of Transmitter delay
525: signal tran_delay_meas : std_logic;
526:
527: -- Bit Error detected
528: signal bit_err : std_logic;
529:
530: -- Reset Bit time measurement counter
531: signal btmc_reset : std_logic;
532:
533: -- Start Measurement of data bit time (in TX Trigger)
534: signal dbt_measure_start : std_logic;
535:
536: -- First SSP generated (in ESI bit)
537: signal gen_first_ssp : std_logic;
538:
539: -----------------------------------------------------------------------------------------------
540: -- Bus Sampling <-> Prescaler Interface
541: -----------------------------------------------------------------------------------------------
542: -- Synchronisation edge (aligned with time quanta)
543: signal sync_edge : std_logic;
544:
545: -- Bit error enable
546: signal bit_err_enable : std_logic;
547:
548: -----------------------------------------------------------------------------------------------
549: -- Bit time FSM outputs
550: -----------------------------------------------------------------------------------------------
551: -- Time quanta edge
552: signal tq_edge : std_logic;
553:
554: -----------------------------------------------------------------------------------------------
555: -- Memory registers
556: -----------------------------------------------------------------------------------------------
557: -- Configuration from Control registers to rest of the core
558: signal mr_ctrl_out : control_registers_out_t;
559:
560: -- Configuration from Test registers to rest of the core
561: signal mr_tst_out : test_registers_out_t;
562:
563: -- Status to registers from CAN core
564: signal cc_stat : t_can_core_stat;
565:
566: -- Debug record from Protocol control
567: signal pc_dbg : t_protocol_control_dbg;
568:
569: -- Interrupt values (actual interrupt status)
570: signal mr_int_stat_rxi_o : std_logic;
571: signal mr_int_stat_txi_o : std_logic;
572: signal mr_int_stat_ewli_o : std_logic;
573: signal mr_int_stat_doi_o : std_logic;
574: signal mr_int_stat_fcsi_o : std_logic;
575: signal mr_int_stat_ali_o : std_logic;
576: signal mr_int_stat_bei_o : std_logic;
577: signal mr_int_stat_ofi_o : std_logic;
578: signal mr_int_stat_rxfi_o : std_logic;
579: signal mr_int_stat_bsi_o : std_logic;
580: signal mr_int_stat_rbnei_o : std_logic;
581: signal mr_int_stat_txbhci_o : std_logic;
582:
583: -- Interrupt enable and mask
584: signal mr_int_ena_set_int_ena_set_o : std_logic_vector(C_INT_COUNT - 1 downto 0);
585: signal mr_int_mask_set_int_mask_set_o : std_logic_vector(C_INT_COUNT - 1 downto 0);
586:
587:
588: -----------------------------------------------------------------------------------------------
589: -- Memory testability Read data
590: -----------------------------------------------------------------------------------------------
591: -- RX buffer test data in
592: signal mr_tst_rdata_tst_rdata_rxb : std_logic_vector(31 downto 0);
593:
594: -- TXT buffers test data input
595: signal mr_tst_rdata_tst_rdata_txb : t_txt_bufs_output(txt_buffer_count - 1 downto 0);
596:
597: signal rxb_port_b_data_out : std_logic_vector(31 downto 0);
598:
599: signal pc_rx_trigger : std_logic;
600:
601: signal mr_tx_command_txbi : std_logic_vector(txt_buffer_count - 1 downto 0);
602: signal mr_tx_priority : t_txt_bufs_priorities(txt_buffer_count - 1 downto 0);
603:
604: begin
605:
606: -- Test probe for observation
607: test_probe.rx_trigger_nbs <= pc_rx_trigger;
608: test_probe.rx_trigger_wbs <= rx_triggers(0);
609: test_probe.tx_trigger <= tx_trigger;
610:
611: -----------------------------------------------------------------------------------------------
612: -- Reset synchroniser
613: -----------------------------------------------------------------------------------------------
614: rst_sync_inst : entity ctu_can_fd_rtl.rst_sync
615: generic map (
616: G_RESET_POLARITY => '0'
617: )
618: port map (
619: clk => clk_sys,
620: arst => res_n,
621: rst => res_n_sync
622: );
623: res_n_out <= res_n_sync;
624:
625: -----------------------------------------------------------------------------------------------
626: -- Memory registers
627: -----------------------------------------------------------------------------------------------
628: memory_registers_inst : entity ctu_can_fd_rtl.memory_registers
629: generic map (
630: G_SUP_FILTA => sup_filtA,
631: G_SUP_FILTB => sup_filtB,
632: G_SUP_FILTC => sup_filtC,
633: G_SUP_RANGE => sup_range,
634: G_SUP_TEST_REGISTERS => sup_test_registers,
635: G_SUP_TRAFFIC_CTRS => sup_traffic_ctrs,
636: G_SUP_PARITY => sup_parity,
637: G_TXT_BUFFER_COUNT => txt_buffer_count,
638: G_RX_BUFF_SIZE => rx_buffer_size,
639: G_RX_BUF_FRAME_CNT_WIDTH => C_RX_BUF_FRAME_CNT_WIDTH,
640: G_RX_BUFF_PTR_WIDTH => C_RX_BUFF_PTR_WIDTH,
641: G_INT_COUNT => C_INT_COUNT,
642: G_TRV_CTR_WIDTH => C_TRV_CTR_WIDTH,
643: G_TS_BITS => active_timestamp_bits,
644: G_DEVICE_ID => C_CAN_DEVICE_ID,
645: G_VERSION_MINOR => C_CTU_CAN_FD_VERSION_MINOR,
646: G_VERSION_MAJOR => C_CTU_CAN_FD_VERSION_MAJOR,
647: G_TECHNOLOGY => target_technology
648: )
649: port map (
650: clk_sys => clk_sys, -- IN
651: res_n => res_n_sync, -- IN
652:
653: -- Generated resets
654: res_core_n => res_core_n, -- OUT
655: res_soft_n => res_soft_n, -- OUT
656:
657: -- DFT support
658: scan_enable => scan_enable, -- IN
659:
660: -- Memory Interface
661: data_in => data_in, -- IN
662: data_out => data_out, -- OUT
663: adress => adress(11 downto 0), -- IN
664: scs => scs, -- IN
665: srd => srd, -- IN
666: swr => swr, -- IN
667: sbe => sbe, -- IN
668: timestamp => timestamp, -- IN
669:
670: -- Configuration and Status to/from rest of the core
671: mr_ctrl_out => mr_ctrl_out, -- OUT
672: mr_tst_out => mr_tst_out, -- OUT
673: cc_stat => cc_stat, -- IN
674: pc_dbg => pc_dbg, -- IN
675: mr_tst_rdata_tst_rdata_rxb => mr_tst_rdata_tst_rdata_rxb, -- IN
676: mr_tst_rdata_tst_rdata_txb => mr_tst_rdata_tst_rdata_txb, -- IN
677:
678: -- RX Buffer Interface
679: rx_full => rx_full, -- IN
680: rx_empty => rx_empty, -- IN
681: rx_frame_count => rx_frame_count, -- IN
682: rx_mem_free => rx_mem_free, -- IN
683: rx_read_pointer => rx_read_pointer, -- IN
684: rx_write_pointer => rx_write_pointer, -- IN
685: rx_data_overrun => rx_data_overrun, -- IN
686: rx_mof => rx_mof, -- IN
687: rx_parity_error => rx_parity_error, -- IN
688: rxb_port_b_data_out => rxb_port_b_data_out, -- IN
689:
690: -- Interface to TXT Buffers
691: txtb_port_a_data_in => txtb_port_a_data_in, -- OUT
692: txtb_port_a_address => txtb_port_a_address, -- OUT
693: txtb_port_a_cs => txtb_port_a_cs, -- OUT
694: txtb_port_a_be => txtb_port_a_be, -- OUT
695: mr_tx_priority => mr_tx_priority, -- OUT
696: mr_tx_command_txbi => mr_tx_command_txbi, -- OUT
697: txtb_state => txtb_state, -- IN
698: txtb_parity_error_valid => txtb_parity_error_valid, -- IN
699: txtb_bb_parity_error => txtb_bb_parity_error, -- IN
700:
701: -- Bus synchroniser interface
702: trv_delay => trv_delay, -- IN
703:
704: -- Interrrupt Manager Interface
705: mr_int_stat_rxi_o => mr_int_stat_rxi_o, -- IN
706: mr_int_stat_txi_o => mr_int_stat_txi_o, -- IN
707: mr_int_stat_ewli_o => mr_int_stat_ewli_o, -- IN
708: mr_int_stat_doi_o => mr_int_stat_doi_o, -- IN
709: mr_int_stat_fcsi_o => mr_int_stat_fcsi_o, -- IN
710: mr_int_stat_ali_o => mr_int_stat_ali_o, -- IN
711: mr_int_stat_bei_o => mr_int_stat_bei_o, -- IN
712: mr_int_stat_ofi_o => mr_int_stat_ofi_o, -- IN
713: mr_int_stat_rxfi_o => mr_int_stat_rxfi_o, -- IN
714: mr_int_stat_bsi_o => mr_int_stat_bsi_o, -- IN
715: mr_int_stat_rbnei_o => mr_int_stat_rbnei_o, -- IN
716: mr_int_stat_txbhci_o => mr_int_stat_txbhci_o, -- IN
717:
718: mr_int_ena_set_int_ena_set_o => mr_int_ena_set_int_ena_set_o, -- IN
719: mr_int_mask_set_int_mask_set_o => mr_int_mask_set_int_mask_set_o -- IN
720: );
721:
722: -----------------------------------------------------------------------------------------------
723: -- RX Buffer
724: -----------------------------------------------------------------------------------------------
725: rx_buffer_inst : entity ctu_can_fd_rtl.rx_buffer
726: generic map (
727: G_RX_BUFF_SIZE => rx_buffer_size,
728: G_RX_BUFF_PTR_WIDTH => C_RX_BUFF_PTR_WIDTH,
729: G_RX_BUF_FRAME_CNT_WIDTH => C_RX_BUF_FRAME_CNT_WIDTH,
730: G_SUP_PARITY => sup_parity,
731: G_RESET_RX_BUF_RAM => reset_buffer_rams,
732: G_TECHNOLOGY => target_technology
733: )
734: port map (
735: -- Clocks and Asynchronous reset
736: clk_sys => clk_sys, -- IN
737: res_n => res_core_n, -- IN
738:
739: -- DFT support
740: scan_enable => scan_enable, -- IN
741:
742: -- Metadata from CAN Core
743: rec_ident => rec_ident, -- IN
744: rec_dlc => rec_dlc, -- IN
745: rec_ident_type => rec_ident_type, -- IN
746: rec_frame_type => rec_frame_type, -- IN
747: rec_lbpf => rec_lbpf, -- IN
748: rec_is_rtr => rec_is_rtr, -- IN
749: rec_brs => rec_brs, -- IN
750: rec_esi => rec_esi, -- IN
751: rec_ivld => rec_ivld, -- IN
752:
753: -- Control signals from CAN Core which control storing of CAN Frame.
754: -- Filtered by Frame filters.
755: store_metadata_f => store_metadata_f, -- IN
756: store_data_f => store_data_f, -- IN
757: store_data_word => store_data_word, -- IN
758: rec_valid_f => rec_valid_f, -- IN
759: rec_abort_f => rec_abort_f, -- IN
760: sof_pulse => sof_pulse, -- IN
761: err_capt_err_type => cc_stat.err_type, -- IN
762: err_capt_err_pos => cc_stat.err_pos, -- IN
763: err_capt_err_erp => cc_stat.err_erp, -- IN
764:
765: -- Status signals of recieve buffer
766: rx_full => rx_full, -- OUT
767: rx_empty => rx_empty, -- OUT
768: rx_frame_count => rx_frame_count, -- OUT
769: rx_mem_free => rx_mem_free, -- OUT
770: rx_read_pointer => rx_read_pointer, -- OUT
771: rx_write_pointer => rx_write_pointer, -- OUT
772: rx_data_overrun => rx_data_overrun, -- OUT
773: rx_mof => rx_mof, -- OUT
774: rx_parity_error => rx_parity_error, -- OUT
775: rxb_port_b_data_out => rxb_port_b_data_out, -- OUT
776:
777: -- External timestamp input
778: timestamp => timestamp, -- IN
779:
780: -- TX Arbitrator interface
781: curr_txtb_index => curr_txtb_index, -- IN
782:
783: -- Memory registers interface
784: mr_mode_rxbam => mr_ctrl_out.mode_rxbam, -- IN
785: mr_command_cdo => mr_ctrl_out.command_cdo, -- IN
786: mr_command_crxpe => mr_ctrl_out.command_crxpe, -- IN
787: mr_command_rrb => mr_ctrl_out.command_rrb, -- IN
788: mr_command_rxrpmv => mr_ctrl_out.command_rxrpmv, -- IN
789: mr_rx_data_read => mr_ctrl_out.rx_data_read, -- IN
790: mr_rx_settings_rtsop => mr_ctrl_out.rx_settings_rtsop, -- IN
791: mr_settings_pchke => mr_ctrl_out.settings_pchke, -- IN
792: mr_mode_erfm => mr_ctrl_out.mode_erfm, -- IN
793:
794: -- Memory testability
795: mr_tst_control_tmaena => mr_tst_out.tst_control_tmaena, -- IN
796: mr_tst_control_twrstb => mr_tst_out.tst_control_twrstb, -- IN
797: mr_tst_dest_tst_addr => mr_tst_out.tst_dest_tst_addr, -- IN
798: mr_tst_dest_tst_mtgt => mr_tst_out.tst_dest_tst_mtgt, -- IN
799: mr_tst_wdata_tst_wdata => mr_tst_out.tst_wdata_tst_wdata, -- IN
800:
801: mr_tst_rdata_tst_rdata => mr_tst_rdata_tst_rdata_rxb -- OUT
802: );
803:
804: -----------------------------------------------------------------------------------------------
805: -- TXT Buffer port A parity encoding
806: -----------------------------------------------------------------------------------------------
807: txtb_parity_true_gen : if (sup_parity) generate
808: txtb_port_a_parity_calculator_inst : entity ctu_can_fd_rtl.parity_calculator
809: generic map (
810: G_WIDTH => 32,
811: G_PARITY_TYPE => C_PARITY_TYPE
812: )
813: port map(
814: data_in => txtb_port_a_data_in,
815: parity => txtb_port_a_parity
816: );
817: end generate;
818:
819: txtb_parity_false_gen : if (not sup_parity) generate
820: txtb_port_a_parity <= '0';
821: end generate;
822:
823:
824: -----------------------------------------------------------------------------------------------
825: -- TXT Buffers
826: -----------------------------------------------------------------------------------------------
827:
828: txt_buf_comp_gen : for i in 0 to txt_buffer_count - 1 generate
829: begin
830:
831: txt_buf_even_gen : if ((i mod 2) = 0) generate
832: txt_buffer_even_inst : entity ctu_can_fd_rtl.txt_buffer_even
833: generic map (
834: G_TXT_BUFFER_COUNT => txt_buffer_count,
835: G_ID => i,
836: G_TECHNOLOGY => target_technology,
837: G_SUP_PARITY => sup_parity,
838: G_RESET_TXT_BUF_RAM => reset_buffer_rams
839: )
840: port map (
841: -- Clock and Asynchronous reset
842: clk_sys => clk_sys, -- IN
843: res_n => res_core_n, -- IN
844:
845: -- DFT support
846: scan_enable => scan_enable, -- IN
847:
848: -- Memory Registers Interface
849: mr_mode_bmm => mr_ctrl_out.mode_bmm, -- IN
850: mr_mode_rom => mr_ctrl_out.mode_rom, -- IN
851: mr_mode_txbbm => mr_ctrl_out.mode_txbbm, -- IN
852: mr_settings_tbfbo => mr_ctrl_out.settings_tbfbo, -- IN
853: mr_settings_pchke => mr_ctrl_out.settings_pchke, -- IN
854: mr_tx_command_txce => mr_ctrl_out.tx_command_txce, -- IN
855: mr_tx_command_txcr => mr_ctrl_out.tx_command_txcr, -- IN
856: mr_tx_command_txca => mr_ctrl_out.tx_command_txca, -- IN
857: mr_tx_command_txbi => mr_tx_command_txbi(i), -- IN
858:
859: mr_tst_control_tmaena => mr_tst_out.tst_control_tmaena, -- IN
860: mr_tst_control_twrstb => mr_tst_out.tst_control_twrstb, -- IN
861: mr_tst_dest_tst_addr => mr_tst_out.tst_dest_tst_addr(4 downto 0), -- IN
862: mr_tst_dest_tst_mtgt => mr_tst_out.tst_dest_tst_mtgt, -- IN
863: mr_tst_wdata_tst_wdata => mr_tst_out.tst_wdata_tst_wdata, -- IN
864: mr_tst_rdata_tst_rdata => mr_tst_rdata_tst_rdata_txb(i), -- OUT
865:
866: txtb_port_a_data_in => txtb_port_a_data_in, -- IN
867: txtb_port_a_parity => txtb_port_a_parity, -- IN
868: txtb_port_a_address => txtb_port_a_address, -- IN
869: txtb_port_a_cs => txtb_port_a_cs(i), -- IN
870: txtb_port_a_be => txtb_port_a_be, -- IN
871:
872: txtb_state => txtb_state(i), -- OUT
873:
874: -- Interrupt Manager Interface
875: txtb_hw_cmd_int => txtb_hw_cmd_int(i), -- OUT
876:
877: -- CAN Core and TX Arbitrator Interface
878: txtb_hw_cmd => txtb_hw_cmd, -- IN
879: txtb_hw_cmd_cs => txtb_hw_cmd_cs(i), -- IN
880: txtb_port_b_data_out => txtb_port_b_data_out(i), -- OUT
881: txtb_port_b_address => txtb_port_b_address, -- IN
882: txtb_port_b_clk_en => txtb_port_b_clk_en, -- IN
883: is_bus_off => cc_stat.is_bus_off, -- IN
884: txtb_available => txtb_available(i), -- OUT
885: txtb_allow_bb => txtb_allow_bb(i), -- OUT
886: txtb_parity_check_valid => txtb_parity_check_valid, -- IN
887: txtb_parity_mismatch => txtb_parity_mismatch(i), -- OUT
888: txtb_parity_error_valid => txtb_parity_error_valid(i), -- OUT
889: txtb_index_muxed => txtb_index_muxed -- IN
890: );
891: end generate;
892:
893: txt_buf_odd_gen : if ((i mod 2) = 1) generate
894: txt_buffer_odd_inst : entity ctu_can_fd_rtl.txt_buffer_odd
895: generic map (
896: G_TXT_BUFFER_COUNT => txt_buffer_count,
897: G_ID => i,
898: G_TECHNOLOGY => target_technology,
899: G_SUP_PARITY => sup_parity,
900: G_RESET_TXT_BUF_RAM => reset_buffer_rams
901: )
902: port map (
903: -- Clock and Asynchronous reset
904: clk_sys => clk_sys, -- IN
905: res_n => res_core_n, -- IN
906:
907: -- DFT support
908: scan_enable => scan_enable, -- IN
909:
910: -- Memory Registers Interface
911: mr_mode_bmm => mr_ctrl_out.mode_bmm, -- IN
912: mr_mode_rom => mr_ctrl_out.mode_rom, -- IN
913: mr_mode_txbbm => mr_ctrl_out.mode_txbbm, -- IN
914: mr_settings_tbfbo => mr_ctrl_out.settings_tbfbo, -- IN
915: mr_settings_pchke => mr_ctrl_out.settings_pchke, -- IN
916: mr_tx_command_txce => mr_ctrl_out.tx_command_txce, -- IN
917: mr_tx_command_txcr => mr_ctrl_out.tx_command_txcr, -- IN
918: mr_tx_command_txca => mr_ctrl_out.tx_command_txca, -- IN
919: mr_tx_command_txbi => mr_tx_command_txbi(i), -- IN
920:
921: mr_tst_control_tmaena => mr_tst_out.tst_control_tmaena, -- IN
922: mr_tst_control_twrstb => mr_tst_out.tst_control_twrstb, -- IN
923: mr_tst_dest_tst_addr => mr_tst_out.tst_dest_tst_addr(4 downto 0), -- IN
924: mr_tst_dest_tst_mtgt => mr_tst_out.tst_dest_tst_mtgt, -- IN
925: mr_tst_wdata_tst_wdata => mr_tst_out.tst_wdata_tst_wdata, -- IN
926: mr_tst_rdata_tst_rdata => mr_tst_rdata_tst_rdata_txb(i), -- OUT
927:
928: txtb_port_a_data_in => txtb_port_a_data_in, -- IN
929: txtb_port_a_parity => txtb_port_a_parity, -- IN
930: txtb_port_a_address => txtb_port_a_address, -- IN
931: txtb_port_a_cs => txtb_port_a_cs(i), -- IN
932: txtb_port_a_be => txtb_port_a_be, -- IN
933:
934: txtb_state => txtb_state(i), -- OUT
935: txtb_is_bb => txtb_is_bb(i / 2), -- IN
936:
937: -- Interrupt Manager Interface
938: txtb_hw_cmd_int => txtb_hw_cmd_int(i), -- OUT
939:
940: -- CAN Core and TX Arbitrator Interface
941: txtb_hw_cmd => txtb_hw_cmd, -- IN
942: txtb_hw_cmd_cs => txtb_hw_cmd_cs(i), -- IN
943: txtb_port_b_data_out => txtb_port_b_data_out(i), -- OUT
944: txtb_port_b_address => txtb_port_b_address, -- IN
945: txtb_port_b_clk_en => txtb_port_b_clk_en, -- IN
946: is_bus_off => cc_stat.is_bus_off, -- IN
947: txtb_available => txtb_available(i), -- OUT
948: txtb_allow_bb => txtb_allow_bb(i), -- OUT
949: txtb_parity_check_valid => txtb_parity_check_valid, -- IN
950: txtb_parity_mismatch => txtb_parity_mismatch(i), -- OUT
951: txtb_parity_error_valid => txtb_parity_error_valid(i), -- OUT
952: txtb_bb_parity_error => txtb_bb_parity_error(i / 2), -- OUT
953: txtb_index_muxed => txtb_index_muxed -- IN
954: );
955: end generate;
956:
957: end generate;
958:
959: -----------------------------------------------------------------------------------------------
960: -- TX Arbitrator
961: -----------------------------------------------------------------------------------------------
962: tx_arbitrator_inst : entity ctu_can_fd_rtl.tx_arbitrator
963: generic map (
964: G_TXT_BUFFER_COUNT => txt_buffer_count
965: )
966: port map (
967: -- Clock and Asynchronous reset
968: clk_sys => clk_sys, -- IN
969: res_n => res_core_n, -- IN
970:
971: -- TXT Buffers interface
972: txtb_port_b_data_out => txtb_port_b_data_out, -- IN
973: txtb_available => txtb_available, -- IN
974: txtb_allow_bb => txtb_allow_bb, -- OUT
975: txtb_port_b_address => txtb_port_b_address, -- OUT
976: txtb_port_b_clk_en => txtb_port_b_clk_en, -- OUT
977: txtb_parity_check_valid => txtb_parity_check_valid, -- OUT
978: txtb_parity_mismatch => txtb_parity_mismatch, -- IN
979: txtb_index_muxed => txtb_index_muxed, -- OUT
980: txtb_is_bb => txtb_is_bb, -- OUT
981:
982: -- CAN Core Interface
983: tran_word => tran_word, -- OUT
984: tran_dlc => tran_dlc, -- OUT
985: tran_is_rtr => tran_is_rtr, -- OUT
986: tran_ident_type => tran_ident_type, -- OUT
987: tran_frame_type => tran_frame_type, -- OUT
988: tran_brs => tran_brs, -- OUT
989: tran_identifier => tran_identifier, -- OUT
990: tran_frame_test => tran_frame_test, -- OUT
991: tran_frame_valid => tran_frame_valid, -- OUT
992: tran_frame_parity_error => tran_frame_parity_error, -- OUT
993: txtb_hw_cmd => txtb_hw_cmd, -- IN
994: txtb_changed => txtb_changed, -- OUT
995: txtb_hw_cmd_cs => txtb_hw_cmd_cs, -- OUT
996: txtb_ptr => txtb_ptr, -- IN
997: txtb_clk_en => txtb_clk_en, -- IN
998:
999: -- RX Buffer interface
1000: curr_txtb_index => curr_txtb_index, -- OUT
1001:
1002: -- Memory registers interface
1003: mr_mode_tttm => mr_ctrl_out.mode_tttm, -- IN
1004: mr_mode_txbbm => mr_ctrl_out.mode_txbbm, -- IN
1005: mr_settings_pchke => mr_ctrl_out.settings_pchke, -- IN
1006: mr_tx_priority => mr_tx_priority, -- IN
1007:
1008: -- Timestamp
1009: timestamp => timestamp -- IN
1010: );
1011:
1012: -----------------------------------------------------------------------------------------------
1013: -- Frame Filters
1014: -----------------------------------------------------------------------------------------------
1015: frame_filters_inst : entity ctu_can_fd_rtl.frame_filters
1016: generic map(
1017: G_SUP_FILTA => sup_filtA,
1018: G_SUP_FILTB => sup_filtB,
1019: G_SUP_FILTC => sup_filtC,
1020: G_SUP_RANGE => sup_range
1021: )
1022: port map(
1023: -- Clock an Asynchronous reset
1024: clk_sys => clk_sys, -- IN
1025: res_n => res_core_n, -- IN
1026:
1027: -- Memory registers interface
1028: mr_filter_control_fafe => mr_ctrl_out.filter_control_fafe, -- IN
1029: mr_filter_control_fafb => mr_ctrl_out.filter_control_fafb, -- IN
1030: mr_filter_control_fane => mr_ctrl_out.filter_control_fane, -- IN
1031: mr_filter_control_fanb => mr_ctrl_out.filter_control_fanb, -- IN
1032:
1033: mr_filter_control_fbfe => mr_ctrl_out.filter_control_fbfe, -- IN
1034: mr_filter_control_fbfb => mr_ctrl_out.filter_control_fbfb, -- IN
1035: mr_filter_control_fbne => mr_ctrl_out.filter_control_fbne, -- IN
1036: mr_filter_control_fbnb => mr_ctrl_out.filter_control_fbnb, -- IN
1037:
1038: mr_filter_control_fcfe => mr_ctrl_out.filter_control_fcfe, -- IN
1039: mr_filter_control_fcfb => mr_ctrl_out.filter_control_fcfb, -- IN
1040: mr_filter_control_fcne => mr_ctrl_out.filter_control_fcne, -- IN
1041: mr_filter_control_fcnb => mr_ctrl_out.filter_control_fcnb, -- IN
1042:
1043: mr_filter_control_frfe => mr_ctrl_out.filter_control_frfe, -- IN
1044: mr_filter_control_frfb => mr_ctrl_out.filter_control_frfb, -- IN
1045: mr_filter_control_frne => mr_ctrl_out.filter_control_frne, -- IN
1046: mr_filter_control_frnb => mr_ctrl_out.filter_control_frnb, -- IN
1047:
1048: mr_filter_a_mask_bit_mask_a_val => mr_ctrl_out.filter_a_mask_bit_mask_a_val, -- IN
1049: mr_filter_a_val_bit_val_a_val => mr_ctrl_out.filter_a_val_bit_val_a_val, -- IN
1050: mr_filter_b_mask_bit_mask_b_val => mr_ctrl_out.filter_b_mask_bit_mask_b_val, -- IN
1051: mr_filter_b_val_bit_val_b_val => mr_ctrl_out.filter_b_val_bit_val_b_val, -- IN
1052: mr_filter_c_mask_bit_mask_c_val => mr_ctrl_out.filter_c_mask_bit_mask_c_val, -- IN
1053: mr_filter_c_val_bit_val_c_val => mr_ctrl_out.filter_c_val_bit_val_c_val, -- IN
1054: mr_filter_ran_high_bit_ran_high_val => mr_ctrl_out.filter_ran_high_bit_ran_high_val, -- IN
1055: mr_filter_ran_low_bit_ran_low_val => mr_ctrl_out.filter_ran_low_bit_ran_low_val, -- IN
1056:
1057: mr_settings_fdrf => mr_ctrl_out.settings_fdrf, -- IN
1058: mr_mode_afm => mr_ctrl_out.mode_afm, -- IN
1059:
1060: -- CAN Core interface
1061: rec_ident => rec_ident, -- IN
1062: rec_ident_type => rec_ident_type, -- IN
1063: rec_frame_type => rec_frame_type, -- IN
1064: rec_is_rtr => rec_is_rtr, -- IN
1065: rec_ivld => rec_ivld, -- IN
1066: store_metadata => store_metadata, -- IN
1067: store_data => store_data, -- IN
1068: rec_valid => rec_valid, -- IN
1069: rec_abort => rec_abort, -- IN
1070:
1071: -- Frame filters output
1072: store_metadata_f => store_metadata_f, -- OUT
1073: store_data_f => store_data_f, -- OUT
1074: rec_valid_f => rec_valid_f, -- OUT
1075: rec_abort_f => rec_abort_f -- OUT
1076: );
1077:
1078: -----------------------------------------------------------------------------------------------
1079: -- Interrrupt Manager
1080: -----------------------------------------------------------------------------------------------
1081: int_manager_inst : entity ctu_can_fd_rtl.int_manager
1082: generic map(
1083: G_INT_COUNT => C_INT_COUNT,
1084: G_TXT_BUFFER_COUNT => txt_buffer_count
1085: )
1086: port map(
1087: -- Clock and Asynchronous reset
1088: clk_sys => clk_sys, -- IN
1089:
1090: -- WARNING:
1091: -- Interrupt manager MUST be reset by Soft reset, not by Core
1092: -- reset since it holds the actual values of Interrupt Enable
1093: -- and Interrupt Mask. These are considered as registers and
1094: -- they must be settable when the core is disabled!
1095: res_n => res_soft_n, -- IN
1096:
1097: -- Interrupt sources
1098: err_detected => err_detected, -- IN
1099: fcs_changed => fcs_changed, -- IN
1100: err_warning_limit_pulse => err_warning_limit_pulse, -- IN
1101: arbitration_lost => arbitration_lost, -- IN
1102: tran_valid => tran_valid, -- IN
1103: br_shifted => br_shifted, -- IN
1104: rx_data_overrun => rx_data_overrun, -- IN
1105: rec_valid => rec_valid, -- IN
1106: rx_full => rx_full, -- IN
1107: rx_empty => rx_empty, -- IN
1108: txtb_hw_cmd_int => txtb_hw_cmd_int, -- IN
1109: is_overload => pc_dbg.is_overload, -- IN
1110:
1111: -- Memory registers Interface
1112: mr_int_ena_set_int_ena_set => mr_ctrl_out.int_ena_set_int_ena_set, -- IN
1113: mr_int_ena_clr_int_ena_clr => mr_ctrl_out.int_ena_clr_int_ena_clr, -- IN
1114: mr_int_mask_set_int_mask_set => mr_ctrl_out.int_mask_set_int_mask_set, -- IN
1115: mr_int_mask_clr_int_mask_clr => mr_ctrl_out.int_mask_clr_int_mask_clr, -- IN
1116:
1117: mr_int_stat_rxi_i => mr_ctrl_out.int_stat_rxi, -- IN
1118: mr_int_stat_txi_i => mr_ctrl_out.int_stat_txi, -- IN
1119: mr_int_stat_ewli_i => mr_ctrl_out.int_stat_ewli, -- IN
1120: mr_int_stat_doi_i => mr_ctrl_out.int_stat_doi, -- IN
1121: mr_int_stat_fcsi_i => mr_ctrl_out.int_stat_fcsi, -- IN
1122: mr_int_stat_ali_i => mr_ctrl_out.int_stat_ali, -- IN
1123: mr_int_stat_bei_i => mr_ctrl_out.int_stat_bei, -- IN
1124: mr_int_stat_ofi_i => mr_ctrl_out.int_stat_ofi, -- IN
1125: mr_int_stat_rxfi_i => mr_ctrl_out.int_stat_rxfi, -- IN
1126: mr_int_stat_bsi_i => mr_ctrl_out.int_stat_bsi, -- IN
1127: mr_int_stat_rbnei_i => mr_ctrl_out.int_stat_rbnei, -- IN
1128: mr_int_stat_txbhci_i => mr_ctrl_out.int_stat_txbhci, -- IN
1129:
1130: -- Reads from Interrupt registers
1131: mr_int_stat_rxi_o => mr_int_stat_rxi_o, -- OUT
1132: mr_int_stat_txi_o => mr_int_stat_txi_o, -- OUT
1133: mr_int_stat_ewli_o => mr_int_stat_ewli_o, -- OUT
1134: mr_int_stat_doi_o => mr_int_stat_doi_o, -- OUT
1135: mr_int_stat_fcsi_o => mr_int_stat_fcsi_o, -- OUT
1136: mr_int_stat_ali_o => mr_int_stat_ali_o, -- OUT
1137: mr_int_stat_bei_o => mr_int_stat_bei_o, -- OUT
1138: mr_int_stat_ofi_o => mr_int_stat_ofi_o, -- OUT
1139: mr_int_stat_rxfi_o => mr_int_stat_rxfi_o, -- OUT
1140: mr_int_stat_bsi_o => mr_int_stat_bsi_o, -- OUT
1141: mr_int_stat_rbnei_o => mr_int_stat_rbnei_o, -- OUT
1142: mr_int_stat_txbhci_o => mr_int_stat_txbhci_o, -- OUT
1143:
1144: mr_int_ena_set_int_ena_set_o => mr_int_ena_set_int_ena_set_o, -- OUT
1145: mr_int_mask_set_int_mask_set_o => mr_int_mask_set_int_mask_set_o, -- OUT
1146:
1147: -- Interrupt output
1148: int => int -- OUT
1149: );
1150:
1151: -----------------------------------------------------------------------------------------------
1152: -- CAN Core
1153: -----------------------------------------------------------------------------------------------
1154: can_core_inst : entity ctu_can_fd_rtl.can_core
1155: generic map (
1156: G_SAMPLE_TRIGGER_COUNT => C_SAMPLE_TRIGGER_COUNT,
1157: G_CTRL_CTR_WIDTH => C_CTRL_CTR_WIDTH,
1158: G_RETR_LIM_CTR_WIDTH => C_RETR_LIM_CTR_WIDTH,
1159: G_ERR_VALID_PIPELINE => C_ERR_VALID_PIPELINE,
1160: G_CRC15_POL => C_CRC15_POL,
1161: G_CRC17_POL => C_CRC17_POL,
1162: G_CRC21_POL => C_CRC21_POL,
1163: G_SUP_TRAFFIC_CTRS => sup_traffic_ctrs
1164: )
1165: port map (
1166: -- Clock and Asynchronous reset
1167: clk_sys => clk_sys, -- IN
1168: res_n => res_core_n, -- IN
1169:
1170: -- DFT support
1171: scan_enable => scan_enable, -- IN
1172:
1173: -- Memory registers interface
1174: mr_mode_acf => mr_ctrl_out.mode_acf, -- IN
1175: mr_mode_stm => mr_ctrl_out.mode_stm, -- IN
1176: mr_mode_bmm => mr_ctrl_out.mode_bmm, -- IN
1177: mr_mode_fde => mr_ctrl_out.mode_fde, -- IN
1178: mr_mode_rom => mr_ctrl_out.mode_rom, -- IN
1179: mr_mode_tstm => mr_ctrl_out.mode_tstm, -- IN
1180: mr_mode_sam => mr_ctrl_out.mode_sam, -- IN
1181:
1182: mr_settings_ena => mr_ctrl_out.settings_ena, -- IN
1183: mr_settings_nisofd => mr_ctrl_out.settings_nisofd, -- IN
1184: mr_settings_rtrth => mr_ctrl_out.settings_rtrth, -- IN
1185: mr_settings_rtrle => mr_ctrl_out.settings_rtrle, -- IN
1186: mr_settings_ilbp => mr_ctrl_out.settings_ilbp, -- IN
1187: mr_settings_pex => mr_ctrl_out.settings_pex, -- IN
1188:
1189: mr_command_ercrst => mr_ctrl_out.command_ercrst, -- IN
1190: mr_command_rxfcrst => mr_ctrl_out.command_rxfcrst, -- IN
1191: mr_command_txfcrst => mr_ctrl_out.command_txfcrst, -- IN
1192: mr_command_cpexs => mr_ctrl_out.command_cpexs, -- IN
1193:
1194: mr_ssp_cfg_ssp_src => mr_ctrl_out.ssp_cfg_ssp_src, -- IN
1195:
1196: mr_ewl_ew_limit => mr_ctrl_out.ewl_ew_limit, -- IN
1197: mr_erp_erp_limit => mr_ctrl_out.erp_erp_limit, -- IN
1198:
1199: mr_ctr_pres_ctpv => mr_ctrl_out.ctr_pres_ctpv, -- IN
1200: mr_ctr_pres_ptx => mr_ctrl_out.ctr_pres_ptx, -- IN
1201: mr_ctr_pres_prx => mr_ctrl_out.ctr_pres_prx, -- IN
1202: mr_ctr_pres_enorm => mr_ctrl_out.ctr_pres_enorm, -- IN
1203: mr_ctr_pres_efd => mr_ctrl_out.ctr_pres_efd, -- IN
1204:
1205: -- Status signals
1206: cc_stat => cc_stat, -- OUT
1207: pc_dbg => pc_dbg, -- OUT
1208:
1209: -- Tx Arbitrator and TXT Buffers interface
1210: tran_word => tran_word, -- IN
1211: tran_dlc => tran_dlc, -- IN
1212: tran_is_rtr => tran_is_rtr, -- IN
1213: tran_ident_type => tran_ident_type, -- IN
1214: tran_frame_type => tran_frame_type, -- IN
1215: tran_brs => tran_brs, -- IN
1216: tran_identifier => tran_identifier, -- IN
1217: tran_frame_test => tran_frame_test, -- IN
1218: tran_frame_valid => tran_frame_valid, -- IN
1219: tran_frame_parity_error => tran_frame_parity_error, -- IN
1220: txtb_hw_cmd => txtb_hw_cmd, -- OUT
1221: txtb_changed => txtb_changed, -- IN
1222: txtb_ptr => txtb_ptr, -- OUT
1223: txtb_clk_en => txtb_clk_en, -- OUT
1224:
1225: -- Recieve Buffer and Message Filter Interface
1226: rec_ident => rec_ident, -- OUT
1227: rec_dlc => rec_dlc, -- OUT
1228: rec_ident_type => rec_ident_type, -- OUT
1229: rec_frame_type => rec_frame_type, -- OUT
1230: rec_lbpf => rec_lbpf, -- OUT
1231: rec_is_rtr => rec_is_rtr, -- OUT
1232: rec_brs => rec_brs, -- OUT
1233: rec_esi => rec_esi, -- OUT
1234: rec_valid => rec_valid, -- OUT
1235: rec_ivld => rec_ivld, -- OUT
1236: store_metadata => store_metadata, -- OUT
1237: store_data => store_data, -- OUT
1238: store_data_word => store_data_word, -- OUT
1239: rec_abort => rec_abort, -- OUT
1240: sof_pulse => sof_pulse, -- OUT
1241:
1242: -- Interrupt Manager Interface
1243: arbitration_lost => arbitration_lost, -- OUT
1244: tran_valid => tran_valid, -- OUT
1245: br_shifted => br_shifted, -- OUT
1246: err_detected => err_detected, -- OUT
1247: fcs_changed => fcs_changed, -- OUT
1248: err_warning_limit_pulse => err_warning_limit_pulse, -- OUT
1249:
1250: -- Prescaler interface
1251: rx_triggers => rx_triggers, -- IN
1252: tx_trigger => tx_trigger, -- IN
1253: sync_control => sync_control, -- OUT
1254: no_pos_resync => no_pos_resync, -- OUT
1255: sp_control => sp_control, -- OUT
1256: nbt_ctrs_en => nbt_ctrs_en, -- OUT
1257: dbt_ctrs_en => dbt_ctrs_en, -- OUT
1258:
1259: -- CAN Bus serial data stream
1260: rx_data_wbs => rx_data_wbs, -- IN
1261: tx_data_wbs => tx_data_wbs, -- OUT
1262:
1263: -- Others
1264: ssp_reset => ssp_reset, -- OUT
1265: tran_delay_meas => tran_delay_meas, -- OUT
1266: bit_err => bit_err, -- IN
1267: btmc_reset => btmc_reset, -- OUT
1268: dbt_measure_start => dbt_measure_start, -- OUT
1269: gen_first_ssp => gen_first_ssp, -- OUT
1270: sync_edge => sync_edge, -- IN
1271: bit_err_enable => bit_err_enable, -- OUT
1272: pc_rx_trigger => pc_rx_trigger -- OUT
1273: );
1274:
1275:
1276: -----------------------------------------------------------------------------------------------
1277: -- Prescaler
1278: -----------------------------------------------------------------------------------------------
1279: prescaler_inst : entity ctu_can_fd_rtl.prescaler
1280: generic map (
1281: G_TSEG1_NBT_WIDTH => C_TSEG1_NBT_WIDTH,
1282: G_TSEG2_NBT_WIDTH => C_TSEG2_NBT_WIDTH,
1283: G_BRP_NBT_WIDTH => C_BRP_NBT_WIDTH,
1284: G_SJW_NBT_WIDTH => C_SJW_NBT_WIDTH,
1285: G_TSEG1_DBT_WIDTH => C_TSEG1_DBT_WIDTH,
1286: G_TSEG2_DBT_WIDTH => C_TSEG2_DBT_WIDTH,
1287: G_BRP_DBT_WIDTH => C_BRP_DBT_WIDTH,
1288: G_SJW_DBT_WIDTH => C_SJW_DBT_WIDTH,
1289: G_SAMPLE_TRIGGER_COUNT => C_SAMPLE_TRIGGER_COUNT
1290: )
1291: port map (
1292: -- Clock and Asynchronous reset
1293: clk_sys => clk_sys, -- IN
1294: res_n => res_core_n, -- IN
1295:
1296: -- Memory registers interface
1297: mr_settings_ena => mr_ctrl_out.settings_ena, -- IN
1298:
1299: mr_btr_prop => mr_ctrl_out.btr_prop, -- IN
1300: mr_btr_ph1 => mr_ctrl_out.btr_ph1, -- IN
1301: mr_btr_ph2 => mr_ctrl_out.btr_ph2, -- IN
1302: mr_btr_brp => mr_ctrl_out.btr_brp, -- IN
1303: mr_btr_sjw => mr_ctrl_out.btr_sjw, -- IN
1304:
1305: mr_btr_fd_prop_fd => mr_ctrl_out.btr_fd_prop_fd, -- IN
1306: mr_btr_fd_ph1_fd => mr_ctrl_out.btr_fd_ph1_fd, -- IN
1307: mr_btr_fd_ph2_fd => mr_ctrl_out.btr_fd_ph2_fd, -- IN
1308: mr_btr_fd_brp_fd => mr_ctrl_out.btr_fd_brp_fd, -- IN
1309: mr_btr_fd_sjw_fd => mr_ctrl_out.btr_fd_sjw_fd, -- IN
1310:
1311: -- Control Interface
1312: sync_edge => sync_edge, -- IN
1313: sp_control => sp_control, -- IN
1314: sync_control => sync_control, -- IN
1315: no_pos_resync => no_pos_resync, -- IN
1316: nbt_ctrs_en => nbt_ctrs_en, -- IN
1317: dbt_ctrs_en => dbt_ctrs_en, -- IN
1318:
1319: -- Trigger signals
1320: rx_triggers => rx_triggers, -- OUT
1321: tx_trigger => tx_trigger, -- OUT
1322:
1323: -- Status outputs
1324: tq_edge => tq_edge -- OUT
1325: );
1326:
1327:
1328: -----------------------------------------------------------------------------------------------
1329: -- Bus Sampling
1330: -----------------------------------------------------------------------------------------------
1331: bus_sampling_inst : entity ctu_can_fd_rtl.bus_sampling
1332: generic map(
1333: G_SSP_DELAY_SAT_VAL => C_SSP_DELAY_SAT_VAL,
1334: G_TX_CACHE_DEPTH => C_TX_CACHE_DEPTH,
1335: G_TX_CACHE_PTR_WIDTH => C_TX_CACHE_PTR_WIDTH,
1336: G_TRV_CTR_WIDTH => C_TRV_CTR_WIDTH,
1337: G_SSP_POS_WIDTH => C_SSP_POS_WIDTH,
1338: G_SSP_OFFSET_WIDTH => C_SSP_OFFSET_WIDTH,
1339: G_SSP_CTRS_WIDTH => C_SSP_CTRS_WIDTH
1340: )
1341: port map(
1342: -- Clock and Async reset
1343: clk_sys => clk_sys, -- IN
1344: res_n => res_core_n, -- IN
1345:
1346: -- DFT support
1347: scan_enable => scan_enable, -- IN
1348:
1349: -- Physical layer interface
1350: can_rx => can_rx, -- IN
1351: can_tx => can_tx, -- OUT
1352:
1353: -- Memory registers interface
1354: mr_settings_ena => mr_ctrl_out.settings_ena, -- IN
1355: mr_ssp_cfg_ssp_offset => mr_ctrl_out.ssp_cfg_ssp_offset, -- IN
1356: mr_ssp_cfg_ssp_src => mr_ctrl_out.ssp_cfg_ssp_src, -- IN
1357:
1358: trv_delay => trv_delay, -- OUT
1359:
1360: -- Prescaler interface
1361: rx_trigger => rx_triggers(1), -- IN
1362: tx_trigger => tx_trigger, -- IN
1363: sync_edge => sync_edge, -- OUT
1364: tq_edge => tq_edge, -- IN
1365:
1366: -- CAN Core Interface
1367: tx_data_wbs => tx_data_wbs, -- IN
1368: rx_data_wbs => rx_data_wbs, -- OUT
1369: sp_control => sp_control, -- IN
1370: ssp_reset => ssp_reset, -- IN
1371: tran_delay_meas => tran_delay_meas, -- IN
1372: bit_err => bit_err, -- OUT
1373: btmc_reset => btmc_reset, -- IN
1374: dbt_measure_start => dbt_measure_start, -- IN
1375: gen_first_ssp => gen_first_ssp, -- IN
1376: bit_err_enable => bit_err_enable -- OUT
1377: );
1378:
1379: -- <RELEASE_OFF>
1380: -- pragma translate_off
1381: -----------------------------------------------------------------------------------------------
1382: -----------------------------------------------------------------------------------------------
1383: -- Assertions
1384: -----------------------------------------------------------------------------------------------
1385: -----------------------------------------------------------------------------------------------
1386:
1387: -- psl default clock is rising_edge(clk_sys);
1388:
1389: -- psl no_tx_dominant_when_disabled_asrt : assert never
1390: -- (mr_ctrl_out.settings_ena = '0' and can_tx = DOMINANT)
1391: -- report "Dominant bit can't be transmitted when Node is disabled!";
1392:
1393: -- psl no_tx_dominant_when_bus_monitoring_asrt : assert never
1394: -- (mr_ctrl_out.mode_bmm = '1' and can_tx = DOMINANT)
1395: -- report "Dominant bit can't be transmitted in Bus monitoring mode!";
1396:
1397: -- Each TXT Buffer should have been unlocked already when unit is
1398: -- transmitting overload frame! This-way we can be sure that no we can
1399: -- block unlock command in Protocol control FSM in overload frames!
1400:
1401: -- coverage off
1402: txtb_asr_gen : for i in 0 to txt_buffer_count - 1 generate
1403: begin
1404:
1405: process (txtb_state, pc_dbg.is_overload)
1406: begin
1407: if ((((txtb_state(i) = TXT_TRAN) or (txtb_state(i) = TXT_ABTP))) and
1408: (pc_dbg.is_overload = '1')) then
1409: report "TXT Buffer should have been unlocked when node is in Overload frame!"
1410: severity error;
1411: end if;
1412: end process;
1413:
1414: end generate;
1415: -- coverage on
1416:
1417: -- pragma translate_on
1418: -- <RELEASE_ON>
1419:
1420: end architecture;