NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.BIT_ERR_DETECTOR_INST	100.0 % (24/24)	100.0 % (24/24)	100.0 % (38/38)	100.0 % (56/56)	N.A.	N.A.	100.0 % (142/142)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

163:    bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and 
164:                                       sample_sec = '1' and 
165:                                       bit_err_enable = '1') 
166:                                 else 
167:                             '0';

Count: 3506845
Threshold: 1

Signal assignment statement:

163: bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and
Count: 102729
Threshold: 1

Signal assignment statement:

167: '0';
Count: 3404116
Threshold: 1

If statement:

174:    bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else 
175:                          '1' when (bit_err_ssp_condition = '1') else 
176:          bit_err_ssp_capt_q;

Count: 44311339
Threshold: 1

Signal assignment statement:

174: bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else
Count: 22153494
Threshold: 1

Signal assignment statement:

175: '1' when (bit_err_ssp_condition = '1') else
Count: 34345
Threshold: 1

Signal assignment statement:

176: bit_err_ssp_capt_q;
Count: 22123500
Threshold: 1

If statement:

180:        if (res_n = '0') then 
181:            bit_err_ssp_capt_q <= '0'; 
182:        elsif (rising_edge(clk_sys)) then 
183:            bit_err_ssp_capt_q <= bit_err_ssp_capt_d; 
184:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

181: bit_err_ssp_capt_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

183: bit_err_ssp_capt_q <= bit_err_ssp_capt_d;
Count: 526374300
Threshold: 1

If statement:

192:    bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and 
193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1')) 
194:                             else 
195:                         '0';

Count: 44370099
Threshold: 1

Signal assignment statement:

192: bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and
Count: 69417
Threshold: 1

Signal assignment statement:

195: '0';
Count: 44300682
Threshold: 1

If statement:

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and 
199:                                    rx_trigger = '1' and 
200:                                    bit_err_enable = '1') 
201:                              else 
202:                          '0';

Count: 48431708
Threshold: 1

Signal assignment statement:

197: bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and
Count: 871682
Threshold: 1

Signal assignment statement:

202: '0';
Count: 47560026
Threshold: 1

If statement:

207:    bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else 
208:                 '1' when (bit_err_ssp_valid = '1') else 
209:                 '1' when (bit_err_norm_valid = '1') else 
210:                 '0';

Count: 1899882
Threshold: 1

Signal assignment statement:

207: bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else
Count: 8072
Threshold: 1

Signal assignment statement:

208: '1' when (bit_err_ssp_valid = '1') else
Count: 69382
Threshold: 1

Signal assignment statement:

209: '1' when (bit_err_norm_valid = '1') else
Count: 871682
Threshold: 1

Signal assignment statement:

210: '0';
Count: 950746
Threshold: 1

If statement:

217:        if (res_n = '0') then 
218:            bit_err_q <= '0'; 
219:        elsif (rising_edge(clk_sys)) then 
220:            bit_err_q <= bit_err_d; 
221:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

218: bit_err_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

220: bit_err_q <= bit_err_d;
Count: 526374300
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

163:    bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and 
164:                                       sample_sec = '1' and 
165:                                       bit_err_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	102729	1
Bin	False	3404116	1

"if" / "when" / "else" condition:

174: bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	22153494	1
Bin	False	22157845	1

"if" / "when" / "else" condition:

175: '1' when (bit_err_ssp_condition = '1') else

	Evaluated to	Count	Threshold
Bin	True	34345	1
Bin	False	22123500	1

"if" / "when" / "else" condition:

180: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

182: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

192:    bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and 
193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1'))

	Evaluated to	Count	Threshold
Bin	True	69417	1
Bin	False	44300682	1

"if" / "when" / "else" condition:

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and 
199:                                    rx_trigger = '1' and 
200:                                    bit_err_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	871682	1
Bin	False	47560026	1

"if" / "when" / "else" condition:

207: bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else

	Evaluated to	Count	Threshold
Bin	True	8072	1
Bin	False	1891810	1

"if" / "when" / "else" condition:

208: '1' when (bit_err_ssp_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	69382	1
Bin	False	1822428	1

"if" / "when" / "else" condition:

209: '1' when (bit_err_norm_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	871682	1
Bin	False	950746	1

"if" / "when" / "else" condition:

217: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

219: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SP_CONTROL(1)

	From	To	Count	Threshold
Bin	0	1	4206	1
Bin	1	0	5806	1

Port:

SP_CONTROL(0)

	From	To	Count	Threshold
Bin	0	1	25548	1
Bin	1	0	27148	1

Port:

RX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	22084127	1
Bin	1	0	22085727	1

Port:

SAMPLE_SEC

	From	To	Count	Threshold
Bin	0	1	190334	1
Bin	1	0	191934	1

Port:

BIT_ERR_ENABLE

	From	To	Count	Threshold
Bin	0	1	66912	1
Bin	1	0	65320	1

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

DATA_TX

	From	To	Count	Threshold
Bin	0	1	635336	1
Bin	1	0	633738	1

Port:

DATA_TX_DELAYED

	From	To	Count	Threshold
Bin	0	1	97563	1
Bin	1	0	95963	1

Port:

DATA_RX_SYNCED

	From	To	Count	Threshold
Bin	0	1	1400896	1
Bin	1	0	1399296	1

Port:

BIT_ERR

	From	To	Count	Threshold
Bin	0	1	9381	1
Bin	1	0	10981	1

Signal:

BIT_ERR_D

	From	To	Count	Threshold
Bin	0	1	941064	1
Bin	1	0	942664	1

Signal:

BIT_ERR_Q

	From	To	Count	Threshold
Bin	0	1	9381	1
Bin	1	0	10981	1

Signal:

BIT_ERR_SSP_CAPT_D

	From	To	Count	Threshold
Bin	0	1	34018	1
Bin	1	0	35618	1

Signal:

BIT_ERR_SSP_CAPT_Q

	From	To	Count	Threshold
Bin	0	1	474	1
Bin	1	0	2074	1

Signal:

BIT_ERR_SSP_VALID

	From	To	Count	Threshold
Bin	0	1	69382	1
Bin	1	0	70982	1

Signal:

BIT_ERR_SSP_CONDITION

	From	To	Count	Threshold
Bin	0	1	102729	1
Bin	1	0	104329	1

Signal:

BIT_ERR_NORM_VALID

	From	To	Count	Threshold
Bin	0	1	871682	1
Bin	1	0	873282	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"/=" expression

163: bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and

	Evaluated to	Count	Threshold
Bin	False	1829701	1
Bin	True	1677144	1

"=" expression

164: sample_sec = '1' and

	Evaluated to	Count	Threshold
Bin	False	3213063	1
Bin	True	293782	1

"and" expression

163:    bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and 
164:                                       sample_sec = '1' and

	LHS	RHS	Count	Threshold
Bin	False	True	190093	1
Bin	True	False	1573455	1
Bin	True	True	103689	1

"=" expression

165: bit_err_enable = '1')

	Evaluated to	Count	Threshold
Bin	False	1904480	1
Bin	True	1602365	1

"and" expression

163:    bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and 
164:                                       sample_sec = '1' and 
165:                                       bit_err_enable = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	1499636	1
Bin	True	False	960	1
Bin	True	True	102729	1

"=" expression

174: bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	22157845	1
Bin	True	22153494	1

"=" expression

175: '1' when (bit_err_ssp_condition = '1') else

	Evaluated to	Count	Threshold
Bin	False	22123500	1
Bin	True	34345	1

"=" expression

180: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

192: bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and

	Evaluated to	Count	Threshold
Bin	False	22216605	1
Bin	True	22153494	1

"and" expression

192:    bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and 
                                       <------------LHS------------>     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	21705066	1
Bin	True	False	450536	1
Bin	True	True	448428	1

"=" expression

193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1'))

	Evaluated to	Count	Threshold
Bin	False	44368440	1
Bin	True	1659	1

"=" expression

193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1'))

	Evaluated to	Count	Threshold
Bin	False	44266811	1
Bin	True	103288	1

"or" expression

193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1')) 
                                        <---------LHS---------->    <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	44265661	1
Bin	False	True	102779	1
Bin	True	False	1150	1

"and" expression

192:    bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and 
193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1'))

	LHS	RHS	Count	Threshold
Bin	False	True	35021	1
Bin	True	False	379011	1
Bin	True	True	69417	1

"/=" expression

198: data_rx_synced /= data_tx and

	Evaluated to	Count	Threshold
Bin	False	35216906	1
Bin	True	13214802	1

"and" expression

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and

	LHS	RHS	Count	Threshold
Bin	False	True	227783	1
Bin	True	False	34462034	1
Bin	True	True	12987019	1

"=" expression

199: rx_trigger = '1' and

	Evaluated to	Count	Threshold
Bin	False	25078640	1
Bin	True	23353068	1

"and" expression

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and 
199:                                    rx_trigger = '1' and

	LHS	RHS	Count	Threshold
Bin	False	True	17258652	1
Bin	True	False	6892603	1
Bin	True	True	6094416	1

"=" expression

200: bit_err_enable = '1')

	Evaluated to	Count	Threshold
Bin	False	36723393	1
Bin	True	11708315	1

"and" expression

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and 
199:                                    rx_trigger = '1' and 
200:                                    bit_err_enable = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	10836633	1
Bin	True	False	5222734	1
Bin	True	True	871682	1

"=" expression

207: bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else

	Evaluated to	Count	Threshold
Bin	False	1891810	1
Bin	True	8072	1

"=" expression

208: '1' when (bit_err_ssp_valid = '1') else

	Evaluated to	Count	Threshold
Bin	False	1822428	1
Bin	True	69382	1

"=" expression

209: '1' when (bit_err_norm_valid = '1') else

	Evaluated to	Count	Threshold
Bin	False	950746	1
Bin	True	871682	1

"=" expression

217: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.BIT_ERR_DETECTOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bit_err_detector.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"/=" expression

"=" expression

"and" expression

"=" expression

"and" expression

"=" expression

"=" expression