NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.BIT_ERR_DETECTOR_INST	100.0 % (25/25)	100.0 % (24/24)	100.0 % (38/38)	100.0 % (56/56)	N.A.	N.A.	100.0 % (143/143)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.BIT_ERR_DETECTOR_INST

100.0 % (25/25)

100.0 % (24/24)

100.0 % (38/38)

100.0 % (56/56)

N.A.

100.0 % (143/143)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 163 to 167:

163:    bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and 
164:                                       sample_sec = '1' and 
165:                                       bit_err_enable = '1') 
166:                                 else 
167:                             '0';

Count: 3419741
Threshold: 1

Signal assignment statement on line 163:

163: bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and
Count: 86431
Threshold: 1

Signal assignment statement on line 167:

167: '0';
Count: 3333310
Threshold: 1

If statement on lines 174 to 176:

174:    bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else 
175:                          '1' when (bit_err_ssp_condition = '1') else 
176:          bit_err_ssp_capt_q;

Count: 45682049
Threshold: 1

Signal assignment statement on line 174:

174: bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else
Count: 22833614
Threshold: 1

Signal assignment statement on line 175:

175: '1' when (bit_err_ssp_condition = '1') else
Count: 32501
Threshold: 1

Signal assignment statement on line 176:

176: bit_err_ssp_capt_q;
Count: 22815934
Threshold: 1

If statement on lines 180 to 184:

180:        if (res_n = '0') then 
181:            bit_err_ssp_capt_q <= '0'; 
182:        elsif (rising_edge(clk_sys)) then 
183:            bit_err_ssp_capt_q <= bit_err_ssp_capt_d; 
184:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 181:

181: bit_err_ssp_capt_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 183:

183: bit_err_ssp_capt_q <= bit_err_ssp_capt_d;
Count: 543791678
Threshold: 1

If statement on lines 192 to 195:

192:    bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and 
193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1')) 
194:                             else 
195:                         '0';

Count: 45740216
Threshold: 1

Signal assignment statement on line 192:

192: bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and
Count: 55187
Threshold: 1

Signal assignment statement on line 195:

195: '0';
Count: 45685029
Threshold: 1

If statement on lines 197 to 202:

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and 
199:                                    rx_trigger = '1' and 
200:                                    bit_err_enable = '1') 
201:                              else 
202:                          '0';

Count: 49820949
Threshold: 1

Signal assignment statement on line 197:

197: bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and
Count: 883109
Threshold: 1

Signal assignment statement on line 202:

202: '0';
Count: 48937840
Threshold: 1

If statement on lines 207 to 210:

207:    bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else 
208:                 '1' when (bit_err_ssp_valid = '1') else 
209:                 '1' when (bit_err_norm_valid = '1') else 
210:                 '0';

Count: 1894293
Threshold: 1

Signal assignment statement on line 207:

207: bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else
Count: 8072
Threshold: 1

Signal assignment statement on line 208:

208: '1' when (bit_err_ssp_valid = '1') else
Count: 55159
Threshold: 1

Signal assignment statement on line 209:

209: '1' when (bit_err_norm_valid = '1') else
Count: 883109
Threshold: 1

Signal assignment statement on line 210:

210: '0';
Count: 947953
Threshold: 1

If statement on lines 217 to 221:

217:        if (res_n = '0') then 
218:            bit_err_q <= '0'; 
219:        elsif (rising_edge(clk_sys)) then 
220:            bit_err_q <= bit_err_d; 
221:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 218:

218: bit_err_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 220:

220: bit_err_q <= bit_err_d;
Count: 543791678
Threshold: 1

Signal assignment statement on line 225:

225: bit_err <= bit_err_q;
Count: 22772
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 163 to 165:

163:    bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and 
164:                                       sample_sec = '1' and 
165:                                       bit_err_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	86431	1
Bin	False	3333310	1

"if" / "when" / "else" condition on line 174:

174: bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	22833614	1
Bin	False	22848435	1

"if" / "when" / "else" condition on line 175:

175: '1' when (bit_err_ssp_condition = '1') else

	Evaluated to	Count	Threshold
Bin	True	32501	1
Bin	False	22815934	1

"if" / "when" / "else" condition on line 180:

180: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 182:

182: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on lines 192 to 193:

192:    bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and 
193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1'))

	Evaluated to	Count	Threshold
Bin	True	55187	1
Bin	False	45685029	1

"if" / "when" / "else" condition on lines 197 to 200:

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and 
199:                                    rx_trigger = '1' and 
200:                                    bit_err_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	883109	1
Bin	False	48937840	1

"if" / "when" / "else" condition on line 207:

207: bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else

	Evaluated to	Count	Threshold
Bin	True	8072	1
Bin	False	1886221	1

"if" / "when" / "else" condition on line 208:

208: '1' when (bit_err_ssp_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	55159	1
Bin	False	1831062	1

"if" / "when" / "else" condition on line 209:

209: '1' when (bit_err_norm_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	883109	1
Bin	False	947953	1

"if" / "when" / "else" condition on line 217:

217: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 219:

219: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SAMPLE_SEC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BIT_ERR_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_TX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_TX_DELAYED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_RX_SYNCED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

BIT_ERR

	From	To	Count	Threshold
Bin	0	1	9785	1
Bin	1	0	11386	1

Signal:

BIT_ERR_D

	From	To	Count	Threshold
Bin	0	1	938268	1
Bin	1	0	939869	1

Signal:

BIT_ERR_Q

	From	To	Count	Threshold
Bin	0	1	9785	1
Bin	1	0	11386	1

Signal:

BIT_ERR_SSP_CAPT_D

	From	To	Count	Threshold
Bin	0	1	32046	1
Bin	1	0	33647	1

Signal:

BIT_ERR_SSP_CAPT_Q

	From	To	Count	Threshold
Bin	0	1	584	1
Bin	1	0	2185	1

Signal:

BIT_ERR_SSP_VALID

	From	To	Count	Threshold
Bin	0	1	55159	1
Bin	1	0	56760	1

Signal:

BIT_ERR_SSP_CONDITION

	From	To	Count	Threshold
Bin	0	1	86431	1
Bin	1	0	88032	1

Signal:

BIT_ERR_NORM_VALID

	From	To	Count	Threshold
Bin	0	1	883109	1
Bin	1	0	884710	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on lines 163 to 165:

 data_tx_delayed /= data_rx_synced and sample_sec = '1' and bit_err_enable = '1' 
 <------------------------LHS------------------------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	1419569	1
Bin	True	False	748	1
Bin	True	True	86431	1

"and" expression on lines 163 to 164:

 data_tx_delayed /= data_rx_synced and sample_sec = '1' 
 <--------------LHS-------------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	159889	1
Bin	True	False	1559952	1
Bin	True	True	87179	1

"/=" expression on line 163:

data_tx_delayed /= data_rx_synced

	Evaluated to	Count	Threshold
Bin	False	1772610	1
Bin	True	1647131	1

"=" expression on line 164:

sample_sec = '1'

	Evaluated to	Count	Threshold
Bin	False	3172673	1
Bin	True	247068	1

"=" expression on line 165:

bit_err_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	1913741	1
Bin	True	1506000	1

"=" expression on line 174:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	22848435	1
Bin	True	22833614	1

"=" expression on line 175:

bit_err_ssp_condition = '1'

	Evaluated to	Count	Threshold
Bin	False	22815934	1
Bin	True	32501	1

"=" expression on line 180:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"and" expression on lines 192 to 193:

 sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1') 
 <----------------------LHS----------------------->      <-------------------------RHS------------------------->

	LHS	RHS	Count	Threshold
Bin	False	True	33236	1
Bin	True	False	318679	1
Bin	True	True	55187	1

"and" expression on line 192:

 sp_control = SECONDARY_SAMPLE and rx_trigger = '1' 
 <------------LHS------------>     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	22459748	1
Bin	True	False	385682	1
Bin	True	True	373866	1

"=" expression on line 192:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	22906602	1
Bin	True	22833614	1

"or" expression on line 193:

 bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1' 
 <---------LHS---------->    <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	45651793	1
Bin	False	True	86468	1
Bin	True	False	1343	1

"=" expression on line 193:

bit_err_ssp_capt_q = '1'

	Evaluated to	Count	Threshold
Bin	False	45738261	1
Bin	True	1955	1

"=" expression on line 193:

bit_err_ssp_condition = '1'

	Evaluated to	Count	Threshold
Bin	False	45653136	1
Bin	True	87080	1

"and" expression on lines 197 to 200:

 sp_control /= SECONDARY_SAMPLE and data_rx_synced /= data_tx and rx_trigger = '1' and bit_err_enable = '1' 
 <--------------------------------------LHS-------------------------------------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	10764233	1
Bin	True	False	5254318	1
Bin	True	True	883109	1

"and" expression on lines 197 to 199:

 sp_control /= SECONDARY_SAMPLE and data_rx_synced /= data_tx and rx_trigger = '1' 
 <---------------------------LHS---------------------------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	17906875	1
Bin	True	False	6939711	1
Bin	True	True	6137427	1

"and" expression on lines 197 to 198:

 sp_control /= SECONDARY_SAMPLE and data_rx_synced /= data_tx 
 <------------LHS------------->     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	191655	1
Bin	True	False	35919459	1
Bin	True	True	13077138	1

"/=" expression on line 198:

data_rx_synced /= data_tx

	Evaluated to	Count	Threshold
Bin	False	36552156	1
Bin	True	13268793	1

"=" expression on line 199:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	25776647	1
Bin	True	24044302	1

"=" expression on line 200:

bit_err_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	38173607	1
Bin	True	11647342	1

"=" expression on line 207:

mr_settings_ena = CTU_CAN_DISABLED

	Evaluated to	Count	Threshold
Bin	False	1886221	1
Bin	True	8072	1

"=" expression on line 208:

bit_err_ssp_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	1831062	1
Bin	True	55159	1

"=" expression on line 209:

bit_err_norm_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	947953	1
Bin	True	883109	1

"=" expression on line 217:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.BIT_ERR_DETECTOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 163 to 167:

Signal assignment statement on line 163:

Signal assignment statement on line 167:

If statement on lines 174 to 176:

Signal assignment statement on line 174:

Signal assignment statement on line 175:

Signal assignment statement on line 176:

If statement on lines 180 to 184:

Signal assignment statement on line 181:

Signal assignment statement on line 183:

If statement on lines 192 to 195:

Signal assignment statement on line 192:

Signal assignment statement on line 195:

If statement on lines 197 to 202:

Signal assignment statement on line 197:

Signal assignment statement on line 202:

If statement on lines 207 to 210:

Signal assignment statement on line 207:

Signal assignment statement on line 208:

Signal assignment statement on line 209:

Signal assignment statement on line 210:

If statement on lines 217 to 221:

Signal assignment statement on line 218:

Signal assignment statement on line 220:

Signal assignment statement on line 225:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 163 to 165:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 175:

"if" / "when" / "else" condition on line 180:

"if" / "when" / "else" condition on line 182:

"if" / "when" / "else" condition on lines 192 to 193:

"if" / "when" / "else" condition on lines 197 to 200:

"if" / "when" / "else" condition on line 207:

"if" / "when" / "else" condition on line 208:

"if" / "when" / "else" condition on line 209:

"if" / "when" / "else" condition on line 217:

"if" / "when" / "else" condition on line 219:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on lines 163 to 165:

"and" expression on lines 163 to 164:

"/=" expression on line 163:

"=" expression on line 164:

"=" expression on line 165:

"=" expression on line 174:

"=" expression on line 175:

"=" expression on line 180: