NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TXTB_PORT_A_CS_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
TXTB_PORT_A_CS_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
TXTB_PORT_A_CS_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
TXTB_PORT_A_CS_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
TXTB_PORT_A_CS_GEN(4)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
TXTB_PORT_A_CS_GEN(5)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
TXTB_PORT_A_CS_GEN(6)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
TXTB_PORT_A_CS_GEN(7)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
CLK_GATE_CONTROL_REGS_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
CLK_GATE_TEST_REGS_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
CONTROL_REGISTERS_REG_MAP_COMP	100.0 % (2312/2312)	100.0 % (2692/2692)	100.0 % (7926/7926)	100.0 % (2297/2297)	N.A.	100.0 % (73/73)	100.0 % (15300/15300)
TEST_REGISTERS_GEN_TRUE	100.0 % (289/289)	100.0 % (353/353)	100.0 % (1064/1064)	100.0 % (286/286)	N.A.	100.0 % (7/7)	100.0 % (1999/1999)
SOFT_RST_RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
GLOBAL_RST_RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
MT_2_TXT_BUFFS	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
MT_3_TXT_BUFFS	100.0 % (4/4)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (11/11)
MT_4_TXT_BUFFS	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
MT_5_TXT_BUFFS	100.0 % (4/4)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (11/11)
MT_6_TXT_BUFFS	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
MT_7_TXT_BUFFS	100.0 % (4/4)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (11/11)
TXTB_FUNC_COV_GEN(0)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXTB_FUNC_COV_GEN(1)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXTB_FUNC_COV_GEN(2)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXTB_FUNC_COV_GEN(3)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXTB_FUNC_COV_GEN(4)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXTB_FUNC_COV_GEN(5)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXTB_FUNC_COV_GEN(6)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
TXTB_FUNC_COV_GEN(7)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST	100.0 % (153/153)	100.0 % (40/40)	100.0 % (5550/5550)	98.6 % (72/73)	N.A.	N.A.	99.9 % (5815/5816)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 351:

351: txtb_port_a_data_in <= data_in;
Count: 2217598
Threshold: 1

Signal assignment statement on line 357:

357: txtb_port_a_address <= adress(6 downto 2);
Count: 55054226
Threshold: 1

If statement on lines 362 to 363:

362:    scs_and_swr <= '1' when (scs = '1' and swr = '1') else 
363:                   '0';

Count: 94966182
Threshold: 1

Signal assignment statement on line 362:

362: scs_and_swr <= '1' when (scs = '1' and swr = '1') else
Count: 801022
Threshold: 1

Signal assignment statement on line 363:

363: '0';
Count: 94165160
Threshold: 1

Signal assignment statement on line 381:

381: txtb_port_a_be <= sbe;
Count: 55052625
Threshold: 1

If statement on lines 386 to 389:

386:    control_registers_cs <= '1' when (adress(11 downto 8) = CONTROL_REGISTERS_BLOCK) and 
387:                                     (scs = '1') 
388:                                else 
389:                            '0';

Count: 94967783
Threshold: 1

Signal assignment statement on line 386:

386: control_registers_cs <= '1' when (adress(11 downto 8) = CONTROL_REGISTERS_BLOCK) and
Count: 19215496
Threshold: 1

Signal assignment statement on line 389:

389: '0';
Count: 75752287
Threshold: 1

If statement on lines 391 to 394:

391:    test_registers_cs <= '1' when (adress(11 downto 8) = TEST_REGISTERS_BLOCK) and 
392:                                  (scs = '1') 
393:                             else 
394:                         '0';

Count: 94967783
Threshold: 1

Signal assignment statement on line 391:

391: test_registers_cs <= '1' when (adress(11 downto 8) = TEST_REGISTERS_BLOCK) and
Count: 313176
Threshold: 1

Signal assignment statement on line 394:

394: '0';
Count: 94654607
Threshold: 1

If statement on lines 401 to 407:

401:        if (res_n = '0') then 
402:            control_registers_cs_reg  <= '0'; 
...
406:            test_registers_cs_reg <= test_registers_cs; 
407:        end if;

Count: 1090016402
Threshold: 1

Signal assignment statement on line 402:

402: control_registers_cs_reg <= '0';
Count: 50414
Threshold: 1

Signal assignment statement on line 403:

403: test_registers_cs_reg <= '0';
Count: 50414
Threshold: 1

Signal assignment statement on line 405:

405: control_registers_cs_reg <= control_registers_cs;
Count: 544977583
Threshold: 1

Signal assignment statement on line 406:

406: test_registers_cs_reg <= test_registers_cs;
Count: 544977583
Threshold: 1

If statement on lines 414 to 416:

414:    data_out <= control_registers_rdata when (control_registers_cs_reg = '1') else 
415:                   test_registers_rdata when (test_registers_cs_reg = '1') else 
416:                        (others => '0');

Count: 21021117
Threshold: 1

Signal assignment statement on line 414:

414: data_out <= control_registers_rdata when (control_registers_cs_reg = '1') else
Count: 10640049
Threshold: 1

Signal assignment statement on line 415:

415: test_registers_rdata when (test_registers_cs_reg = '1') else
Count: 101999
Threshold: 1

Signal assignment statement on line 416:

416: (others => '0');
Count: 10279069
Threshold: 1

If statement on lines 423 to 425:

423:    control_regs_clk_en <= '1' when (srd = '1' or swr = '1') and (control_registers_cs = '1') 
424:                               else 
425:                           '0';

Count: 93485218
Threshold: 1

Signal assignment statement on line 423:

423: control_regs_clk_en <= '1' when (srd = '1' or swr = '1') and (control_registers_cs = '1')
Count: 19215496
Threshold: 1

Signal assignment statement on line 425:

425: '0';
Count: 74269722
Threshold: 1

If statement on lines 427 to 429:

427:    test_regs_clk_en <= '1' when (srd = '1' or swr = '1') and (test_registers_cs = '1') 
428:                            else 
429:                        '0';

Count: 55680578
Threshold: 1

Signal assignment statement on line 427:

427: test_regs_clk_en <= '1' when (srd = '1' or swr = '1') and (test_registers_cs = '1')
Count: 313176
Threshold: 1

Signal assignment statement on line 429:

429: '0';
Count: 55367402
Threshold: 1

Signal assignment statement on line 485:

485: mr_ctrl_out <= mr_ctrl_out_i;
Count: 499194
Threshold: 1

Signal assignment statement on line 549:

549: mr_tst_out <= mr_tst_out_i;
Count: 202562
Threshold: 1

Signal assignment statement on line 555:

555: reg_lock_1_active <= not mr_ctrl_out_i.mode_tstm;
Count: 5255
Threshold: 1

Signal assignment statement on line 558:

558: reg_lock_2_active <= mr_ctrl_out_i.settings_ena;
Count: 16156
Threshold: 1

Signal assignment statement on line 569:

569: soft_res_d_n <= not mr_ctrl_out_i.mode_rst;
Count: 66626
Threshold: 1

If statement on lines 590 to 592:

590:    res_core_d_n <= '0' when (mr_ctrl_out_i.mode_rst = '1' or mr_ctrl_out_i.settings_ena = '0') 
591:                        else 
592:                    '1';

Count: 81181
Threshold: 1

Signal assignment statement on line 590:

590: res_core_d_n <= '0' when (mr_ctrl_out_i.mode_rst = '1' or mr_ctrl_out_i.settings_ena = '0')
Count: 19724
Threshold: 1

Signal assignment statement on line 592:

592: '1';
Count: 61457
Threshold: 1

Signal assignment statement on line 614:

614: res_soft_n <= soft_res_q_n;
Count: 19290
Threshold: 1

Signal assignment statement on line 622:

622: mr_tx_priority(0) <= mr_ctrl_out_i.tx_priority_txt1p;
Count: 3594
Threshold: 1

Signal assignment statement on line 623:

623: mr_tx_command_txbi(0) <= mr_ctrl_out_i.tx_command_txb1;
Count: 16303
Threshold: 1

Signal assignment statement on line 625:

625: mr_tx_priority(1) <= mr_ctrl_out_i.tx_priority_txt2p;
Count: 3643
Threshold: 1

If statement on lines 626 to 628:

626:    mr_tx_command_txbi(1)   <= mr_ctrl_out_i.tx_command_txb2 when (mr_ctrl_out_i.mode_txbbm = '0') 
627:                                                             else 
628:                               mr_ctrl_out_i.tx_command_txb1 or mr_ctrl_out_i.tx_command_txb2;

Count: 17010
Threshold: 1

Signal assignment statement on line 626:

626: mr_tx_command_txbi(1) <= mr_ctrl_out_i.tx_command_txb2 when (mr_ctrl_out_i.mode_txbbm = '0')
Count: 15265
Threshold: 1

Signal assignment statement on line 628:

628:                               mr_ctrl_out_i.tx_command_txb1 or mr_ctrl_out_i.tx_command_txb2;

Count: 1745
Threshold: 1

Signal assignment statement on line 673:

673: mr_ctrl_in.device_id_device_id <= G_DEVICE_ID;
Count: 1601
Threshold: 1

Signal assignment statement on line 676:

676: mr_ctrl_in.version_ver_minor <= G_VERSION_MINOR;
Count: 1601
Threshold: 1

Signal assignment statement on line 677:

677: mr_ctrl_in.version_ver_major <= G_VERSION_MAJOR;
Count: 1601
Threshold: 1

If statement on lines 680 to 682:

680:    mr_ctrl_in.status_idle <= '1' when (cc_stat.is_bus_off = '1') else 
681:                              '1' when (cc_stat.is_idle = '1') else 
682:                              '0';

Count: 117316
Threshold: 1

Signal assignment statement on line 680:

680: mr_ctrl_in.status_idle <= '1' when (cc_stat.is_bus_off = '1') else
Count: 8361
Threshold: 1

Signal assignment statement on line 681:

681: '1' when (cc_stat.is_idle = '1') else
Count: 55892
Threshold: 1

Signal assignment statement on line 682:

682: '0';
Count: 53063
Threshold: 1

Signal assignment statement on line 683:

683: mr_ctrl_in.status_ewl <= cc_stat.status_ewl;
Count: 4757
Threshold: 1

Signal assignment statement on line 684:

684: mr_ctrl_in.status_txs <= cc_stat.is_transmitter;
Count: 43835
Threshold: 1

Signal assignment statement on line 685:

685: mr_ctrl_in.status_rxs <= cc_stat.is_receiver;
Count: 65011
Threshold: 1

Signal assignment statement on line 690:

690: mr_ctrl_in.status_txnf <= '0';
Count: 82056
Threshold: 1

Loop statement on lines 691 to 695:

691:        for i in 0 to G_TXT_BUFFER_COUNT - 1 loop 
692:            if (txtb_state(i) = TXT_ETY) then 
693:                mr_ctrl_in.status_txnf <= '1'; 
694:            end if; 
695:        end loop;

Count: 82056
Threshold: 1

If statement on lines 692 to 694:

692:            if (txtb_state(i) = TXT_ETY) then 
693:                mr_ctrl_in.status_txnf <= '1'; 
694:            end if;

Count: 273782
Threshold: 1

Signal assignment statement on line 693:

693: mr_ctrl_in.status_txnf <= '1';
Count: 142099
Threshold: 1

Signal assignment statement on line 698:

698: mr_ctrl_in.status_rxne <= not rx_empty;
Count: 19601
Threshold: 1

Signal assignment statement on line 699:

699: mr_ctrl_in.status_dor <= rx_data_overrun;
Count: 3264
Threshold: 1

Signal assignment statement on line 700:

700: mr_ctrl_in.status_eft <= pc_dbg.is_err;
Count: 57465
Threshold: 1

Signal assignment statement on line 701:

701: mr_ctrl_in.status_pexs <= cc_stat.status_pexs;
Count: 3352
Threshold: 1

Signal assignment statement on line 702:

702: mr_ctrl_in.status_rxpe <= rx_parity_error;
Count: 3220
Threshold: 1

If statement on lines 707 to 728:

707:        if (soft_res_q_n = '0') then 
708:            mr_ctrl_in.status_txpe <= '0'; 
...
727:            end if; 
728:        end if;

Count: 1090019739
Threshold: 1

Signal assignment statement on line 708:

708: mr_ctrl_in.status_txpe <= '0';
Count: 67370
Threshold: 1

Signal assignment statement on line 709:

709: mr_ctrl_in.status_txdpe <= '0';
Count: 67370
Threshold: 1

Loop statement on lines 711 to 719:

711:            for i in 0 to G_TXT_BUFFER_COUNT - 1 loop 
712:                if (txtb_parity_error_valid(i) = '1') then 
...
718:                end if; 
719:            end loop;

Count: 544969539
Threshold: 1

If statement on lines 712 to 714:

712:                if (txtb_parity_error_valid(i) = '1') then 
713:                    mr_ctrl_in.status_txpe <= '1'; 
714:                end if;

Count: 1325538740
Threshold: 1

Signal assignment statement on line 713:

713: mr_ctrl_in.status_txpe <= '1';
Count: 393
Threshold: 1

If statement on lines 716 to 718:

716:                if (txtb_bb_parity_error(i / 2) = '1') then 
717:                    mr_ctrl_in.status_txdpe <= '1'; 
718:                end if;

Count: 1325538740
Threshold: 1

Signal assignment statement on line 717:

717: mr_ctrl_in.status_txdpe <= '1';
Count: 88
Threshold: 1

If statement on lines 721 to 723:

721:            if (mr_ctrl_out_i.command_ctxpe = '1') then 
722:                mr_ctrl_in.status_txpe <= '0'; 
723:            end if;

Count: 544969539
Threshold: 1

Signal assignment statement on line 722:

722: mr_ctrl_in.status_txpe <= '0';
Count: 440
Threshold: 1

If statement on lines 725 to 727:

725:            if (mr_ctrl_out_i.command_ctxdpe = '1') then 
726:                mr_ctrl_in.status_txdpe <= '0'; 
727:            end if;

Count: 544969539
Threshold: 1

Signal assignment statement on line 726:

726: mr_ctrl_in.status_txdpe <= '0';
Count: 40
Threshold: 1

Sequential statement on lines 731 to 733:

731:    mr_ctrl_in.status_stcnt <= '1' when G_SUP_TRAFFIC_CTRS 
732:                                   else 
733:                               '0';

Count: 1601
Threshold: 1

Sequential statement on lines 734 to 736:

734:    mr_ctrl_in.status_sprt <= '1' when G_SUP_PARITY 
735:                                  else 
736:                              '0';

Count: 1601
Threshold: 1

Sequential statement on lines 737 to 739:

737:    mr_ctrl_in.status_strgs <= '1' when G_SUP_TEST_REGISTERS 
738:                                   else 
739:                               '0';

Count: 1601
Threshold: 1

Signal assignment statement on line 742:

742: mr_ctrl_in.int_stat_rxi <= mr_int_stat_rxi_o;
Count: 4816
Threshold: 1

Signal assignment statement on line 743:

743: mr_ctrl_in.int_stat_txi <= mr_int_stat_txi_o;
Count: 5628
Threshold: 1

Signal assignment statement on line 744:

744: mr_ctrl_in.int_stat_ewli <= mr_int_stat_ewli_o;
Count: 4375
Threshold: 1

Signal assignment statement on line 745:

745: mr_ctrl_in.int_stat_doi <= mr_int_stat_doi_o;
Count: 3244
Threshold: 1

Signal assignment statement on line 746:

746: mr_ctrl_in.int_stat_fcsi <= mr_int_stat_fcsi_o;
Count: 9798
Threshold: 1

Signal assignment statement on line 747:

747: mr_ctrl_in.int_stat_ali <= mr_int_stat_ali_o;
Count: 3398
Threshold: 1

Signal assignment statement on line 748:

748: mr_ctrl_in.int_stat_bei <= mr_int_stat_bei_o;
Count: 6028
Threshold: 1

Signal assignment statement on line 749:

749: mr_ctrl_in.int_stat_ofi <= mr_int_stat_ofi_o;
Count: 3506
Threshold: 1

Signal assignment statement on line 750:

750: mr_ctrl_in.int_stat_rxfi <= mr_int_stat_rxfi_o;
Count: 3242
Threshold: 1

Signal assignment statement on line 751:

751: mr_ctrl_in.int_stat_bsi <= mr_int_stat_bsi_o;
Count: 5794
Threshold: 1

Signal assignment statement on line 752:

752: mr_ctrl_in.int_stat_rbnei <= mr_int_stat_rbnei_o;
Count: 5072
Threshold: 1

Signal assignment statement on line 753:

753: mr_ctrl_in.int_stat_txbhci <= mr_int_stat_txbhci_o;
Count: 6557
Threshold: 1

Signal assignment statement on line 756:

756: mr_ctrl_in.int_ena_set_int_ena_set <= mr_int_ena_set_int_ena_set_o;
Count: 3774
Threshold: 1

Signal assignment statement on line 759:

759: mr_ctrl_in.int_mask_set_int_mask_set <= mr_int_mask_set_int_mask_set_o;
Count: 3436
Threshold: 1

Signal assignment statement on line 762:

762: mr_ctrl_in.fault_state_era <= cc_stat.is_err_active;
Count: 18442
Threshold: 1

Signal assignment statement on line 763:

763: mr_ctrl_in.fault_state_erp <= cc_stat.is_err_passive;
Count: 4724
Threshold: 1

Signal assignment statement on line 764:

764: mr_ctrl_in.fault_state_bof <= cc_stat.is_bus_off;
Count: 18066
Threshold: 1

Signal assignment statement on line 767:

767: mr_ctrl_in.rec_rec_val <= cc_stat.rx_err_ctr;
Count: 27286
Threshold: 1

Signal assignment statement on line 770:

770: mr_ctrl_in.tec_tec_val <= cc_stat.tx_err_ctr;
Count: 33426
Threshold: 1

Signal assignment statement on line 773:

773: mr_ctrl_in.err_norm_err_norm_val <= cc_stat.norm_err_ctr;
Count: 27160
Threshold: 1

Signal assignment statement on line 774:

774: mr_ctrl_in.err_fd_err_fd_val <= cc_stat.data_err_ctr;
Count: 14587
Threshold: 1

Sequential statement on lines 777 to 778:

777:    mr_ctrl_in.filter_status_sfa <= '1' when G_SUP_FILTA else 
778:                                    '0';

Count: 1601
Threshold: 1

Sequential statement on lines 780 to 781:

780:    mr_ctrl_in.filter_status_sfb <= '1' when G_SUP_FILTB else 
781:                                    '0';

Count: 1601
Threshold: 1

Sequential statement on lines 783 to 784:

783:    mr_ctrl_in.filter_status_sfc <= '1' when G_SUP_FILTC else 
784:                                    '0';

Count: 1601
Threshold: 1

Sequential statement on lines 786 to 787:

786:    mr_ctrl_in.filter_status_sfr <= '1' when G_SUP_RANGE else 
787:                                    '0';

Count: 1601
Threshold: 1

Signal assignment statement on line 790:

790: mr_ctrl_in.rx_mem_info_rx_buff_size <= std_logic_vector(to_unsigned(G_RX_BUFF_SIZE, 13));
Count: 1601
Threshold: 1

Signal assignment statement on line 794:

794: mr_ctrl_in.rx_mem_info_rx_mem_free <= (others => '0');
Count: 68645
Threshold: 1

Signal assignment statement on line 795:

795: mr_ctrl_in.rx_mem_info_rx_mem_free(G_RX_BUFF_PTR_WIDTH downto 0) <= rx_mem_free;
Count: 68645
Threshold: 1

Signal assignment statement on line 801:

801: mr_ctrl_in.rx_pointers_rx_wpp <= (others => '0');
Count: 17729
Threshold: 1

Signal assignment statement on line 802:

802: mr_ctrl_in.rx_pointers_rx_wpp(G_RX_BUFF_PTR_WIDTH - 1 downto 0) <= rx_write_pointer;
Count: 17729
Threshold: 1

Signal assignment statement on line 807:

807: mr_ctrl_in.rx_pointers_rx_rpp <= (others => '0');
Count: 55704
Threshold: 1

Signal assignment statement on line 808:

808: mr_ctrl_in.rx_pointers_rx_rpp(G_RX_BUFF_PTR_WIDTH - 1 downto 0) <= rx_read_pointer;
Count: 55704
Threshold: 1

Signal assignment statement on line 812:

812: mr_ctrl_in.rx_status_rxe <= rx_empty;
Count: 19601
Threshold: 1

Signal assignment statement on line 813:

813: mr_ctrl_in.rx_status_rxf <= rx_full;
Count: 3242
Threshold: 1

Signal assignment statement on line 814:

814: mr_ctrl_in.rx_status_rxmof <= rx_mof;
Count: 23475
Threshold: 1

Signal assignment statement on line 818:

818: mr_ctrl_in.rx_status_rxfrc <= (others => '0');
Count: 26313
Threshold: 1

Signal assignment statement on line 819:

819: mr_ctrl_in.rx_status_rxfrc(G_RX_BUF_FRAME_CNT_WIDTH - 1 downto 0) <= rx_frame_count;
Count: 26313
Threshold: 1

Signal assignment statement on line 823:

823: mr_ctrl_in.rx_data_rx_data <= rxb_port_b_data_out;
Count: 60711
Threshold: 1

Variable assignment statement on line 829:

829: txtb_state_padded := (others => (others => '0'));
Count: 82056
Threshold: 1

Variable assignment statement on line 830:

830: txtb_state_padded(G_TXT_BUFFER_COUNT - 1 downto 0) := txtb_state;
Count: 82056
Threshold: 1

Signal assignment statement on line 832:

832: mr_ctrl_in.tx_status_tx1s <= txtb_state_padded(0);
Count: 82056
Threshold: 1

Signal assignment statement on line 833:

833: mr_ctrl_in.tx_status_tx2s <= txtb_state_padded(1);
Count: 82056
Threshold: 1

Signal assignment statement on line 834:

834: mr_ctrl_in.tx_status_tx3s <= txtb_state_padded(2);
Count: 82056
Threshold: 1

Signal assignment statement on line 835:

835: mr_ctrl_in.tx_status_tx4s <= txtb_state_padded(3);
Count: 82056
Threshold: 1

Signal assignment statement on line 836:

836: mr_ctrl_in.tx_status_tx5s <= txtb_state_padded(4);
Count: 82056
Threshold: 1

Signal assignment statement on line 837:

837: mr_ctrl_in.tx_status_tx6s <= txtb_state_padded(5);
Count: 82056
Threshold: 1

Signal assignment statement on line 838:

838: mr_ctrl_in.tx_status_tx7s <= txtb_state_padded(6);
Count: 82056
Threshold: 1

Signal assignment statement on line 839:

839: mr_ctrl_in.tx_status_tx8s <= txtb_state_padded(7);
Count: 82056
Threshold: 1

Signal assignment statement on line 843:

843: mr_ctrl_in.txtb_info_txt_buffer_count <= std_logic_vector(to_unsigned(G_TXT_BUFFER_COUNT, 4));
Count: 1601
Threshold: 1

Signal assignment statement on line 846:

846: mr_ctrl_in.err_capt_err_pos <= cc_stat.err_pos;
Count: 12038
Threshold: 1

Signal assignment statement on line 847:

847: mr_ctrl_in.err_capt_err_type <= cc_stat.err_type;
Count: 7328
Threshold: 1

Signal assignment statement on line 848:

848: mr_ctrl_in.err_capt_err_erp <= cc_stat.err_erp;
Count: 3782
Threshold: 1

Signal assignment statement on line 851:

851: mr_ctrl_in.retr_ctr_retr_ctr_val <= cc_stat.retr_ctr;
Count: 4515
Threshold: 1

Signal assignment statement on line 854:

854: mr_ctrl_in.alc_alc_bit <= cc_stat.alc_bit;
Count: 3819
Threshold: 1

Signal assignment statement on line 855:

855: mr_ctrl_in.alc_alc_id_field <= cc_stat.alc_id_field;
Count: 3470
Threshold: 1

Signal assignment statement on line 858:

858: mr_ctrl_in.ts_info_ts_bits <= std_logic_vector(to_unsigned(G_TS_BITS, 6));
Count: 1601
Threshold: 1

Signal assignment statement on line 861:

861: mr_ctrl_in.trv_delay_trv_delay_value <= trv_delay;
Count: 7601
Threshold: 1

Signal assignment statement on line 864:

864: mr_ctrl_in.rx_fr_ctr_rx_fr_ctr_val <= cc_stat.rx_frame_ctr;
Count: 15421
Threshold: 1

Signal assignment statement on line 867:

867: mr_ctrl_in.tx_fr_ctr_tx_fr_ctr_val <= cc_stat.tx_frame_ctr;
Count: 8142
Threshold: 1

Signal assignment statement on line 870:

870: mr_ctrl_in.debug_register_stuff_count <= cc_stat.bst_ctr;
Count: 296187
Threshold: 1

Signal assignment statement on line 871:

871: mr_ctrl_in.debug_register_destuff_count <= cc_stat.dst_ctr;
Count: 995560
Threshold: 1

Signal assignment statement on line 872:

872: mr_ctrl_in.debug_register_pc_arb <= pc_dbg.is_arbitration;
Count: 114648
Threshold: 1

Signal assignment statement on line 873:

873: mr_ctrl_in.debug_register_pc_con <= pc_dbg.is_control;
Count: 105142
Threshold: 1

Signal assignment statement on line 874:

874: mr_ctrl_in.debug_register_pc_dat <= pc_dbg.is_data;
Count: 76842
Threshold: 1

Signal assignment statement on line 875:

875: mr_ctrl_in.debug_register_pc_stc <= pc_dbg.is_stuff_count;
Count: 30206
Threshold: 1

Signal assignment statement on line 876:

876: mr_ctrl_in.debug_register_pc_crc <= pc_dbg.is_crc;
Count: 65628
Threshold: 1

Signal assignment statement on line 877:

877: mr_ctrl_in.debug_register_pc_crcd <= pc_dbg.is_crc_delim;
Count: 62672
Threshold: 1

Signal assignment statement on line 878:

878: mr_ctrl_in.debug_register_pc_ack <= pc_dbg.is_ack;
Count: 62378
Threshold: 1

Signal assignment statement on line 879:

879: mr_ctrl_in.debug_register_pc_ackd <= pc_dbg.is_ack_delim;
Count: 59532
Threshold: 1

Signal assignment statement on line 880:

880: mr_ctrl_in.debug_register_pc_eof <= pc_dbg.is_eof;
Count: 57748
Threshold: 1

Signal assignment statement on line 881:

881: mr_ctrl_in.debug_register_pc_int <= pc_dbg.is_intermission;
Count: 106633
Threshold: 1

Signal assignment statement on line 882:

882: mr_ctrl_in.debug_register_pc_susp <= pc_dbg.is_suspend;
Count: 8760
Threshold: 1

Signal assignment statement on line 883:

883: mr_ctrl_in.debug_register_pc_ovr <= pc_dbg.is_overload;
Count: 4260
Threshold: 1

Signal assignment statement on line 884:

884: mr_ctrl_in.debug_register_pc_sof <= pc_dbg.is_sof;
Count: 53050
Threshold: 1

Signal assignment statement on line 887:

887: mr_ctrl_in.yolo_reg_yolo_val <= YOLO_VAL_RSTVAL;
Count: 1601
Threshold: 1

Signal assignment statement on line 890:

890: mr_ctrl_in.timestamp_low_timestamp_low <= timestamp(31 downto 0);
Count: 545001030
Threshold: 1

Signal assignment statement on line 891:

891: mr_ctrl_in.timestamp_high_timestamp_high <= timestamp(63 downto 32);
Count: 3442
Threshold: 1

	Evaluated to	Count	Threshold
Bin	True	801022	1
Bin	False	94165160	1

	Evaluated to	Count	Threshold
Bin	True	19215496	1
Bin	False	75752287	1

	Evaluated to	Count	Threshold
Bin	True	313176	1
Bin	False	94654607	1

	Evaluated to	Count	Threshold
Bin	True	50414	1
Bin	False	1089965988	1

	Evaluated to	Count	Threshold
Bin	True	544977583	1
Bin	False	544988405	1

	Evaluated to	Count	Threshold
Bin	True	10640049	1
Bin	False	10381068	1

	Evaluated to	Count	Threshold
Bin	True	101999	1
Bin	False	10279069	1

	Evaluated to	Count	Threshold
Bin	True	19215496	1
Bin	False	74269722	1

	Evaluated to	Count	Threshold
Bin	True	313176	1
Bin	False	55367402	1

	Evaluated to	Count	Threshold
Bin	True	19724	1
Bin	False	61457	1

	Evaluated to	Count	Threshold
Bin	True	15265	1
Bin	False	1745	1

	Evaluated to	Count	Threshold
Bin	True	8361	1
Bin	False	108955	1

	Evaluated to	Count	Threshold
Bin	True	55892	1
Bin	False	53063	1

	Evaluated to	Count	Threshold
Bin	True	142099	1
Bin	False	131683	1

	Evaluated to	Count	Threshold
Bin	True	67370	1
Bin	False	1089952369	1

	Evaluated to	Count	Threshold
Bin	True	544969539	1
Bin	False	544982830	1

	Evaluated to	Count	Threshold
Bin	True	393	1
Bin	False	1325538347	1

	Evaluated to	Count	Threshold
Bin	True	88	1
Bin	False	1325538652	1

	Evaluated to	Count	Threshold
Bin	True	440	1
Bin	False	544969099	1

	Evaluated to	Count	Threshold
Bin	True	40	1
Bin	False	544969499	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ADRESS

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SCS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SRD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SWR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SBE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TIMESTAMP

	Element	From	To	Threshold	Excluded due to
Bin	(63)	0	1	1	Exclude file
Bin	(63)	1	0	1	Exclude file
Bin	(62)	0	1	1	Exclude file
Bin	(62)	1	0	1	Exclude file
Bin	(61)	0	1	1	Exclude file
Bin	(61)	1	0	1	Exclude file
Bin	(60)	0	1	1	Exclude file
Bin	(60)	1	0	1	Exclude file
Bin	(59)	0	1	1	Exclude file
Bin	(59)	1	0	1	Exclude file
Bin	(58)	0	1	1	Exclude file
Bin	(58)	1	0	1	Exclude file
Bin	(57)	0	1	1	Exclude file
Bin	(57)	1	0	1	Exclude file
Bin	(56)	0	1	1	Exclude file
Bin	(56)	1	0	1	Exclude file
Bin	(55)	0	1	1	Exclude file
Bin	(55)	1	0	1	Exclude file
Bin	(54)	0	1	1	Exclude file
Bin	(54)	1	0	1	Exclude file
Bin	(53)	0	1	1	Exclude file
Bin	(53)	1	0	1	Exclude file
Bin	(52)	0	1	1	Exclude file
Bin	(52)	1	0	1	Exclude file
Bin	(51)	0	1	1	Exclude file
Bin	(51)	1	0	1	Exclude file
Bin	(50)	0	1	1	Exclude file
Bin	(50)	1	0	1	Exclude file
Bin	(49)	0	1	1	Exclude file
Bin	(49)	1	0	1	Exclude file
Bin	(48)	0	1	1	Exclude file
Bin	(48)	1	0	1	Exclude file
Bin	(47)	0	1	1	Exclude file
Bin	(47)	1	0	1	Exclude file
Bin	(46)	0	1	1	Exclude file
Bin	(46)	1	0	1	Exclude file
Bin	(45)	0	1	1	Exclude file
Bin	(45)	1	0	1	Exclude file
Bin	(44)	0	1	1	Exclude file
Bin	(44)	1	0	1	Exclude file
Bin	(43)	0	1	1	Exclude file
Bin	(43)	1	0	1	Exclude file
Bin	(42)	0	1	1	Exclude file
Bin	(42)	1	0	1	Exclude file
Bin	(41)	0	1	1	Exclude file
Bin	(41)	1	0	1	Exclude file
Bin	(40)	0	1	1	Exclude file
Bin	(40)	1	0	1	Exclude file
Bin	(39)	0	1	1	Exclude file
Bin	(39)	1	0	1	Exclude file
Bin	(38)	0	1	1	Exclude file
Bin	(38)	1	0	1	Exclude file
Bin	(37)	0	1	1	Exclude file
Bin	(37)	1	0	1	Exclude file
Bin	(36)	0	1	1	Exclude file
Bin	(36)	1	0	1	Exclude file
Bin	(35)	0	1	1	Exclude file
Bin	(35)	1	0	1	Exclude file
Bin	(34)	0	1	1	Exclude file
Bin	(34)	1	0	1	Exclude file
Bin	(33)	0	1	1	Exclude file
Bin	(33)	1	0	1	Exclude file
Bin	(32)	0	1	1	Exclude file
Bin	(32)	1	0	1	Exclude file
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_RDATA_TST_RDATA_RXB

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_RDATA_TST_RDATA_TXB

	Element	From	To	Threshold	Excluded due to
Bin	(7)(31)	0	1	1	Exclude file
Bin	(7)(31)	1	0	1	Exclude file
Bin	(7)(30)	0	1	1	Exclude file
Bin	(7)(30)	1	0	1	Exclude file
Bin	(7)(29)	0	1	1	Exclude file
Bin	(7)(29)	1	0	1	Exclude file
Bin	(7)(28)	0	1	1	Exclude file
Bin	(7)(28)	1	0	1	Exclude file
Bin	(7)(27)	0	1	1	Exclude file
Bin	(7)(27)	1	0	1	Exclude file
Bin	(7)(26)	0	1	1	Exclude file
Bin	(7)(26)	1	0	1	Exclude file
Bin	(7)(25)	0	1	1	Exclude file
Bin	(7)(25)	1	0	1	Exclude file
Bin	(7)(24)	0	1	1	Exclude file
Bin	(7)(24)	1	0	1	Exclude file
Bin	(7)(23)	0	1	1	Exclude file
Bin	(7)(23)	1	0	1	Exclude file
Bin	(7)(22)	0	1	1	Exclude file
Bin	(7)(22)	1	0	1	Exclude file
Bin	(7)(21)	0	1	1	Exclude file
Bin	(7)(21)	1	0	1	Exclude file
Bin	(7)(20)	0	1	1	Exclude file
Bin	(7)(20)	1	0	1	Exclude file
Bin	(7)(19)	0	1	1	Exclude file
Bin	(7)(19)	1	0	1	Exclude file
Bin	(7)(18)	0	1	1	Exclude file
Bin	(7)(18)	1	0	1	Exclude file
Bin	(7)(17)	0	1	1	Exclude file
Bin	(7)(17)	1	0	1	Exclude file
Bin	(7)(16)	0	1	1	Exclude file
Bin	(7)(16)	1	0	1	Exclude file
Bin	(7)(15)	0	1	1	Exclude file
Bin	(7)(15)	1	0	1	Exclude file
Bin	(7)(14)	0	1	1	Exclude file
Bin	(7)(14)	1	0	1	Exclude file
Bin	(7)(13)	0	1	1	Exclude file
Bin	(7)(13)	1	0	1	Exclude file
Bin	(7)(12)	0	1	1	Exclude file
Bin	(7)(12)	1	0	1	Exclude file
Bin	(7)(11)	0	1	1	Exclude file
Bin	(7)(11)	1	0	1	Exclude file
Bin	(7)(10)	0	1	1	Exclude file
Bin	(7)(10)	1	0	1	Exclude file
Bin	(7)(9)	0	1	1	Exclude file
Bin	(7)(9)	1	0	1	Exclude file
Bin	(7)(8)	0	1	1	Exclude file
Bin	(7)(8)	1	0	1	Exclude file
Bin	(7)(7)	0	1	1	Exclude file
Bin	(7)(7)	1	0	1	Exclude file
Bin	(7)(6)	0	1	1	Exclude file
Bin	(7)(6)	1	0	1	Exclude file
Bin	(7)(5)	0	1	1	Exclude file
Bin	(7)(5)	1	0	1	Exclude file
Bin	(7)(4)	0	1	1	Exclude file
Bin	(7)(4)	1	0	1	Exclude file
Bin	(7)(3)	0	1	1	Exclude file
Bin	(7)(3)	1	0	1	Exclude file
Bin	(7)(2)	0	1	1	Exclude file
Bin	(7)(2)	1	0	1	Exclude file
Bin	(7)(1)	0	1	1	Exclude file
Bin	(7)(1)	1	0	1	Exclude file
Bin	(7)(0)	0	1	1	Exclude file
Bin	(7)(0)	1	0	1	Exclude file
Bin	(6)(31)	0	1	1	Exclude file
Bin	(6)(31)	1	0	1	Exclude file
Bin	(6)(30)	0	1	1	Exclude file
Bin	(6)(30)	1	0	1	Exclude file
Bin	(6)(29)	0	1	1	Exclude file
Bin	(6)(29)	1	0	1	Exclude file
Bin	(6)(28)	0	1	1	Exclude file
Bin	(6)(28)	1	0	1	Exclude file
Bin	(6)(27)	0	1	1	Exclude file
Bin	(6)(27)	1	0	1	Exclude file
Bin	(6)(26)	0	1	1	Exclude file
Bin	(6)(26)	1	0	1	Exclude file
Bin	(6)(25)	0	1	1	Exclude file
Bin	(6)(25)	1	0	1	Exclude file
Bin	(6)(24)	0	1	1	Exclude file
Bin	(6)(24)	1	0	1	Exclude file
Bin	(6)(23)	0	1	1	Exclude file
Bin	(6)(23)	1	0	1	Exclude file
Bin	(6)(22)	0	1	1	Exclude file
Bin	(6)(22)	1	0	1	Exclude file
Bin	(6)(21)	0	1	1	Exclude file
Bin	(6)(21)	1	0	1	Exclude file
Bin	(6)(20)	0	1	1	Exclude file
Bin	(6)(20)	1	0	1	Exclude file
Bin	(6)(19)	0	1	1	Exclude file
Bin	(6)(19)	1	0	1	Exclude file
Bin	(6)(18)	0	1	1	Exclude file
Bin	(6)(18)	1	0	1	Exclude file
Bin	(6)(17)	0	1	1	Exclude file
Bin	(6)(17)	1	0	1	Exclude file
Bin	(6)(16)	0	1	1	Exclude file
Bin	(6)(16)	1	0	1	Exclude file
Bin	(6)(15)	0	1	1	Exclude file
Bin	(6)(15)	1	0	1	Exclude file
Bin	(6)(14)	0	1	1	Exclude file
Bin	(6)(14)	1	0	1	Exclude file
Bin	(6)(13)	0	1	1	Exclude file
Bin	(6)(13)	1	0	1	Exclude file
Bin	(6)(12)	0	1	1	Exclude file
Bin	(6)(12)	1	0	1	Exclude file
Bin	(6)(11)	0	1	1	Exclude file
Bin	(6)(11)	1	0	1	Exclude file
Bin	(6)(10)	0	1	1	Exclude file
Bin	(6)(10)	1	0	1	Exclude file
Bin	(6)(9)	0	1	1	Exclude file
Bin	(6)(9)	1	0	1	Exclude file
Bin	(6)(8)	0	1	1	Exclude file
Bin	(6)(8)	1	0	1	Exclude file
Bin	(6)(7)	0	1	1	Exclude file
Bin	(6)(7)	1	0	1	Exclude file
Bin	(6)(6)	0	1	1	Exclude file
Bin	(6)(6)	1	0	1	Exclude file
Bin	(6)(5)	0	1	1	Exclude file
Bin	(6)(5)	1	0	1	Exclude file
Bin	(6)(4)	0	1	1	Exclude file
Bin	(6)(4)	1	0	1	Exclude file
Bin	(6)(3)	0	1	1	Exclude file
Bin	(6)(3)	1	0	1	Exclude file
Bin	(6)(2)	0	1	1	Exclude file
Bin	(6)(2)	1	0	1	Exclude file
Bin	(6)(1)	0	1	1	Exclude file
Bin	(6)(1)	1	0	1	Exclude file
Bin	(6)(0)	0	1	1	Exclude file
Bin	(6)(0)	1	0	1	Exclude file
Bin	(5)(31)	0	1	1	Exclude file
Bin	(5)(31)	1	0	1	Exclude file
Bin	(5)(30)	0	1	1	Exclude file
Bin	(5)(30)	1	0	1	Exclude file
Bin	(5)(29)	0	1	1	Exclude file
Bin	(5)(29)	1	0	1	Exclude file
Bin	(5)(28)	0	1	1	Exclude file
Bin	(5)(28)	1	0	1	Exclude file
Bin	(5)(27)	0	1	1	Exclude file
Bin	(5)(27)	1	0	1	Exclude file
Bin	(5)(26)	0	1	1	Exclude file
Bin	(5)(26)	1	0	1	Exclude file
Bin	(5)(25)	0	1	1	Exclude file
Bin	(5)(25)	1	0	1	Exclude file
Bin	(5)(24)	0	1	1	Exclude file
Bin	(5)(24)	1	0	1	Exclude file
Bin	(5)(23)	0	1	1	Exclude file
Bin	(5)(23)	1	0	1	Exclude file
Bin	(5)(22)	0	1	1	Exclude file
Bin	(5)(22)	1	0	1	Exclude file
Bin	(5)(21)	0	1	1	Exclude file
Bin	(5)(21)	1	0	1	Exclude file
Bin	(5)(20)	0	1	1	Exclude file
Bin	(5)(20)	1	0	1	Exclude file
Bin	(5)(19)	0	1	1	Exclude file
Bin	(5)(19)	1	0	1	Exclude file
Bin	(5)(18)	0	1	1	Exclude file
Bin	(5)(18)	1	0	1	Exclude file
Bin	(5)(17)	0	1	1	Exclude file
Bin	(5)(17)	1	0	1	Exclude file
Bin	(5)(16)	0	1	1	Exclude file
Bin	(5)(16)	1	0	1	Exclude file
Bin	(5)(15)	0	1	1	Exclude file
Bin	(5)(15)	1	0	1	Exclude file
Bin	(5)(14)	0	1	1	Exclude file
Bin	(5)(14)	1	0	1	Exclude file
Bin	(5)(13)	0	1	1	Exclude file
Bin	(5)(13)	1	0	1	Exclude file
Bin	(5)(12)	0	1	1	Exclude file
Bin	(5)(12)	1	0	1	Exclude file
Bin	(5)(11)	0	1	1	Exclude file
Bin	(5)(11)	1	0	1	Exclude file
Bin	(5)(10)	0	1	1	Exclude file
Bin	(5)(10)	1	0	1	Exclude file
Bin	(5)(9)	0	1	1	Exclude file
Bin	(5)(9)	1	0	1	Exclude file
Bin	(5)(8)	0	1	1	Exclude file
Bin	(5)(8)	1	0	1	Exclude file
Bin	(5)(7)	0	1	1	Exclude file
Bin	(5)(7)	1	0	1	Exclude file
Bin	(5)(6)	0	1	1	Exclude file
Bin	(5)(6)	1	0	1	Exclude file
Bin	(5)(5)	0	1	1	Exclude file
Bin	(5)(5)	1	0	1	Exclude file
Bin	(5)(4)	0	1	1	Exclude file
Bin	(5)(4)	1	0	1	Exclude file
Bin	(5)(3)	0	1	1	Exclude file
Bin	(5)(3)	1	0	1	Exclude file
Bin	(5)(2)	0	1	1	Exclude file
Bin	(5)(2)	1	0	1	Exclude file
Bin	(5)(1)	0	1	1	Exclude file
Bin	(5)(1)	1	0	1	Exclude file
Bin	(5)(0)	0	1	1	Exclude file
Bin	(5)(0)	1	0	1	Exclude file
Bin	(4)(31)	0	1	1	Exclude file
Bin	(4)(31)	1	0	1	Exclude file
Bin	(4)(30)	0	1	1	Exclude file
Bin	(4)(30)	1	0	1	Exclude file
Bin	(4)(29)	0	1	1	Exclude file
Bin	(4)(29)	1	0	1	Exclude file
Bin	(4)(28)	0	1	1	Exclude file
Bin	(4)(28)	1	0	1	Exclude file
Bin	(4)(27)	0	1	1	Exclude file
Bin	(4)(27)	1	0	1	Exclude file
Bin	(4)(26)	0	1	1	Exclude file
Bin	(4)(26)	1	0	1	Exclude file
Bin	(4)(25)	0	1	1	Exclude file
Bin	(4)(25)	1	0	1	Exclude file
Bin	(4)(24)	0	1	1	Exclude file
Bin	(4)(24)	1	0	1	Exclude file
Bin	(4)(23)	0	1	1	Exclude file
Bin	(4)(23)	1	0	1	Exclude file
Bin	(4)(22)	0	1	1	Exclude file
Bin	(4)(22)	1	0	1	Exclude file
Bin	(4)(21)	0	1	1	Exclude file
Bin	(4)(21)	1	0	1	Exclude file
Bin	(4)(20)	0	1	1	Exclude file
Bin	(4)(20)	1	0	1	Exclude file
Bin	(4)(19)	0	1	1	Exclude file
Bin	(4)(19)	1	0	1	Exclude file
Bin	(4)(18)	0	1	1	Exclude file
Bin	(4)(18)	1	0	1	Exclude file
Bin	(4)(17)	0	1	1	Exclude file
Bin	(4)(17)	1	0	1	Exclude file
Bin	(4)(16)	0	1	1	Exclude file
Bin	(4)(16)	1	0	1	Exclude file
Bin	(4)(15)	0	1	1	Exclude file
Bin	(4)(15)	1	0	1	Exclude file
Bin	(4)(14)	0	1	1	Exclude file
Bin	(4)(14)	1	0	1	Exclude file
Bin	(4)(13)	0	1	1	Exclude file
Bin	(4)(13)	1	0	1	Exclude file
Bin	(4)(12)	0	1	1	Exclude file
Bin	(4)(12)	1	0	1	Exclude file
Bin	(4)(11)	0	1	1	Exclude file
Bin	(4)(11)	1	0	1	Exclude file
Bin	(4)(10)	0	1	1	Exclude file
Bin	(4)(10)	1	0	1	Exclude file
Bin	(4)(9)	0	1	1	Exclude file
Bin	(4)(9)	1	0	1	Exclude file
Bin	(4)(8)	0	1	1	Exclude file
Bin	(4)(8)	1	0	1	Exclude file
Bin	(4)(7)	0	1	1	Exclude file
Bin	(4)(7)	1	0	1	Exclude file
Bin	(4)(6)	0	1	1	Exclude file
Bin	(4)(6)	1	0	1	Exclude file
Bin	(4)(5)	0	1	1	Exclude file
Bin	(4)(5)	1	0	1	Exclude file
Bin	(4)(4)	0	1	1	Exclude file
Bin	(4)(4)	1	0	1	Exclude file
Bin	(4)(3)	0	1	1	Exclude file
Bin	(4)(3)	1	0	1	Exclude file
Bin	(4)(2)	0	1	1	Exclude file
Bin	(4)(2)	1	0	1	Exclude file
Bin	(4)(1)	0	1	1	Exclude file
Bin	(4)(1)	1	0	1	Exclude file
Bin	(4)(0)	0	1	1	Exclude file
Bin	(4)(0)	1	0	1	Exclude file
Bin	(3)(31)	0	1	1	Exclude file
Bin	(3)(31)	1	0	1	Exclude file
Bin	(3)(30)	0	1	1	Exclude file
Bin	(3)(30)	1	0	1	Exclude file
Bin	(3)(29)	0	1	1	Exclude file
Bin	(3)(29)	1	0	1	Exclude file
Bin	(3)(28)	0	1	1	Exclude file
Bin	(3)(28)	1	0	1	Exclude file
Bin	(3)(27)	0	1	1	Exclude file
Bin	(3)(27)	1	0	1	Exclude file
Bin	(3)(26)	0	1	1	Exclude file
Bin	(3)(26)	1	0	1	Exclude file
Bin	(3)(25)	0	1	1	Exclude file
Bin	(3)(25)	1	0	1	Exclude file
Bin	(3)(24)	0	1	1	Exclude file
Bin	(3)(24)	1	0	1	Exclude file
Bin	(3)(23)	0	1	1	Exclude file
Bin	(3)(23)	1	0	1	Exclude file
Bin	(3)(22)	0	1	1	Exclude file
Bin	(3)(22)	1	0	1	Exclude file
Bin	(3)(21)	0	1	1	Exclude file
Bin	(3)(21)	1	0	1	Exclude file
Bin	(3)(20)	0	1	1	Exclude file
Bin	(3)(20)	1	0	1	Exclude file
Bin	(3)(19)	0	1	1	Exclude file
Bin	(3)(19)	1	0	1	Exclude file
Bin	(3)(18)	0	1	1	Exclude file
Bin	(3)(18)	1	0	1	Exclude file
Bin	(3)(17)	0	1	1	Exclude file
Bin	(3)(17)	1	0	1	Exclude file
Bin	(3)(16)	0	1	1	Exclude file
Bin	(3)(16)	1	0	1	Exclude file
Bin	(3)(15)	0	1	1	Exclude file
Bin	(3)(15)	1	0	1	Exclude file
Bin	(3)(14)	0	1	1	Exclude file
Bin	(3)(14)	1	0	1	Exclude file
Bin	(3)(13)	0	1	1	Exclude file
Bin	(3)(13)	1	0	1	Exclude file
Bin	(3)(12)	0	1	1	Exclude file
Bin	(3)(12)	1	0	1	Exclude file
Bin	(3)(11)	0	1	1	Exclude file
Bin	(3)(11)	1	0	1	Exclude file
Bin	(3)(10)	0	1	1	Exclude file
Bin	(3)(10)	1	0	1	Exclude file
Bin	(3)(9)	0	1	1	Exclude file
Bin	(3)(9)	1	0	1	Exclude file
Bin	(3)(8)	0	1	1	Exclude file
Bin	(3)(8)	1	0	1	Exclude file
Bin	(3)(7)	0	1	1	Exclude file
Bin	(3)(7)	1	0	1	Exclude file
Bin	(3)(6)	0	1	1	Exclude file
Bin	(3)(6)	1	0	1	Exclude file
Bin	(3)(5)	0	1	1	Exclude file
Bin	(3)(5)	1	0	1	Exclude file
Bin	(3)(4)	0	1	1	Exclude file
Bin	(3)(4)	1	0	1	Exclude file
Bin	(3)(3)	0	1	1	Exclude file
Bin	(3)(3)	1	0	1	Exclude file
Bin	(3)(2)	0	1	1	Exclude file
Bin	(3)(2)	1	0	1	Exclude file
Bin	(3)(1)	0	1	1	Exclude file
Bin	(3)(1)	1	0	1	Exclude file
Bin	(3)(0)	0	1	1	Exclude file
Bin	(3)(0)	1	0	1	Exclude file
Bin	(2)(31)	0	1	1	Exclude file
Bin	(2)(31)	1	0	1	Exclude file
Bin	(2)(30)	0	1	1	Exclude file
Bin	(2)(30)	1	0	1	Exclude file
Bin	(2)(29)	0	1	1	Exclude file
Bin	(2)(29)	1	0	1	Exclude file
Bin	(2)(28)	0	1	1	Exclude file
Bin	(2)(28)	1	0	1	Exclude file
Bin	(2)(27)	0	1	1	Exclude file
Bin	(2)(27)	1	0	1	Exclude file
Bin	(2)(26)	0	1	1	Exclude file
Bin	(2)(26)	1	0	1	Exclude file
Bin	(2)(25)	0	1	1	Exclude file
Bin	(2)(25)	1	0	1	Exclude file
Bin	(2)(24)	0	1	1	Exclude file
Bin	(2)(24)	1	0	1	Exclude file
Bin	(2)(23)	0	1	1	Exclude file
Bin	(2)(23)	1	0	1	Exclude file
Bin	(2)(22)	0	1	1	Exclude file
Bin	(2)(22)	1	0	1	Exclude file
Bin	(2)(21)	0	1	1	Exclude file
Bin	(2)(21)	1	0	1	Exclude file
Bin	(2)(20)	0	1	1	Exclude file
Bin	(2)(20)	1	0	1	Exclude file
Bin	(2)(19)	0	1	1	Exclude file
Bin	(2)(19)	1	0	1	Exclude file
Bin	(2)(18)	0	1	1	Exclude file
Bin	(2)(18)	1	0	1	Exclude file
Bin	(2)(17)	0	1	1	Exclude file
Bin	(2)(17)	1	0	1	Exclude file
Bin	(2)(16)	0	1	1	Exclude file
Bin	(2)(16)	1	0	1	Exclude file
Bin	(2)(15)	0	1	1	Exclude file
Bin	(2)(15)	1	0	1	Exclude file
Bin	(2)(14)	0	1	1	Exclude file
Bin	(2)(14)	1	0	1	Exclude file
Bin	(2)(13)	0	1	1	Exclude file
Bin	(2)(13)	1	0	1	Exclude file
Bin	(2)(12)	0	1	1	Exclude file
Bin	(2)(12)	1	0	1	Exclude file
Bin	(2)(11)	0	1	1	Exclude file
Bin	(2)(11)	1	0	1	Exclude file
Bin	(2)(10)	0	1	1	Exclude file
Bin	(2)(10)	1	0	1	Exclude file
Bin	(2)(9)	0	1	1	Exclude file
Bin	(2)(9)	1	0	1	Exclude file
Bin	(2)(8)	0	1	1	Exclude file
Bin	(2)(8)	1	0	1	Exclude file
Bin	(2)(7)	0	1	1	Exclude file
Bin	(2)(7)	1	0	1	Exclude file
Bin	(2)(6)	0	1	1	Exclude file
Bin	(2)(6)	1	0	1	Exclude file
Bin	(2)(5)	0	1	1	Exclude file
Bin	(2)(5)	1	0	1	Exclude file
Bin	(2)(4)	0	1	1	Exclude file
Bin	(2)(4)	1	0	1	Exclude file
Bin	(2)(3)	0	1	1	Exclude file
Bin	(2)(3)	1	0	1	Exclude file
Bin	(2)(2)	0	1	1	Exclude file
Bin	(2)(2)	1	0	1	Exclude file
Bin	(2)(1)	0	1	1	Exclude file
Bin	(2)(1)	1	0	1	Exclude file
Bin	(2)(0)	0	1	1	Exclude file
Bin	(2)(0)	1	0	1	Exclude file
Bin	(1)(31)	0	1	1	Exclude file
Bin	(1)(31)	1	0	1	Exclude file
Bin	(1)(30)	0	1	1	Exclude file
Bin	(1)(30)	1	0	1	Exclude file
Bin	(1)(29)	0	1	1	Exclude file
Bin	(1)(29)	1	0	1	Exclude file
Bin	(1)(28)	0	1	1	Exclude file
Bin	(1)(28)	1	0	1	Exclude file
Bin	(1)(27)	0	1	1	Exclude file
Bin	(1)(27)	1	0	1	Exclude file
Bin	(1)(26)	0	1	1	Exclude file
Bin	(1)(26)	1	0	1	Exclude file
Bin	(1)(25)	0	1	1	Exclude file
Bin	(1)(25)	1	0	1	Exclude file
Bin	(1)(24)	0	1	1	Exclude file
Bin	(1)(24)	1	0	1	Exclude file
Bin	(1)(23)	0	1	1	Exclude file
Bin	(1)(23)	1	0	1	Exclude file
Bin	(1)(22)	0	1	1	Exclude file
Bin	(1)(22)	1	0	1	Exclude file
Bin	(1)(21)	0	1	1	Exclude file
Bin	(1)(21)	1	0	1	Exclude file
Bin	(1)(20)	0	1	1	Exclude file
Bin	(1)(20)	1	0	1	Exclude file
Bin	(1)(19)	0	1	1	Exclude file
Bin	(1)(19)	1	0	1	Exclude file
Bin	(1)(18)	0	1	1	Exclude file
Bin	(1)(18)	1	0	1	Exclude file
Bin	(1)(17)	0	1	1	Exclude file
Bin	(1)(17)	1	0	1	Exclude file
Bin	(1)(16)	0	1	1	Exclude file
Bin	(1)(16)	1	0	1	Exclude file
Bin	(1)(15)	0	1	1	Exclude file
Bin	(1)(15)	1	0	1	Exclude file
Bin	(1)(14)	0	1	1	Exclude file
Bin	(1)(14)	1	0	1	Exclude file
Bin	(1)(13)	0	1	1	Exclude file
Bin	(1)(13)	1	0	1	Exclude file
Bin	(1)(12)	0	1	1	Exclude file
Bin	(1)(12)	1	0	1	Exclude file
Bin	(1)(11)	0	1	1	Exclude file
Bin	(1)(11)	1	0	1	Exclude file
Bin	(1)(10)	0	1	1	Exclude file
Bin	(1)(10)	1	0	1	Exclude file
Bin	(1)(9)	0	1	1	Exclude file
Bin	(1)(9)	1	0	1	Exclude file
Bin	(1)(8)	0	1	1	Exclude file
Bin	(1)(8)	1	0	1	Exclude file
Bin	(1)(7)	0	1	1	Exclude file
Bin	(1)(7)	1	0	1	Exclude file
Bin	(1)(6)	0	1	1	Exclude file
Bin	(1)(6)	1	0	1	Exclude file
Bin	(1)(5)	0	1	1	Exclude file
Bin	(1)(5)	1	0	1	Exclude file
Bin	(1)(4)	0	1	1	Exclude file
Bin	(1)(4)	1	0	1	Exclude file
Bin	(1)(3)	0	1	1	Exclude file
Bin	(1)(3)	1	0	1	Exclude file
Bin	(1)(2)	0	1	1	Exclude file
Bin	(1)(2)	1	0	1	Exclude file
Bin	(1)(1)	0	1	1	Exclude file
Bin	(1)(1)	1	0	1	Exclude file
Bin	(1)(0)	0	1	1	Exclude file
Bin	(1)(0)	1	0	1	Exclude file
Bin	(0)(31)	0	1	1	Exclude file
Bin	(0)(31)	1	0	1	Exclude file
Bin	(0)(30)	0	1	1	Exclude file
Bin	(0)(30)	1	0	1	Exclude file
Bin	(0)(29)	0	1	1	Exclude file
Bin	(0)(29)	1	0	1	Exclude file
Bin	(0)(28)	0	1	1	Exclude file
Bin	(0)(28)	1	0	1	Exclude file
Bin	(0)(27)	0	1	1	Exclude file
Bin	(0)(27)	1	0	1	Exclude file
Bin	(0)(26)	0	1	1	Exclude file
Bin	(0)(26)	1	0	1	Exclude file
Bin	(0)(25)	0	1	1	Exclude file
Bin	(0)(25)	1	0	1	Exclude file
Bin	(0)(24)	0	1	1	Exclude file
Bin	(0)(24)	1	0	1	Exclude file
Bin	(0)(23)	0	1	1	Exclude file
Bin	(0)(23)	1	0	1	Exclude file
Bin	(0)(22)	0	1	1	Exclude file
Bin	(0)(22)	1	0	1	Exclude file
Bin	(0)(21)	0	1	1	Exclude file
Bin	(0)(21)	1	0	1	Exclude file
Bin	(0)(20)	0	1	1	Exclude file
Bin	(0)(20)	1	0	1	Exclude file
Bin	(0)(19)	0	1	1	Exclude file
Bin	(0)(19)	1	0	1	Exclude file
Bin	(0)(18)	0	1	1	Exclude file
Bin	(0)(18)	1	0	1	Exclude file
Bin	(0)(17)	0	1	1	Exclude file
Bin	(0)(17)	1	0	1	Exclude file
Bin	(0)(16)	0	1	1	Exclude file
Bin	(0)(16)	1	0	1	Exclude file
Bin	(0)(15)	0	1	1	Exclude file
Bin	(0)(15)	1	0	1	Exclude file
Bin	(0)(14)	0	1	1	Exclude file
Bin	(0)(14)	1	0	1	Exclude file
Bin	(0)(13)	0	1	1	Exclude file
Bin	(0)(13)	1	0	1	Exclude file
Bin	(0)(12)	0	1	1	Exclude file
Bin	(0)(12)	1	0	1	Exclude file
Bin	(0)(11)	0	1	1	Exclude file
Bin	(0)(11)	1	0	1	Exclude file
Bin	(0)(10)	0	1	1	Exclude file
Bin	(0)(10)	1	0	1	Exclude file
Bin	(0)(9)	0	1	1	Exclude file
Bin	(0)(9)	1	0	1	Exclude file
Bin	(0)(8)	0	1	1	Exclude file
Bin	(0)(8)	1	0	1	Exclude file
Bin	(0)(7)	0	1	1	Exclude file
Bin	(0)(7)	1	0	1	Exclude file
Bin	(0)(6)	0	1	1	Exclude file
Bin	(0)(6)	1	0	1	Exclude file
Bin	(0)(5)	0	1	1	Exclude file
Bin	(0)(5)	1	0	1	Exclude file
Bin	(0)(4)	0	1	1	Exclude file
Bin	(0)(4)	1	0	1	Exclude file
Bin	(0)(3)	0	1	1	Exclude file
Bin	(0)(3)	1	0	1	Exclude file
Bin	(0)(2)	0	1	1	Exclude file
Bin	(0)(2)	1	0	1	Exclude file
Bin	(0)(1)	0	1	1	Exclude file
Bin	(0)(1)	1	0	1	Exclude file
Bin	(0)(0)	0	1	1	Exclude file
Bin	(0)(0)	1	0	1	Exclude file

Port:

RX_FULL

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_EMPTY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_FRAME_COUNT

	Element	From	To	Threshold	Excluded due to
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_MEM_FREE

	Element	From	To	Threshold	Excluded due to
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_READ_POINTER

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_WRITE_POINTER

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_DATA_OVERRUN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_MOF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_PARITY_ERROR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RXB_PORT_B_DATA_OUT

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_STATE

	Element	From	To	Threshold	Excluded due to
Bin	(7)(3)	0	1	1	Exclude file
Bin	(7)(3)	1	0	1	Exclude file
Bin	(7)(2)	0	1	1	Exclude file
Bin	(7)(2)	1	0	1	Exclude file
Bin	(7)(1)	0	1	1	Exclude file
Bin	(7)(1)	1	0	1	Exclude file
Bin	(7)(0)	0	1	1	Exclude file
Bin	(7)(0)	1	0	1	Exclude file
Bin	(6)(3)	0	1	1	Exclude file
Bin	(6)(3)	1	0	1	Exclude file
Bin	(6)(2)	0	1	1	Exclude file
Bin	(6)(2)	1	0	1	Exclude file
Bin	(6)(1)	0	1	1	Exclude file
Bin	(6)(1)	1	0	1	Exclude file
Bin	(6)(0)	0	1	1	Exclude file
Bin	(6)(0)	1	0	1	Exclude file
Bin	(5)(3)	0	1	1	Exclude file
Bin	(5)(3)	1	0	1	Exclude file
Bin	(5)(2)	0	1	1	Exclude file
Bin	(5)(2)	1	0	1	Exclude file
Bin	(5)(1)	0	1	1	Exclude file
Bin	(5)(1)	1	0	1	Exclude file
Bin	(5)(0)	0	1	1	Exclude file
Bin	(5)(0)	1	0	1	Exclude file
Bin	(4)(3)	0	1	1	Exclude file
Bin	(4)(3)	1	0	1	Exclude file
Bin	(4)(2)	0	1	1	Exclude file
Bin	(4)(2)	1	0	1	Exclude file
Bin	(4)(1)	0	1	1	Exclude file
Bin	(4)(1)	1	0	1	Exclude file
Bin	(4)(0)	0	1	1	Exclude file
Bin	(4)(0)	1	0	1	Exclude file
Bin	(3)(3)	0	1	1	Exclude file
Bin	(3)(3)	1	0	1	Exclude file
Bin	(3)(2)	0	1	1	Exclude file
Bin	(3)(2)	1	0	1	Exclude file
Bin	(3)(1)	0	1	1	Exclude file
Bin	(3)(1)	1	0	1	Exclude file
Bin	(3)(0)	0	1	1	Exclude file
Bin	(3)(0)	1	0	1	Exclude file
Bin	(2)(3)	0	1	1	Exclude file
Bin	(2)(3)	1	0	1	Exclude file
Bin	(2)(2)	0	1	1	Exclude file
Bin	(2)(2)	1	0	1	Exclude file
Bin	(2)(1)	0	1	1	Exclude file
Bin	(2)(1)	1	0	1	Exclude file
Bin	(2)(0)	0	1	1	Exclude file
Bin	(2)(0)	1	0	1	Exclude file
Bin	(1)(3)	0	1	1	Exclude file
Bin	(1)(3)	1	0	1	Exclude file
Bin	(1)(2)	0	1	1	Exclude file
Bin	(1)(2)	1	0	1	Exclude file
Bin	(1)(1)	0	1	1	Exclude file
Bin	(1)(1)	1	0	1	Exclude file
Bin	(1)(0)	0	1	1	Exclude file
Bin	(1)(0)	1	0	1	Exclude file
Bin	(0)(3)	0	1	1	Exclude file
Bin	(0)(3)	1	0	1	Exclude file
Bin	(0)(2)	0	1	1	Exclude file
Bin	(0)(2)	1	0	1	Exclude file
Bin	(0)(1)	0	1	1	Exclude file
Bin	(0)(1)	1	0	1	Exclude file
Bin	(0)(0)	0	1	1	Exclude file
Bin	(0)(0)	1	0	1	Exclude file

Port:

TXTB_PARITY_ERROR_VALID

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_BB_PARITY_ERROR

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TRV_DELAY

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_INT_STAT_RXI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_TXI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_EWLI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_DOI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_FCSI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_ALI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_BEI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_OFI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_RXFI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_BSI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_RBNEI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_TXBHCI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_ENA_SET_INT_ENA_SET_O

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_INT_MASK_SET_INT_MASK_SET_O

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Signal:

MR_CTRL_IN

	Element	From	To	Threshold	Excluded due to
Bin	DEVICE_ID_DEVICE_ID(15)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(14)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(13)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(12)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(11)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(10)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(9)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(8)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(7)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(6)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(5)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(4)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(3)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(2)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(1)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(0)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(7)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(6)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(5)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(4)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(3)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(2)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(1)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(0)	1	0	1	Exclude file
Bin	VERSION_VER_MAJOR(7)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(6)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(5)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(4)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(3)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(2)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(1)	1	0	1	Exclude file
Bin	VERSION_VER_MAJOR(0)	0	1	1	Exclude file
Bin	STATUS_STRGS	1	0	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(11)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(10)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(9)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(8)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(6)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(4)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(3)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(2)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(1)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(0)	0	1	1	Exclude file
Bin	TXTB_INFO_TXT_BUFFER_COUNT(0)	0	1	1	Exclude file
Bin	TS_INFO_TS_BITS(5)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(4)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(3)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(2)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(1)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(0)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(31)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(30)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(29)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(28)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(27)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(26)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(25)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(24)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(23)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(22)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(21)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(20)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(19)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(18)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(17)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(16)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(15)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(14)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(13)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(12)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(11)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(10)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(9)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(8)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(7)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(6)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(5)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(4)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(3)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(2)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(1)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(0)	1	0	1	Exclude file

Covered toggles:

Port:

RES_SOFT_N

	From	To	Count	Threshold
Bin	0	1	9645	1
Bin	1	0	8044	1

Port:

RES_CORE_N

	From	To	Count	Threshold
Bin	0	1	8084	1
Bin	1	0	8072	1

Port:

DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	23290	1
Bin	(31)	1	0	24891	1
Bin	(30)	0	1	24560	1
Bin	(30)	1	0	26161	1
Bin	(29)	0	1	24277	1
Bin	(29)	1	0	25878	1
Bin	(28)	0	1	31636	1
Bin	(28)	1	0	33237	1
Bin	(27)	0	1	34459	1
Bin	(27)	1	0	36060	1
Bin	(26)	0	1	31727	1
Bin	(26)	1	0	33328	1
Bin	(25)	0	1	51413	1
Bin	(25)	1	0	53014	1
Bin	(24)	0	1	38847	1
Bin	(24)	1	0	40448	1
Bin	(23)	0	1	50091	1
Bin	(23)	1	0	51692	1
Bin	(22)	0	1	124214	1
Bin	(22)	1	0	125815	1
Bin	(21)	0	1	40120	1
Bin	(21)	1	0	41721	1
Bin	(20)	0	1	52872	1
Bin	(20)	1	0	54473	1
Bin	(19)	0	1	50450	1
Bin	(19)	1	0	52051	1
Bin	(18)	0	1	301783	1
Bin	(18)	1	0	303384	1
Bin	(17)	0	1	119387	1
Bin	(17)	1	0	120988	1
Bin	(16)	0	1	132923	1
Bin	(16)	1	0	134524	1
Bin	(15)	0	1	170697	1
Bin	(15)	1	0	172298	1
Bin	(14)	0	1	576961	1
Bin	(14)	1	0	578562	1
Bin	(13)	0	1	132552	1
Bin	(13)	1	0	134153	1
Bin	(12)	0	1	193711	1
Bin	(12)	1	0	195312	1
Bin	(11)	0	1	146760	1
Bin	(11)	1	0	148361	1
Bin	(10)	0	1	1547924	1
Bin	(10)	1	0	1549525	1
Bin	(9)	0	1	360406	1
Bin	(9)	1	0	362007	1
Bin	(8)	0	1	3213616	1
Bin	(8)	1	0	3215217	1
Bin	(7)	0	1	969991	1
Bin	(7)	1	0	971592	1
Bin	(6)	0	1	3009906	1
Bin	(6)	1	0	3011507	1
Bin	(5)	0	1	1606600	1
Bin	(5)	1	0	1608201	1
Bin	(4)	0	1	3699908	1
Bin	(4)	1	0	3701509	1
Bin	(3)	0	1	4323474	1
Bin	(3)	1	0	4325075	1
Bin	(2)	0	1	642997	1
Bin	(2)	1	0	644597	1
Bin	(1)	0	1	1590029	1
Bin	(1)	1	0	1591629	1
Bin	(0)	0	1	1958762	1
Bin	(0)	1	0	1960362	1

Port:

MR_CTRL_OUT

	Element	From	To	Count	Threshold
Bin	MODE_RST	0	1	868	1
Bin	MODE_RST	1	0	32879	1
Bin	MODE_BMM	0	1	15	1
Bin	MODE_BMM	1	0	1616	1
Bin	MODE_STM	0	1	160	1
Bin	MODE_STM	1	0	1761	1
Bin	MODE_AFM	0	1	68	1
Bin	MODE_AFM	1	0	1669	1
Bin	MODE_FDE	0	1	1801	1
Bin	MODE_FDE	1	0	200	1
Bin	MODE_TTTM	0	1	55	1
Bin	MODE_TTTM	1	0	1656	1
Bin	MODE_ROM	0	1	51	1
Bin	MODE_ROM	1	0	1652	1
Bin	MODE_ACF	0	1	19	1
Bin	MODE_ACF	1	0	1620	1
Bin	MODE_TSTM	0	1	1027	1
Bin	MODE_TSTM	1	0	2627	1
Bin	MODE_RXBAM	0	1	1731	1
Bin	MODE_RXBAM	1	0	130	1
Bin	MODE_TXBBM	0	1	33	1
Bin	MODE_TXBBM	1	0	1634	1
Bin	MODE_SAM	0	1	55	1
Bin	MODE_SAM	1	0	1656	1
Bin	MODE_ERFM	0	1	153	1
Bin	MODE_ERFM	1	0	1754	1
Bin	SETTINGS_RTRLE	0	1	2454	1
Bin	SETTINGS_RTRLE	1	0	4054	1
Bin	SETTINGS_RTRTH(3)	0	1	22	1
Bin	SETTINGS_RTRTH(3)	1	0	1623	1
Bin	SETTINGS_RTRTH(2)	0	1	54	1
Bin	SETTINGS_RTRTH(2)	1	0	1655	1
Bin	SETTINGS_RTRTH(1)	0	1	22	1
Bin	SETTINGS_RTRTH(1)	1	0	1623	1
Bin	SETTINGS_RTRTH(0)	0	1	59	1
Bin	SETTINGS_RTRTH(0)	1	0	1660	1
Bin	SETTINGS_ILBP	0	1	130	1
Bin	SETTINGS_ILBP	1	0	1731	1
Bin	SETTINGS_ENA	0	1	6483	1
Bin	SETTINGS_ENA	1	0	8072	1
Bin	SETTINGS_NISOFD	0	1	130	1
Bin	SETTINGS_NISOFD	1	0	1731	1
Bin	SETTINGS_PEX	0	1	72	1
Bin	SETTINGS_PEX	1	0	1673	1
Bin	SETTINGS_TBFBO	0	1	2534	1
Bin	SETTINGS_TBFBO	1	0	944	1
Bin	SETTINGS_FDRF	0	1	4	1
Bin	SETTINGS_FDRF	1	0	1605	1
Bin	SETTINGS_PCHKE	0	1	112	1
Bin	SETTINGS_PCHKE	1	0	1713	1
Bin	COMMAND_RXRPMV	0	1	25	1
Bin	COMMAND_RXRPMV	1	0	3068	1
Bin	COMMAND_RRB	0	1	460	1
Bin	COMMAND_RRB	1	0	3068	1
Bin	COMMAND_CDO	0	1	20	1
Bin	COMMAND_CDO	1	0	3068	1
Bin	COMMAND_ERCRST	0	1	170	1
Bin	COMMAND_ERCRST	1	0	3068	1
Bin	COMMAND_RXFCRST	0	1	124	1
Bin	COMMAND_RXFCRST	1	0	3068	1
Bin	COMMAND_TXFCRST	0	1	124	1
Bin	COMMAND_TXFCRST	1	0	3068	1
Bin	COMMAND_CPEXS	0	1	60	1
Bin	COMMAND_CPEXS	1	0	3068	1
Bin	COMMAND_CRXPE	0	1	40	1
Bin	COMMAND_CRXPE	1	0	3068	1
Bin	COMMAND_CTXPE	0	1	440	1
Bin	COMMAND_CTXPE	1	0	3068	1
Bin	COMMAND_CTXDPE	0	1	40	1
Bin	COMMAND_CTXDPE	1	0	3068	1
Bin	INT_STAT_RXI	0	1	40	1
Bin	INT_STAT_RXI	1	0	1748	1
Bin	INT_STAT_TXI	0	1	42	1
Bin	INT_STAT_TXI	1	0	1748	1
Bin	INT_STAT_EWLI	0	1	30	1
Bin	INT_STAT_EWLI	1	0	1748	1
Bin	INT_STAT_DOI	0	1	16	1
Bin	INT_STAT_DOI	1	0	1748	1
Bin	INT_STAT_FCSI	0	1	80	1
Bin	INT_STAT_FCSI	1	0	1748	1
Bin	INT_STAT_ALI	0	1	5	1
Bin	INT_STAT_ALI	1	0	1748	1
Bin	INT_STAT_BEI	0	1	15	1
Bin	INT_STAT_BEI	1	0	1748	1
Bin	INT_STAT_OFI	0	1	5	1
Bin	INT_STAT_OFI	1	0	1748	1
Bin	INT_STAT_RXFI	0	1	15	1
Bin	INT_STAT_RXFI	1	0	1748	1
Bin	INT_STAT_BSI	0	1	34	1
Bin	INT_STAT_BSI	1	0	1748	1
Bin	INT_STAT_RBNEI	0	1	50	1
Bin	INT_STAT_RBNEI	1	0	1748	1
Bin	INT_STAT_TXBHCI	0	1	52	1
Bin	INT_STAT_TXBHCI	1	0	1748	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	0	1	66	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	1	0	2373	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	0	1	30	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	1	0	2409	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	0	1	50	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	1	0	2389	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	1	0	2419	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	1	0	2419	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	1	0	2419	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	0	1	476	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	1	0	2209	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	0	1	512	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	1	0	2173	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	0	1	492	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	1	0	2193	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	1	0	2163	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	1	0	2163	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	1	0	2163	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	0	1	66	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	1	0	2261	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	0	1	40	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	1	0	2287	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	0	1	50	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	1	0	2277	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	0	1	15	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	1	0	2312	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	1	0	2317	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	0	1	409	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	1	0	2142	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	0	1	435	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	1	0	2116	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	0	1	425	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	1	0	2126	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	0	1	460	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	1	0	2091	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	1	0	2086	1
Bin	BTR_PROP(6)	0	1	200	1
Bin	BTR_PROP(6)	1	0	1799	1
Bin	BTR_PROP(5)	0	1	309	1
Bin	BTR_PROP(5)	1	0	1907	1
Bin	BTR_PROP(4)	0	1	225	1
Bin	BTR_PROP(4)	1	0	1823	1
Bin	BTR_PROP(3)	0	1	273	1
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Bin	BTR_PROP(2)	0	1	3822	1
Bin	BTR_PROP(2)	1	0	2222	1
Bin	BTR_PROP(1)	0	1	262	1
Bin	BTR_PROP(1)	1	0	1860	1
Bin	BTR_PROP(0)	0	1	1793	1
Bin	BTR_PROP(0)	1	0	193	1
Bin	BTR_PH1(5)	0	1	318	1
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Bin	BTR_PH1(4)	0	1	254	1
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Bin	BTR_PH1(3)	0	1	263	1
Bin	BTR_PH1(3)	1	0	1862	1
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Bin	BTR_PH1(2)	1	0	2897	1
Bin	BTR_PH1(1)	0	1	1924	1
Bin	BTR_PH1(1)	1	0	324	1
Bin	BTR_PH1(0)	0	1	2090	1
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Bin	BTR_PH2(5)	1	0	1803	1
Bin	BTR_PH2(4)	0	1	349	1
Bin	BTR_PH2(4)	1	0	1947	1
Bin	BTR_PH2(3)	0	1	313	1
Bin	BTR_PH2(3)	1	0	1912	1
Bin	BTR_PH2(2)	0	1	3874	1
Bin	BTR_PH2(2)	1	0	2275	1
Bin	BTR_PH2(1)	0	1	3412	1
Bin	BTR_PH2(1)	1	0	5003	1
Bin	BTR_PH2(0)	0	1	2160	1
Bin	BTR_PH2(0)	1	0	559	1
Bin	BTR_BRP(7)	0	1	13	1
Bin	BTR_BRP(7)	1	0	1614	1
Bin	BTR_BRP(6)	0	1	14	1
Bin	BTR_BRP(6)	1	0	1615	1
Bin	BTR_BRP(5)	0	1	12	1
Bin	BTR_BRP(5)	1	0	1613	1
Bin	BTR_BRP(4)	0	1	16	1
Bin	BTR_BRP(4)	1	0	1617	1
Bin	BTR_BRP(3)	0	1	4831	1
Bin	BTR_BRP(3)	1	0	3242	1
Bin	BTR_BRP(2)	0	1	930	1
Bin	BTR_BRP(2)	1	0	2524	1
Bin	BTR_BRP(1)	0	1	4762	1
Bin	BTR_BRP(1)	1	0	3170	1
Bin	BTR_BRP(0)	0	1	2317	1
Bin	BTR_BRP(0)	1	0	3915	1
Bin	BTR_SJW(4)	0	1	204	1
Bin	BTR_SJW(4)	1	0	1802	1
Bin	BTR_SJW(3)	0	1	271	1
Bin	BTR_SJW(3)	1	0	1869	1
Bin	BTR_SJW(2)	0	1	971	1
Bin	BTR_SJW(2)	1	0	2568	1
Bin	BTR_SJW(1)	0	1	2624	1
Bin	BTR_SJW(1)	1	0	1032	1
Bin	BTR_SJW(0)	0	1	3116	1
Bin	BTR_SJW(0)	1	0	4713	1
Bin	BTR_FD_PROP_FD(5)	0	1	239	1
Bin	BTR_FD_PROP_FD(5)	1	0	1837	1
Bin	BTR_FD_PROP_FD(4)	0	1	292	1
Bin	BTR_FD_PROP_FD(4)	1	0	1890	1
Bin	BTR_FD_PROP_FD(3)	0	1	278	1
Bin	BTR_FD_PROP_FD(3)	1	0	1876	1
Bin	BTR_FD_PROP_FD(2)	0	1	1184	1
Bin	BTR_FD_PROP_FD(2)	1	0	2773	1
Bin	BTR_FD_PROP_FD(1)	0	1	4706	1
Bin	BTR_FD_PROP_FD(1)	1	0	3114	1
Bin	BTR_FD_PROP_FD(0)	0	1	3888	1
Bin	BTR_FD_PROP_FD(0)	1	0	2287	1
Bin	BTR_FD_PH1_FD(4)	0	1	245	1
Bin	BTR_FD_PH1_FD(4)	1	0	1844	1
Bin	BTR_FD_PH1_FD(3)	0	1	293	1
Bin	BTR_FD_PH1_FD(3)	1	0	1892	1
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Bin	BTR_FD_PH1_FD(2)	1	0	2765	1
Bin	BTR_FD_PH1_FD(1)	0	1	1695	1
Bin	BTR_FD_PH1_FD(1)	1	0	95	1
Bin	BTR_FD_PH1_FD(0)	0	1	3844	1
Bin	BTR_FD_PH1_FD(0)	1	0	2244	1
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Bin	BTR_FD_PH2_FD(4)	1	0	1887	1
Bin	BTR_FD_PH2_FD(3)	0	1	315	1
Bin	BTR_FD_PH2_FD(3)	1	0	1914	1
Bin	BTR_FD_PH2_FD(2)	0	1	1212	1
Bin	BTR_FD_PH2_FD(2)	1	0	2802	1
Bin	BTR_FD_PH2_FD(1)	0	1	1734	1
Bin	BTR_FD_PH2_FD(1)	1	0	134	1
Bin	BTR_FD_PH2_FD(0)	0	1	3870	1
Bin	BTR_FD_PH2_FD(0)	1	0	2269	1
Bin	BTR_FD_BRP_FD(7)	0	1	18	1
Bin	BTR_FD_BRP_FD(7)	1	0	1619	1
Bin	BTR_FD_BRP_FD(6)	0	1	29	1
Bin	BTR_FD_BRP_FD(6)	1	0	1630	1
Bin	BTR_FD_BRP_FD(5)	0	1	17	1
Bin	BTR_FD_BRP_FD(5)	1	0	1618	1
Bin	BTR_FD_BRP_FD(4)	0	1	30	1
Bin	BTR_FD_BRP_FD(4)	1	0	1631	1
Bin	BTR_FD_BRP_FD(3)	0	1	27	1
Bin	BTR_FD_BRP_FD(3)	1	0	1628	1
Bin	BTR_FD_BRP_FD(2)	0	1	4843	1
Bin	BTR_FD_BRP_FD(2)	1	0	3254	1
Bin	BTR_FD_BRP_FD(1)	0	1	757	1
Bin	BTR_FD_BRP_FD(1)	1	0	2355	1
Bin	BTR_FD_BRP_FD(0)	0	1	2600	1
Bin	BTR_FD_BRP_FD(0)	1	0	4192	1
Bin	BTR_FD_SJW_FD(4)	0	1	247	1
Bin	BTR_FD_SJW_FD(4)	1	0	1845	1
Bin	BTR_FD_SJW_FD(3)	0	1	289	1
Bin	BTR_FD_SJW_FD(3)	1	0	1887	1
Bin	BTR_FD_SJW_FD(2)	0	1	916	1
Bin	BTR_FD_SJW_FD(2)	1	0	2513	1
Bin	BTR_FD_SJW_FD(1)	0	1	2568	1
Bin	BTR_FD_SJW_FD(1)	1	0	976	1
Bin	BTR_FD_SJW_FD(0)	0	1	953	1
Bin	BTR_FD_SJW_FD(0)	1	0	2550	1
Bin	EWL_EW_LIMIT(7)	0	1	78	1
Bin	EWL_EW_LIMIT(7)	1	0	1679	1
Bin	EWL_EW_LIMIT(6)	0	1	1686	1
Bin	EWL_EW_LIMIT(6)	1	0	85	1
Bin	EWL_EW_LIMIT(5)	0	1	1672	1
Bin	EWL_EW_LIMIT(5)	1	0	71	1
Bin	EWL_EW_LIMIT(4)	0	1	72	1
Bin	EWL_EW_LIMIT(4)	1	0	1673	1
Bin	EWL_EW_LIMIT(3)	0	1	75	1
Bin	EWL_EW_LIMIT(3)	1	0	1676	1
Bin	EWL_EW_LIMIT(2)	0	1	85	1
Bin	EWL_EW_LIMIT(2)	1	0	1686	1
Bin	EWL_EW_LIMIT(1)	0	1	88	1
Bin	EWL_EW_LIMIT(1)	1	0	1689	1
Bin	EWL_EW_LIMIT(0)	0	1	81	1
Bin	EWL_EW_LIMIT(0)	1	0	1682	1
Bin	ERP_ERP_LIMIT(7)	0	1	1732	1
Bin	ERP_ERP_LIMIT(7)	1	0	131	1
Bin	ERP_ERP_LIMIT(6)	0	1	25	1
Bin	ERP_ERP_LIMIT(6)	1	0	1626	1
Bin	ERP_ERP_LIMIT(5)	0	1	21	1
Bin	ERP_ERP_LIMIT(5)	1	0	1622	1
Bin	ERP_ERP_LIMIT(4)	0	1	26	1
Bin	ERP_ERP_LIMIT(4)	1	0	1627	1
Bin	ERP_ERP_LIMIT(3)	0	1	21	1
Bin	ERP_ERP_LIMIT(3)	1	0	1622	1
Bin	ERP_ERP_LIMIT(2)	0	1	26	1
Bin	ERP_ERP_LIMIT(2)	1	0	1627	1
Bin	ERP_ERP_LIMIT(1)	0	1	28	1
Bin	ERP_ERP_LIMIT(1)	1	0	1629	1
Bin	ERP_ERP_LIMIT(0)	0	1	30	1
Bin	ERP_ERP_LIMIT(0)	1	0	1631	1
Bin	CTR_PRES_CTPV(8)	0	1	253	1
Bin	CTR_PRES_CTPV(8)	1	0	1854	1
Bin	CTR_PRES_CTPV(7)	0	1	2608	1
Bin	CTR_PRES_CTPV(7)	1	0	4209	1
Bin	CTR_PRES_CTPV(6)	0	1	733	1
Bin	CTR_PRES_CTPV(6)	1	0	2334	1
Bin	CTR_PRES_CTPV(5)	0	1	2611	1
Bin	CTR_PRES_CTPV(5)	1	0	4212	1
Bin	CTR_PRES_CTPV(4)	0	1	2773	1
Bin	CTR_PRES_CTPV(4)	1	0	4374	1
Bin	CTR_PRES_CTPV(3)	0	1	893	1
Bin	CTR_PRES_CTPV(3)	1	0	2494	1
Bin	CTR_PRES_CTPV(2)	0	1	2887	1
Bin	CTR_PRES_CTPV(2)	1	0	4488	1
Bin	CTR_PRES_CTPV(1)	0	1	1015	1
Bin	CTR_PRES_CTPV(1)	1	0	2616	1
Bin	CTR_PRES_CTPV(0)	0	1	804	1
Bin	CTR_PRES_CTPV(0)	1	0	2405	1
Bin	CTR_PRES_PTX	0	1	19125	1
Bin	CTR_PRES_PTX	1	0	44590	1
Bin	CTR_PRES_PRX	0	1	19522	1
Bin	CTR_PRES_PRX	1	0	44590	1
Bin	CTR_PRES_ENORM	0	1	6369	1
Bin	CTR_PRES_ENORM	1	0	44590	1
Bin	CTR_PRES_EFD	0	1	6369	1
Bin	CTR_PRES_EFD	1	0	44590	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	0	1	389	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	1	0	1990	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	0	1	349	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	1	0	1950	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	0	1	339	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	1	0	1940	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	0	1	365	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	1	0	1966	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	0	1	366	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	1	0	1967	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	0	1	378	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	1	0	1979	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	0	1	395	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	1	0	1996	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	0	1	366	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	1	0	1967	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	0	1	383	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	1	0	1984	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	0	1	368	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	1	0	1969	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	0	1	411	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	1	0	2012	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	0	1	97	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	1	0	1698	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	0	1	82	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	1	0	1683	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	0	1	94	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	1	0	1695	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	0	1	106	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	1	0	1707	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	0	1	118	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	1	0	1719	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	0	1	131	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	1	0	1732	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	0	1	106	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	1	0	1707	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	0	1	249	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	1	0	1850	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	0	1	250	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	1	0	1851	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	0	1	252	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	1	0	1853	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	0	1	281	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	1	0	1882	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	0	1	265	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	1	0	1866	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	0	1	278	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	1	0	1879	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	0	1	239	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	1	0	1840	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	0	1	267	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	1	0	1868	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	0	1	280	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	1	0	1881	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	0	1	242	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	1	0	1843	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	0	1	270	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	1	0	1871	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	0	1	816	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	1	0	2417	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	0	1	793	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	1	0	2394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	0	1	803	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	1	0	2404	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	0	1	791	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	1	0	2392	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	0	1	805	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	1	0	2406	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	0	1	764	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	1	0	2365	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	0	1	832	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	1	0	2433	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	0	1	772	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	1	0	2373	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	0	1	763	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	1	0	2364	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	0	1	832	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	1	0	2433	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	0	1	836	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	1	0	2437	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	0	1	395	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	1	0	1996	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	0	1	429	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	1	0	2030	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	0	1	403	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	1	0	2004	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	0	1	415	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	1	0	2016	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	0	1	415	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	1	0	2016	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	0	1	413	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	1	0	2014	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	0	1	397	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	1	0	1998	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	0	1	398	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	1	0	1999	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	0	1	402	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	1	0	2003	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	0	1	394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	1	0	1995	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	0	1	421	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	1	0	2022	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	0	1	396	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	1	0	1997	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	0	1	423	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	1	0	2024	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	0	1	378	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	1	0	1979	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	0	1	410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	1	0	2011	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	0	1	91	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	1	0	1692	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	0	1	80	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	1	0	1681	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	0	1	102	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	1	0	1703	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	0	1	91	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	1	0	1692	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	0	1	82	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	1	0	1683	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	0	1	105	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	1	0	1706	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	0	1	89	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	1	0	1690	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	0	1	22	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	1	0	1623	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	0	1	15	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	1	0	1616	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	0	1	33	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	1	0	1634	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	0	1	22	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	1	0	1623	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	0	1	36	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	1	0	1637	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	0	1	35	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	1	0	1636	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	0	1	34	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	1	0	1635	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	0	1	63	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	1	0	1664	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	0	1	66	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	1	0	1667	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	1	0	1672	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	1	0	1672	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	0	1	65	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	1	0	1666	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	0	1	68	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	1	0	1669	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	0	1	67	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	1	0	1668	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	0	1	59	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	1	0	1660	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	0	1	186	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	1	0	1787	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	0	1	191	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	1	0	1792	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	0	1	195	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	1	0	1796	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	0	1	200	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	1	0	1801	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	0	1	198	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	1	0	1799	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	0	1	204	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	1	0	1805	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	0	1	206	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	1	0	1807	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	0	1	198	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	1	0	1799	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	0	1	202	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	1	0	1803	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	0	1	213	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	1	0	1814	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	0	1	212	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	1	0	1813	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	0	1	100	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	1	0	1701	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	1	0	1707	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	0	1	92	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	1	0	1693	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	0	1	111	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	1	0	1712	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	1	0	1702	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	0	1	91	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	1	0	1692	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	0	1	103	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	1	0	1704	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	1	0	1702	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	0	1	97	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	1	0	1698	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	0	1	104	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	1	0	1705	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	0	1	95	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	1	0	1696	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	0	1	102	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	1	0	1703	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	1	0	1707	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	0	1	100	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	1	0	1701	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	0	1	107	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	1	0	1708	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	0	1	94	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	1	0	1695	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	0	1	94	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	1	0	1695	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	0	1	100	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	1	0	1701	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	0	1	86	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	1	0	1687	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	0	1	100	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	1	0	1701	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	0	1	104	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	1	0	1705	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	0	1	93	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	1	0	1694	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	0	1	98	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	1	0	1699	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	0	1	88	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	1	0	1689	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	0	1	97	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	1	0	1698	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	0	1	79	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	1	0	1680	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	0	1	87	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	1	0	1688	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	0	1	22	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	1	0	1623	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	0	1	17	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	1	0	1618	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	0	1	30	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	1	0	1631	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	0	1	21	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	1	0	1622	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	0	1	37	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	1	0	1638	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	1	0	1635	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	1	0	1635	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	1	0	1667	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	0	1	71	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	1	0	1672	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	0	1	63	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	1	0	1664	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	0	1	69	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	1	0	1670	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	1	0	1663	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	0	1	71	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	1	0	1672	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	0	1	69	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	1	0	1670	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	1	0	1663	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	1	0	1668	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	1	0	1667	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	0	1	58	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	1	0	1659	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	0	1	184	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	1	0	1785	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	0	1	182	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	1	0	1783	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	0	1	199	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	1	0	1800	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	0	1	193	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	1	0	1794	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	0	1	190	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	1	0	1791	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	0	1	207	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	1	0	1808	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	0	1	213	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	1	0	1814	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	1	0	1799	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	1	0	1799	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	0	1	203	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	1	0	1804	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	0	1	214	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	1	0	1815	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	1	0	1701	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	0	1	103	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	1	0	1704	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	1	0	1701	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	0	1	99	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	1	0	1700	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	0	1	105	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	1	0	1706	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	0	1	86	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	1	0	1687	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	1	0	1699	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	0	1	104	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	1	0	1705	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	0	1	102	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	1	0	1703	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	0	1	95	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	1	0	1696	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	0	1	96	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	1	0	1697	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	0	1	105	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	1	0	1706	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	0	1	110	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	1	0	1711	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	1	0	1699	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	0	1	95	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	1	0	1696	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	1	0	1602	1
Bin	FILTER_CONTROL_FANB	0	1	2052	1
Bin	FILTER_CONTROL_FANB	1	0	451	1
Bin	FILTER_CONTROL_FANE	0	1	2029	1
Bin	FILTER_CONTROL_FANE	1	0	428	1
Bin	FILTER_CONTROL_FAFB	0	1	2060	1
Bin	FILTER_CONTROL_FAFB	1	0	459	1
Bin	FILTER_CONTROL_FAFE	0	1	2029	1
Bin	FILTER_CONTROL_FAFE	1	0	428	1
Bin	FILTER_CONTROL_FBNB	0	1	106	1
Bin	FILTER_CONTROL_FBNB	1	0	1707	1
Bin	FILTER_CONTROL_FBNE	0	1	105	1
Bin	FILTER_CONTROL_FBNE	1	0	1706	1
Bin	FILTER_CONTROL_FBFB	0	1	107	1
Bin	FILTER_CONTROL_FBFB	1	0	1708	1
Bin	FILTER_CONTROL_FBFE	0	1	105	1
Bin	FILTER_CONTROL_FBFE	1	0	1706	1
Bin	FILTER_CONTROL_FCNB	0	1	106	1
Bin	FILTER_CONTROL_FCNB	1	0	1707	1
Bin	FILTER_CONTROL_FCNE	0	1	105	1
Bin	FILTER_CONTROL_FCNE	1	0	1706	1
Bin	FILTER_CONTROL_FCFB	0	1	107	1
Bin	FILTER_CONTROL_FCFB	1	0	1708	1
Bin	FILTER_CONTROL_FCFE	0	1	105	1
Bin	FILTER_CONTROL_FCFE	1	0	1706	1
Bin	FILTER_CONTROL_FRNB	0	1	6	1
Bin	FILTER_CONTROL_FRNB	1	0	1607	1
Bin	FILTER_CONTROL_FRNE	0	1	5	1
Bin	FILTER_CONTROL_FRNE	1	0	1606	1
Bin	FILTER_CONTROL_FRFB	0	1	6	1
Bin	FILTER_CONTROL_FRFB	1	0	1607	1
Bin	FILTER_CONTROL_FRFE	0	1	5	1
Bin	FILTER_CONTROL_FRFE	1	0	1606	1
Bin	RX_SETTINGS_RTSOP	0	1	5	1
Bin	RX_SETTINGS_RTSOP	1	0	1606	1
Bin	RX_DATA_READ	0	1	51790	1
Bin	RX_DATA_READ	1	0	53391	1
Bin	TX_COMMAND_TXCE	0	1	354	1
Bin	TX_COMMAND_TXCE	1	0	25076	1
Bin	TX_COMMAND_TXCR	0	1	21387	1
Bin	TX_COMMAND_TXCR	1	0	25076	1
Bin	TX_COMMAND_TXCA	0	1	1734	1
Bin	TX_COMMAND_TXCA	1	0	25076	1
Bin	TX_COMMAND_TXB1	0	1	6553	1
Bin	TX_COMMAND_TXB1	1	0	8149	1
Bin	TX_COMMAND_TXB2	0	1	5587	1
Bin	TX_COMMAND_TXB2	1	0	7188	1
Bin	TX_COMMAND_TXB3	0	1	332	1
Bin	TX_COMMAND_TXB3	1	0	1933	1
Bin	TX_COMMAND_TXB4	0	1	345	1
Bin	TX_COMMAND_TXB4	1	0	1946	1
Bin	TX_COMMAND_TXB5	0	1	91	1
Bin	TX_COMMAND_TXB5	1	0	1692	1
Bin	TX_COMMAND_TXB6	0	1	73	1
Bin	TX_COMMAND_TXB6	1	0	1674	1
Bin	TX_COMMAND_TXB7	0	1	87	1
Bin	TX_COMMAND_TXB7	1	0	1688	1
Bin	TX_COMMAND_TXB8	0	1	74	1
Bin	TX_COMMAND_TXB8	1	0	1675	1
Bin	TX_PRIORITY_TXT1P(2)	0	1	105	1
Bin	TX_PRIORITY_TXT1P(2)	1	0	1706	1
Bin	TX_PRIORITY_TXT1P(1)	0	1	111	1
Bin	TX_PRIORITY_TXT1P(1)	1	0	1712	1
Bin	TX_PRIORITY_TXT1P(0)	0	1	1723	1
Bin	TX_PRIORITY_TXT1P(0)	1	0	122	1
Bin	TX_PRIORITY_TXT2P(2)	0	1	94	1
Bin	TX_PRIORITY_TXT2P(2)	1	0	1695	1
Bin	TX_PRIORITY_TXT2P(1)	0	1	131	1
Bin	TX_PRIORITY_TXT2P(1)	1	0	1732	1
Bin	TX_PRIORITY_TXT2P(0)	0	1	124	1
Bin	TX_PRIORITY_TXT2P(0)	1	0	1725	1
Bin	TX_PRIORITY_TXT3P(2)	0	1	72	1
Bin	TX_PRIORITY_TXT3P(2)	1	0	1673	1
Bin	TX_PRIORITY_TXT3P(1)	0	1	103	1
Bin	TX_PRIORITY_TXT3P(1)	1	0	1704	1
Bin	TX_PRIORITY_TXT3P(0)	0	1	96	1
Bin	TX_PRIORITY_TXT3P(0)	1	0	1697	1
Bin	TX_PRIORITY_TXT4P(2)	0	1	77	1
Bin	TX_PRIORITY_TXT4P(2)	1	0	1678	1
Bin	TX_PRIORITY_TXT4P(1)	0	1	91	1
Bin	TX_PRIORITY_TXT4P(1)	1	0	1692	1
Bin	TX_PRIORITY_TXT4P(0)	0	1	99	1
Bin	TX_PRIORITY_TXT4P(0)	1	0	1700	1
Bin	TX_PRIORITY_TXT5P(2)	0	1	23	1
Bin	TX_PRIORITY_TXT5P(2)	1	0	1624	1
Bin	TX_PRIORITY_TXT5P(1)	0	1	33	1
Bin	TX_PRIORITY_TXT5P(1)	1	0	1634	1
Bin	TX_PRIORITY_TXT5P(0)	0	1	29	1
Bin	TX_PRIORITY_TXT5P(0)	1	0	1630	1
Bin	TX_PRIORITY_TXT6P(2)	0	1	28	1
Bin	TX_PRIORITY_TXT6P(2)	1	0	1629	1
Bin	TX_PRIORITY_TXT6P(1)	0	1	31	1
Bin	TX_PRIORITY_TXT6P(1)	1	0	1632	1
Bin	TX_PRIORITY_TXT6P(0)	0	1	33	1
Bin	TX_PRIORITY_TXT6P(0)	1	0	1634	1
Bin	TX_PRIORITY_TXT7P(2)	0	1	26	1
Bin	TX_PRIORITY_TXT7P(2)	1	0	1627	1
Bin	TX_PRIORITY_TXT7P(1)	0	1	27	1
Bin	TX_PRIORITY_TXT7P(1)	1	0	1628	1
Bin	TX_PRIORITY_TXT7P(0)	0	1	31	1
Bin	TX_PRIORITY_TXT7P(0)	1	0	1632	1
Bin	TX_PRIORITY_TXT8P(2)	0	1	27	1
Bin	TX_PRIORITY_TXT8P(2)	1	0	1628	1
Bin	TX_PRIORITY_TXT8P(1)	0	1	31	1
Bin	TX_PRIORITY_TXT8P(1)	1	0	1632	1
Bin	TX_PRIORITY_TXT8P(0)	0	1	28	1
Bin	TX_PRIORITY_TXT8P(0)	1	0	1629	1
Bin	SSP_CFG_SSP_OFFSET(7)	0	1	24	1
Bin	SSP_CFG_SSP_OFFSET(7)	1	0	1625	1
Bin	SSP_CFG_SSP_OFFSET(6)	0	1	23	1
Bin	SSP_CFG_SSP_OFFSET(6)	1	0	1624	1
Bin	SSP_CFG_SSP_OFFSET(5)	0	1	48	1
Bin	SSP_CFG_SSP_OFFSET(5)	1	0	1649	1
Bin	SSP_CFG_SSP_OFFSET(4)	0	1	50	1
Bin	SSP_CFG_SSP_OFFSET(4)	1	0	1651	1
Bin	SSP_CFG_SSP_OFFSET(3)	0	1	4306	1
Bin	SSP_CFG_SSP_OFFSET(3)	1	0	2716	1
Bin	SSP_CFG_SSP_OFFSET(2)	0	1	535	1
Bin	SSP_CFG_SSP_OFFSET(2)	1	0	2135	1
Bin	SSP_CFG_SSP_OFFSET(1)	0	1	2902	1
Bin	SSP_CFG_SSP_OFFSET(1)	1	0	1313	1
Bin	SSP_CFG_SSP_OFFSET(0)	0	1	2397	1
Bin	SSP_CFG_SSP_OFFSET(0)	1	0	3997	1
Bin	SSP_CFG_SSP_SRC(1)	0	1	45	1
Bin	SSP_CFG_SSP_SRC(1)	1	0	1646	1
Bin	SSP_CFG_SSP_SRC(0)	0	1	815	1
Bin	SSP_CFG_SSP_SRC(0)	1	0	2405	1

Port:

MR_TST_OUT

	Element	From	To	Count	Threshold
Bin	TST_CONTROL_TMAENA	0	1	648	1
Bin	TST_CONTROL_TMAENA	1	0	2249	1
Bin	TST_CONTROL_TWRSTB	0	1	32343	1
Bin	TST_CONTROL_TWRSTB	1	0	35235	1
Bin	TST_DEST_TST_ADDR(15)	0	1	5	1
Bin	TST_DEST_TST_ADDR(15)	1	0	47044	1
Bin	TST_DEST_TST_ADDR(14)	0	1	5	1
Bin	TST_DEST_TST_ADDR(14)	1	0	47044	1
Bin	TST_DEST_TST_ADDR(13)	0	1	5	1
Bin	TST_DEST_TST_ADDR(13)	1	0	47044	1
Bin	TST_DEST_TST_ADDR(12)	0	1	5	1
Bin	TST_DEST_TST_ADDR(12)	1	0	47044	1
Bin	TST_DEST_TST_ADDR(11)	0	1	325	1
Bin	TST_DEST_TST_ADDR(11)	1	0	47333	1
Bin	TST_DEST_TST_ADDR(10)	0	1	645	1
Bin	TST_DEST_TST_ADDR(10)	1	0	47653	1
Bin	TST_DEST_TST_ADDR(9)	0	1	1285	1
Bin	TST_DEST_TST_ADDR(9)	1	0	48293	1
Bin	TST_DEST_TST_ADDR(8)	0	1	2565	1
Bin	TST_DEST_TST_ADDR(8)	1	0	49573	1
Bin	TST_DEST_TST_ADDR(7)	0	1	5125	1
Bin	TST_DEST_TST_ADDR(7)	1	0	52133	1
Bin	TST_DEST_TST_ADDR(6)	0	1	11205	1
Bin	TST_DEST_TST_ADDR(6)	1	0	58120	1
Bin	TST_DEST_TST_ADDR(5)	0	1	22405	1
Bin	TST_DEST_TST_ADDR(5)	1	0	69320	1
Bin	TST_DEST_TST_ADDR(4)	0	1	3617	1
Bin	TST_DEST_TST_ADDR(4)	1	0	5218	1
Bin	TST_DEST_TST_ADDR(3)	0	1	5036	1
Bin	TST_DEST_TST_ADDR(3)	1	0	6637	1
Bin	TST_DEST_TST_ADDR(2)	0	1	10348	1
Bin	TST_DEST_TST_ADDR(2)	1	0	11949	1
Bin	TST_DEST_TST_ADDR(1)	0	1	22453	1
Bin	TST_DEST_TST_ADDR(1)	1	0	24054	1
Bin	TST_DEST_TST_ADDR(0)	0	1	44900	1
Bin	TST_DEST_TST_ADDR(0)	1	0	46501	1
Bin	TST_DEST_TST_MTGT(3)	0	1	236	1
Bin	TST_DEST_TST_MTGT(3)	1	0	1837	1
Bin	TST_DEST_TST_MTGT(2)	0	1	373	1
Bin	TST_DEST_TST_MTGT(2)	1	0	1974	1
Bin	TST_DEST_TST_MTGT(1)	0	1	514	1
Bin	TST_DEST_TST_MTGT(1)	1	0	2115	1
Bin	TST_DEST_TST_MTGT(0)	0	1	979	1
Bin	TST_DEST_TST_MTGT(0)	1	0	2580	1
Bin	TST_WDATA_TST_WDATA(31)	0	1	1524	1
Bin	TST_WDATA_TST_WDATA(31)	1	0	3125	1
Bin	TST_WDATA_TST_WDATA(30)	0	1	1474	1
Bin	TST_WDATA_TST_WDATA(30)	1	0	3075	1
Bin	TST_WDATA_TST_WDATA(29)	0	1	1522	1
Bin	TST_WDATA_TST_WDATA(29)	1	0	3123	1
Bin	TST_WDATA_TST_WDATA(28)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(28)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(27)	0	1	1638	1
Bin	TST_WDATA_TST_WDATA(27)	1	0	3239	1
Bin	TST_WDATA_TST_WDATA(26)	0	1	1628	1
Bin	TST_WDATA_TST_WDATA(26)	1	0	3229	1
Bin	TST_WDATA_TST_WDATA(25)	0	1	1652	1
Bin	TST_WDATA_TST_WDATA(25)	1	0	3253	1
Bin	TST_WDATA_TST_WDATA(24)	0	1	1686	1
Bin	TST_WDATA_TST_WDATA(24)	1	0	3287	1
Bin	TST_WDATA_TST_WDATA(23)	0	1	1580	1
Bin	TST_WDATA_TST_WDATA(23)	1	0	3181	1
Bin	TST_WDATA_TST_WDATA(22)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(22)	1	0	3130	1
Bin	TST_WDATA_TST_WDATA(21)	0	1	1580	1
Bin	TST_WDATA_TST_WDATA(21)	1	0	3181	1
Bin	TST_WDATA_TST_WDATA(20)	0	1	1659	1
Bin	TST_WDATA_TST_WDATA(20)	1	0	3260	1
Bin	TST_WDATA_TST_WDATA(19)	0	1	1673	1
Bin	TST_WDATA_TST_WDATA(19)	1	0	3274	1
Bin	TST_WDATA_TST_WDATA(18)	0	1	1660	1
Bin	TST_WDATA_TST_WDATA(18)	1	0	3261	1
Bin	TST_WDATA_TST_WDATA(17)	0	1	1624	1
Bin	TST_WDATA_TST_WDATA(17)	1	0	3225	1
Bin	TST_WDATA_TST_WDATA(16)	0	1	1658	1
Bin	TST_WDATA_TST_WDATA(16)	1	0	3259	1
Bin	TST_WDATA_TST_WDATA(15)	0	1	1598	1
Bin	TST_WDATA_TST_WDATA(15)	1	0	3199	1
Bin	TST_WDATA_TST_WDATA(14)	0	1	1523	1
Bin	TST_WDATA_TST_WDATA(14)	1	0	3124	1
Bin	TST_WDATA_TST_WDATA(13)	0	1	1588	1
Bin	TST_WDATA_TST_WDATA(13)	1	0	3189	1
Bin	TST_WDATA_TST_WDATA(12)	0	1	1665	1
Bin	TST_WDATA_TST_WDATA(12)	1	0	3266	1
Bin	TST_WDATA_TST_WDATA(11)	0	1	1665	1
Bin	TST_WDATA_TST_WDATA(11)	1	0	3266	1
Bin	TST_WDATA_TST_WDATA(10)	0	1	1644	1
Bin	TST_WDATA_TST_WDATA(10)	1	0	3245	1
Bin	TST_WDATA_TST_WDATA(9)	0	1	1680	1
Bin	TST_WDATA_TST_WDATA(9)	1	0	3281	1
Bin	TST_WDATA_TST_WDATA(8)	0	1	1711	1
Bin	TST_WDATA_TST_WDATA(8)	1	0	3312	1
Bin	TST_WDATA_TST_WDATA(7)	0	1	1605	1
Bin	TST_WDATA_TST_WDATA(7)	1	0	3206	1
Bin	TST_WDATA_TST_WDATA(6)	0	1	1553	1
Bin	TST_WDATA_TST_WDATA(6)	1	0	3154	1
Bin	TST_WDATA_TST_WDATA(5)	0	1	1586	1
Bin	TST_WDATA_TST_WDATA(5)	1	0	3187	1
Bin	TST_WDATA_TST_WDATA(4)	0	1	1660	1
Bin	TST_WDATA_TST_WDATA(4)	1	0	3261	1
Bin	TST_WDATA_TST_WDATA(3)	0	1	1643	1
Bin	TST_WDATA_TST_WDATA(3)	1	0	3244	1
Bin	TST_WDATA_TST_WDATA(2)	0	1	1661	1
Bin	TST_WDATA_TST_WDATA(2)	1	0	3262	1
Bin	TST_WDATA_TST_WDATA(1)	0	1	1697	1
Bin	TST_WDATA_TST_WDATA(1)	1	0	3298	1
Bin	TST_WDATA_TST_WDATA(0)	0	1	1695	1
Bin	TST_WDATA_TST_WDATA(0)	1	0	3296	1

Port:

CC_STAT

	Element	From	To	Count	Threshold
Bin	IS_ERR_ACTIVE	0	1	8426	1
Bin	IS_ERR_ACTIVE	1	0	8415	1
Bin	IS_ERR_PASSIVE	0	1	761	1
Bin	IS_ERR_PASSIVE	1	0	2362	1
Bin	IS_BUS_OFF	0	1	8227	1
Bin	IS_BUS_OFF	1	0	8238	1
Bin	IS_TRANSMITTER	0	1	20317	1
Bin	IS_TRANSMITTER	1	0	21917	1
Bin	IS_RECEIVER	0	1	30908	1
Bin	IS_RECEIVER	1	0	32502	1
Bin	IS_IDLE	0	1	55892	1
Bin	IS_IDLE	1	0	57490	1
Bin	TX_ERR_CTR(8)	0	1	246	1
Bin	TX_ERR_CTR(8)	1	0	1847	1
Bin	TX_ERR_CTR(7)	0	1	506	1
Bin	TX_ERR_CTR(7)	1	0	2107	1
Bin	TX_ERR_CTR(6)	0	1	504	1
Bin	TX_ERR_CTR(6)	1	0	2105	1
Bin	TX_ERR_CTR(5)	0	1	787	1
Bin	TX_ERR_CTR(5)	1	0	2388	1
Bin	TX_ERR_CTR(4)	0	1	1957	1
Bin	TX_ERR_CTR(4)	1	0	3557	1
Bin	TX_ERR_CTR(3)	0	1	12521	1
Bin	TX_ERR_CTR(3)	1	0	14122	1
Bin	TX_ERR_CTR(2)	0	1	2978	1
Bin	TX_ERR_CTR(2)	1	0	4579	1
Bin	TX_ERR_CTR(1)	0	1	3314	1
Bin	TX_ERR_CTR(1)	1	0	4915	1
Bin	TX_ERR_CTR(0)	0	1	3548	1
Bin	TX_ERR_CTR(0)	1	0	5149	1
Bin	RX_ERR_CTR(8)	0	1	126	1
Bin	RX_ERR_CTR(8)	1	0	1727	1
Bin	RX_ERR_CTR(7)	0	1	344	1
Bin	RX_ERR_CTR(7)	1	0	1945	1
Bin	RX_ERR_CTR(6)	0	1	262	1
Bin	RX_ERR_CTR(6)	1	0	1860	1
Bin	RX_ERR_CTR(5)	0	1	343	1
Bin	RX_ERR_CTR(5)	1	0	1943	1
Bin	RX_ERR_CTR(4)	0	1	501	1
Bin	RX_ERR_CTR(4)	1	0	2101	1
Bin	RX_ERR_CTR(3)	0	1	680	1
Bin	RX_ERR_CTR(3)	1	0	2280	1
Bin	RX_ERR_CTR(2)	0	1	639	1
Bin	RX_ERR_CTR(2)	1	0	2240	1
Bin	RX_ERR_CTR(1)	0	1	1198	1
Bin	RX_ERR_CTR(1)	1	0	2799	1
Bin	RX_ERR_CTR(0)	0	1	11242	1
Bin	RX_ERR_CTR(0)	1	0	12836	1
Bin	STATUS_PEXS	0	1	75	1
Bin	STATUS_PEXS	1	0	1676	1
Bin	NORM_ERR_CTR(15)	0	1	67	1
Bin	NORM_ERR_CTR(15)	1	0	1665	1
Bin	NORM_ERR_CTR(14)	0	1	65	1
Bin	NORM_ERR_CTR(14)	1	0	1663	1
Bin	NORM_ERR_CTR(13)	0	1	66	1
Bin	NORM_ERR_CTR(13)	1	0	1662	1
Bin	NORM_ERR_CTR(12)	0	1	61	1
Bin	NORM_ERR_CTR(12)	1	0	1659	1
Bin	NORM_ERR_CTR(11)	0	1	71	1
Bin	NORM_ERR_CTR(11)	1	0	1670	1
Bin	NORM_ERR_CTR(10)	0	1	67	1
Bin	NORM_ERR_CTR(10)	1	0	1665	1
Bin	NORM_ERR_CTR(9)	0	1	54	1
Bin	NORM_ERR_CTR(9)	1	0	1654	1
Bin	NORM_ERR_CTR(8)	0	1	71	1
Bin	NORM_ERR_CTR(8)	1	0	1668	1
Bin	NORM_ERR_CTR(7)	0	1	83	1
Bin	NORM_ERR_CTR(7)	1	0	1682	1
Bin	NORM_ERR_CTR(6)	0	1	97	1
Bin	NORM_ERR_CTR(6)	1	0	1695	1
Bin	NORM_ERR_CTR(5)	0	1	150	1
Bin	NORM_ERR_CTR(5)	1	0	1747	1
Bin	NORM_ERR_CTR(4)	0	1	271	1
Bin	NORM_ERR_CTR(4)	1	0	1869	1
Bin	NORM_ERR_CTR(3)	0	1	605	1
Bin	NORM_ERR_CTR(3)	1	0	2200	1
Bin	NORM_ERR_CTR(2)	0	1	1369	1
Bin	NORM_ERR_CTR(2)	1	0	2967	1
Bin	NORM_ERR_CTR(1)	0	1	3083	1
Bin	NORM_ERR_CTR(1)	1	0	4677	1
Bin	NORM_ERR_CTR(0)	0	1	11506	1
Bin	NORM_ERR_CTR(0)	1	0	13100	1
Bin	DATA_ERR_CTR(15)	0	1	59	1
Bin	DATA_ERR_CTR(15)	1	0	1657	1
Bin	DATA_ERR_CTR(14)	0	1	68	1
Bin	DATA_ERR_CTR(14)	1	0	1666	1
Bin	DATA_ERR_CTR(13)	0	1	70	1
Bin	DATA_ERR_CTR(13)	1	0	1669	1
Bin	DATA_ERR_CTR(12)	0	1	66	1
Bin	DATA_ERR_CTR(12)	1	0	1665	1
Bin	DATA_ERR_CTR(11)	0	1	63	1
Bin	DATA_ERR_CTR(11)	1	0	1663	1
Bin	DATA_ERR_CTR(10)	0	1	68	1
Bin	DATA_ERR_CTR(10)	1	0	1666	1
Bin	DATA_ERR_CTR(9)	0	1	77	1
Bin	DATA_ERR_CTR(9)	1	0	1674	1
Bin	DATA_ERR_CTR(8)	0	1	90	1
Bin	DATA_ERR_CTR(8)	1	0	1688	1
Bin	DATA_ERR_CTR(7)	0	1	99	1
Bin	DATA_ERR_CTR(7)	1	0	1698	1
Bin	DATA_ERR_CTR(6)	0	1	126	1
Bin	DATA_ERR_CTR(6)	1	0	1723	1
Bin	DATA_ERR_CTR(5)	0	1	212	1
Bin	DATA_ERR_CTR(5)	1	0	1809	1
Bin	DATA_ERR_CTR(4)	0	1	363	1
Bin	DATA_ERR_CTR(4)	1	0	1962	1
Bin	DATA_ERR_CTR(3)	0	1	679	1
Bin	DATA_ERR_CTR(3)	1	0	2278	1
Bin	DATA_ERR_CTR(2)	0	1	1288	1
Bin	DATA_ERR_CTR(2)	1	0	2888	1
Bin	DATA_ERR_CTR(1)	0	1	2512	1
Bin	DATA_ERR_CTR(1)	1	0	4112	1
Bin	DATA_ERR_CTR(0)	0	1	5598	1
Bin	DATA_ERR_CTR(0)	1	0	7196	1
Bin	ERR_TYPE(2)	0	1	964	1
Bin	ERR_TYPE(2)	1	0	2564	1
Bin	ERR_TYPE(1)	0	1	1234	1
Bin	ERR_TYPE(1)	1	0	2833	1
Bin	ERR_TYPE(0)	0	1	336	1
Bin	ERR_TYPE(0)	1	0	1936	1
Bin	ERR_ERP	0	1	290	1
Bin	ERR_ERP	1	0	1891	1
Bin	ERR_POS(3)	0	1	4188	1
Bin	ERR_POS(3)	1	0	2595	1
Bin	ERR_POS(2)	0	1	4421	1
Bin	ERR_POS(2)	1	0	2821	1
Bin	ERR_POS(1)	0	1	3743	1
Bin	ERR_POS(1)	1	0	2146	1
Bin	ERR_POS(0)	0	1	2941	1
Bin	ERR_POS(0)	1	0	1341	1
Bin	RETR_CTR(3)	0	1	54	1
Bin	RETR_CTR(3)	1	0	1655	1
Bin	RETR_CTR(2)	0	1	140	1
Bin	RETR_CTR(2)	1	0	1741	1
Bin	RETR_CTR(1)	0	1	257	1
Bin	RETR_CTR(1)	1	0	1858	1
Bin	RETR_CTR(0)	0	1	642	1
Bin	RETR_CTR(0)	1	0	2242	1
Bin	ALC_BIT(4)	0	1	68	1
Bin	ALC_BIT(4)	1	0	1667	1
Bin	ALC_BIT(3)	0	1	89	1
Bin	ALC_BIT(3)	1	0	1688	1
Bin	ALC_BIT(2)	0	1	102	1
Bin	ALC_BIT(2)	1	0	1701	1
Bin	ALC_BIT(1)	0	1	170	1
Bin	ALC_BIT(1)	1	0	1769	1
Bin	ALC_BIT(0)	0	1	297	1
Bin	ALC_BIT(0)	1	0	1896	1
Bin	ALC_ID_FIELD(2)	0	1	35	1
Bin	ALC_ID_FIELD(2)	1	0	1636	1
Bin	ALC_ID_FIELD(1)	0	1	41	1
Bin	ALC_ID_FIELD(1)	1	0	1640	1
Bin	ALC_ID_FIELD(0)	0	1	92	1
Bin	ALC_ID_FIELD(0)	1	0	1693	1
Bin	RX_FRAME_CTR(31)	0	1	53	1
Bin	RX_FRAME_CTR(31)	1	0	1652	1
Bin	RX_FRAME_CTR(30)	0	1	56	1
Bin	RX_FRAME_CTR(30)	1	0	1656	1
Bin	RX_FRAME_CTR(29)	0	1	51	1
Bin	RX_FRAME_CTR(29)	1	0	1650	1
Bin	RX_FRAME_CTR(28)	0	1	50	1
Bin	RX_FRAME_CTR(28)	1	0	1648	1
Bin	RX_FRAME_CTR(27)	0	1	53	1
Bin	RX_FRAME_CTR(27)	1	0	1652	1
Bin	RX_FRAME_CTR(26)	0	1	49	1
Bin	RX_FRAME_CTR(26)	1	0	1650	1
Bin	RX_FRAME_CTR(25)	0	1	49	1
Bin	RX_FRAME_CTR(25)	1	0	1647	1
Bin	RX_FRAME_CTR(24)	0	1	57	1
Bin	RX_FRAME_CTR(24)	1	0	1656	1
Bin	RX_FRAME_CTR(23)	0	1	49	1
Bin	RX_FRAME_CTR(23)	1	0	1650	1
Bin	RX_FRAME_CTR(22)	0	1	49	1
Bin	RX_FRAME_CTR(22)	1	0	1650	1
Bin	RX_FRAME_CTR(21)	0	1	54	1
Bin	RX_FRAME_CTR(21)	1	0	1653	1
Bin	RX_FRAME_CTR(20)	0	1	57	1
Bin	RX_FRAME_CTR(20)	1	0	1656	1
Bin	RX_FRAME_CTR(19)	0	1	53	1
Bin	RX_FRAME_CTR(19)	1	0	1651	1
Bin	RX_FRAME_CTR(18)	0	1	53	1
Bin	RX_FRAME_CTR(18)	1	0	1652	1
Bin	RX_FRAME_CTR(17)	0	1	55	1
Bin	RX_FRAME_CTR(17)	1	0	1654	1
Bin	RX_FRAME_CTR(16)	0	1	54	1
Bin	RX_FRAME_CTR(16)	1	0	1653	1
Bin	RX_FRAME_CTR(15)	0	1	54	1
Bin	RX_FRAME_CTR(15)	1	0	1651	1
Bin	RX_FRAME_CTR(14)	0	1	47	1
Bin	RX_FRAME_CTR(14)	1	0	1647	1
Bin	RX_FRAME_CTR(13)	0	1	57	1
Bin	RX_FRAME_CTR(13)	1	0	1656	1
Bin	RX_FRAME_CTR(12)	0	1	61	1
Bin	RX_FRAME_CTR(12)	1	0	1660	1
Bin	RX_FRAME_CTR(11)	0	1	50	1
Bin	RX_FRAME_CTR(11)	1	0	1648	1
Bin	RX_FRAME_CTR(10)	0	1	54	1
Bin	RX_FRAME_CTR(10)	1	0	1652	1
Bin	RX_FRAME_CTR(9)	0	1	53	1
Bin	RX_FRAME_CTR(9)	1	0	1651	1
Bin	RX_FRAME_CTR(8)	0	1	66	1
Bin	RX_FRAME_CTR(8)	1	0	1665	1
Bin	RX_FRAME_CTR(7)	0	1	87	1
Bin	RX_FRAME_CTR(7)	1	0	1686	1
Bin	RX_FRAME_CTR(6)	0	1	113	1
Bin	RX_FRAME_CTR(6)	1	0	1712	1
Bin	RX_FRAME_CTR(5)	0	1	215	1
Bin	RX_FRAME_CTR(5)	1	0	1814	1
Bin	RX_FRAME_CTR(4)	0	1	353	1
Bin	RX_FRAME_CTR(4)	1	0	1953	1
Bin	RX_FRAME_CTR(3)	0	1	747	1
Bin	RX_FRAME_CTR(3)	1	0	2345	1
Bin	RX_FRAME_CTR(2)	0	1	1493	1
Bin	RX_FRAME_CTR(2)	1	0	3092	1
Bin	RX_FRAME_CTR(1)	0	1	2963	1
Bin	RX_FRAME_CTR(1)	1	0	4561	1
Bin	RX_FRAME_CTR(0)	0	1	5921	1
Bin	RX_FRAME_CTR(0)	1	0	7521	1
Bin	TX_FRAME_CTR(31)	0	1	101	1
Bin	TX_FRAME_CTR(31)	1	0	1702	1
Bin	TX_FRAME_CTR(30)	0	1	106	1
Bin	TX_FRAME_CTR(30)	1	0	1707	1
Bin	TX_FRAME_CTR(29)	0	1	110	1
Bin	TX_FRAME_CTR(29)	1	0	1711	1
Bin	TX_FRAME_CTR(28)	0	1	98	1
Bin	TX_FRAME_CTR(28)	1	0	1699	1
Bin	TX_FRAME_CTR(27)	0	1	105	1
Bin	TX_FRAME_CTR(27)	1	0	1706	1
Bin	TX_FRAME_CTR(26)	0	1	101	1
Bin	TX_FRAME_CTR(26)	1	0	1702	1
Bin	TX_FRAME_CTR(25)	0	1	99	1
Bin	TX_FRAME_CTR(25)	1	0	1700	1
Bin	TX_FRAME_CTR(24)	0	1	97	1
Bin	TX_FRAME_CTR(24)	1	0	1698	1
Bin	TX_FRAME_CTR(23)	0	1	102	1
Bin	TX_FRAME_CTR(23)	1	0	1703	1
Bin	TX_FRAME_CTR(22)	0	1	100	1
Bin	TX_FRAME_CTR(22)	1	0	1701	1
Bin	TX_FRAME_CTR(21)	0	1	105	1
Bin	TX_FRAME_CTR(21)	1	0	1706	1
Bin	TX_FRAME_CTR(20)	0	1	108	1
Bin	TX_FRAME_CTR(20)	1	0	1709	1
Bin	TX_FRAME_CTR(19)	0	1	97	1
Bin	TX_FRAME_CTR(19)	1	0	1698	1
Bin	TX_FRAME_CTR(18)	0	1	98	1
Bin	TX_FRAME_CTR(18)	1	0	1699	1
Bin	TX_FRAME_CTR(17)	0	1	105	1
Bin	TX_FRAME_CTR(17)	1	0	1706	1
Bin	TX_FRAME_CTR(16)	0	1	111	1
Bin	TX_FRAME_CTR(16)	1	0	1712	1
Bin	TX_FRAME_CTR(15)	0	1	102	1
Bin	TX_FRAME_CTR(15)	1	0	1703	1
Bin	TX_FRAME_CTR(14)	0	1	105	1
Bin	TX_FRAME_CTR(14)	1	0	1706	1
Bin	TX_FRAME_CTR(13)	0	1	91	1
Bin	TX_FRAME_CTR(13)	1	0	1692	1
Bin	TX_FRAME_CTR(12)	0	1	99	1
Bin	TX_FRAME_CTR(12)	1	0	1700	1
Bin	TX_FRAME_CTR(11)	0	1	98	1
Bin	TX_FRAME_CTR(11)	1	0	1699	1
Bin	TX_FRAME_CTR(10)	0	1	96	1
Bin	TX_FRAME_CTR(10)	1	0	1697	1
Bin	TX_FRAME_CTR(9)	0	1	106	1
Bin	TX_FRAME_CTR(9)	1	0	1707	1
Bin	TX_FRAME_CTR(8)	0	1	104	1
Bin	TX_FRAME_CTR(8)	1	0	1705	1
Bin	TX_FRAME_CTR(7)	0	1	103	1
Bin	TX_FRAME_CTR(7)	1	0	1704	1
Bin	TX_FRAME_CTR(6)	0	1	108	1
Bin	TX_FRAME_CTR(6)	1	0	1709	1
Bin	TX_FRAME_CTR(5)	0	1	109	1
Bin	TX_FRAME_CTR(5)	1	0	1710	1
Bin	TX_FRAME_CTR(4)	0	1	152	1
Bin	TX_FRAME_CTR(4)	1	0	1753	1
Bin	TX_FRAME_CTR(3)	0	1	258	1
Bin	TX_FRAME_CTR(3)	1	0	1859	1
Bin	TX_FRAME_CTR(2)	0	1	619	1
Bin	TX_FRAME_CTR(2)	1	0	2220	1
Bin	TX_FRAME_CTR(1)	0	1	1052	1
Bin	TX_FRAME_CTR(1)	1	0	2653	1
Bin	TX_FRAME_CTR(0)	0	1	2203	1
Bin	TX_FRAME_CTR(0)	1	0	3804	1
Bin	BST_CTR(2)	0	1	33452	1
Bin	BST_CTR(2)	1	0	35053	1
Bin	BST_CTR(1)	0	1	70940	1
Bin	BST_CTR(1)	1	0	72538	1
Bin	BST_CTR(0)	0	1	141315	1
Bin	BST_CTR(0)	1	0	142914	1
Bin	DST_CTR(2)	0	1	117682	1
Bin	DST_CTR(2)	1	0	119283	1
Bin	DST_CTR(1)	0	1	242662	1
Bin	DST_CTR(1)	1	0	244257	1
Bin	DST_CTR(0)	0	1	484884	1
Bin	DST_CTR(0)	1	0	486480	1
Bin	STATUS_EWL	0	1	778	1
Bin	STATUS_EWL	1	0	2378	1

Port:

PC_DBG

	Element	From	To	Count	Threshold
Bin	IS_SOF	0	1	24924	1
Bin	IS_SOF	1	0	26525	1
Bin	IS_ARBITRATION	0	1	55723	1
Bin	IS_ARBITRATION	1	0	57324	1
Bin	IS_CONTROL	0	1	50970	1
Bin	IS_CONTROL	1	0	52571	1
Bin	IS_DATA	0	1	36820	1
Bin	IS_DATA	1	0	38421	1
Bin	IS_STUFF_COUNT	0	1	13502	1
Bin	IS_STUFF_COUNT	1	0	15103	1
Bin	IS_CRC	0	1	31213	1
Bin	IS_CRC	1	0	32814	1
Bin	IS_CRC_DELIM	0	1	29735	1
Bin	IS_CRC_DELIM	1	0	31336	1
Bin	IS_ACK	0	1	29588	1
Bin	IS_ACK	1	0	31189	1
Bin	IS_ACK_DELIM	0	1	28165	1
Bin	IS_ACK_DELIM	1	0	29766	1
Bin	IS_EOF	0	1	27273	1
Bin	IS_EOF	1	0	28874	1
Bin	IS_OVERLOAD	0	1	529	1
Bin	IS_OVERLOAD	1	0	2130	1
Bin	IS_ERR	0	1	27135	1
Bin	IS_ERR	1	0	28729	1
Bin	IS_INTERMISSION	0	1	51716	1
Bin	IS_INTERMISSION	1	0	53316	1
Bin	IS_SUSPEND	0	1	2779	1
Bin	IS_SUSPEND	1	0	4380	1

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold
Bin	(31)	0	1	69559	1
Bin	(31)	1	0	1039240	1
Bin	(30)	0	1	73293	1
Bin	(30)	1	0	1035506	1
Bin	(29)	0	1	73366	1
Bin	(29)	1	0	1035433	1
Bin	(28)	0	1	99117	1
Bin	(28)	1	0	1009682	1
Bin	(27)	0	1	90358	1
Bin	(27)	1	0	1018441	1
Bin	(26)	0	1	88295	1
Bin	(26)	1	0	1020504	1
Bin	(25)	0	1	93286	1
Bin	(25)	1	0	1015513	1
Bin	(24)	0	1	86136	1
Bin	(24)	1	0	1022663	1
Bin	(23)	0	1	78398	1
Bin	(23)	1	0	1030401	1
Bin	(22)	0	1	112701	1
Bin	(22)	1	0	996098	1
Bin	(21)	0	1	78143	1
Bin	(21)	1	0	1030656	1
Bin	(20)	0	1	87507	1
Bin	(20)	1	0	1021292	1
Bin	(19)	0	1	117342	1
Bin	(19)	1	0	991457	1
Bin	(18)	0	1	134409	1
Bin	(18)	1	0	974390	1
Bin	(17)	0	1	128234	1
Bin	(17)	1	0	980565	1
Bin	(16)	0	1	198469	1
Bin	(16)	1	0	910330	1
Bin	(15)	0	1	78983	1
Bin	(15)	1	0	1029816	1
Bin	(14)	0	1	94254	1
Bin	(14)	1	0	1014545	1
Bin	(13)	0	1	83324	1
Bin	(13)	1	0	1025475	1
Bin	(12)	0	1	86320	1
Bin	(12)	1	0	1022479	1
Bin	(11)	0	1	105643	1
Bin	(11)	1	0	1003156	1
Bin	(10)	0	1	127120	1
Bin	(10)	1	0	981679	1
Bin	(9)	0	1	181819	1
Bin	(9)	1	0	926980	1
Bin	(8)	0	1	157890	1
Bin	(8)	1	0	950909	1
Bin	(7)	0	1	133793	1
Bin	(7)	1	0	975006	1
Bin	(6)	0	1	115658	1
Bin	(6)	1	0	993141	1
Bin	(5)	0	1	109105	1
Bin	(5)	1	0	999694	1
Bin	(4)	0	1	169955	1
Bin	(4)	1	0	938844	1
Bin	(3)	0	1	147742	1
Bin	(3)	1	0	961057	1
Bin	(2)	0	1	172490	1
Bin	(2)	1	0	936309	1
Bin	(1)	0	1	244111	1
Bin	(1)	1	0	864688	1
Bin	(0)	0	1	204311	1
Bin	(0)	1	0	904488	1

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold
Bin	(4)	0	1	328666	1
Bin	(4)	1	0	27198447	1
Bin	(3)	0	1	588207	1
Bin	(3)	1	0	26938906	1
Bin	(2)	0	1	445850	1
Bin	(2)	1	0	27081263	1
Bin	(1)	0	1	26740027	1
Bin	(1)	1	0	787086	1
Bin	(0)	0	1	17592114	1
Bin	(0)	1	0	9934999	1

Port:

TXTB_PORT_A_CS

	Element	From	To	Count	Threshold
Bin	(7)	0	1	11139	1
Bin	(7)	1	0	185020	1
Bin	(6)	0	1	11345	1
Bin	(6)	1	0	184814	1
Bin	(5)	0	1	11686	1
Bin	(5)	1	0	184473	1
Bin	(4)	0	1	11397	1
Bin	(4)	1	0	184762	1
Bin	(3)	0	1	45314	1
Bin	(3)	1	0	469970	1
Bin	(2)	0	1	45635	1
Bin	(2)	1	0	469649	1
Bin	(1)	0	1	128057	1
Bin	(1)	1	0	727220	1
Bin	(0)	0	1	162265	1
Bin	(0)	1	0	693012	1

Port:

TXTB_PORT_A_BE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	27488021	1
Bin	(3)	1	0	37491	1
Bin	(2)	0	1	27488403	1
Bin	(2)	1	0	37109	1
Bin	(1)	0	1	27389228	1
Bin	(1)	1	0	136284	1
Bin	(0)	0	1	27390472	1
Bin	(0)	1	0	135040	1

Port:

MR_TX_PRIORITY

	Element	From	To	Count	Threshold
Bin	(7)(2)	0	1	136	1
Bin	(7)(2)	1	0	403	1
Bin	(7)(1)	0	1	138	1
Bin	(7)(1)	1	0	431	1
Bin	(7)(0)	0	1	126	1
Bin	(7)(0)	1	0	402	1
Bin	(6)(2)	0	1	122	1
Bin	(6)(2)	1	0	351	1
Bin	(6)(1)	0	1	136	1
Bin	(6)(1)	1	0	346	1
Bin	(6)(0)	0	1	129	1
Bin	(6)(0)	1	0	373	1
Bin	(5)(2)	0	1	115	1
Bin	(5)(2)	1	0	373	1
Bin	(5)(1)	0	1	161	1
Bin	(5)(1)	1	0	383	1
Bin	(5)(0)	0	1	144	1
Bin	(5)(0)	1	0	414	1
Bin	(4)(2)	0	1	119	1
Bin	(4)(2)	1	0	319	1
Bin	(4)(1)	0	1	129	1
Bin	(4)(1)	1	0	343	1
Bin	(4)(0)	0	1	152	1
Bin	(4)(0)	1	0	326	1
Bin	(3)(2)	0	1	261	1
Bin	(3)(2)	1	0	1104	1
Bin	(3)(1)	0	1	292	1
Bin	(3)(1)	1	0	1167	1
Bin	(3)(0)	0	1	354	1
Bin	(3)(0)	1	0	1173	1
Bin	(2)(2)	0	1	259	1
Bin	(2)(2)	1	0	1003	1
Bin	(2)(1)	0	1	348	1
Bin	(2)(1)	1	0	1136	1
Bin	(2)(0)	0	1	394	1
Bin	(2)(0)	1	0	1061	1
Bin	(1)(2)	0	1	332	1
Bin	(1)(2)	1	0	1912	1
Bin	(1)(1)	0	1	469	1
Bin	(1)(1)	1	0	2069	1
Bin	(1)(0)	0	1	428	1
Bin	(1)(0)	1	0	1961	1
Bin	(0)(2)	0	1	446	1
Bin	(0)(2)	1	0	1942	1
Bin	(0)(1)	0	1	419	1
Bin	(0)(1)	1	0	2037	1
Bin	(0)(0)	0	1	2056	1
Bin	(0)(0)	1	0	464	1

Port:

MR_TX_COMMAND_TXBI

	Element	From	To	Count	Threshold
Bin	(7)	0	1	76	1
Bin	(7)	1	0	1130	1
Bin	(6)	0	1	79	1
Bin	(6)	1	0	1127	1
Bin	(5)	0	1	75	1
Bin	(5)	1	0	1131	1
Bin	(4)	0	1	83	1
Bin	(4)	1	0	1123	1
Bin	(3)	0	1	392	1
Bin	(3)	1	0	4053	1
Bin	(2)	0	1	330	1
Bin	(2)	1	0	4115	1
Bin	(1)	0	1	5642	1
Bin	(1)	1	0	10511	1
Bin	(0)	0	1	6553	1
Bin	(0)	1	0	9600	1

Signal:

MR_CTRL_OUT_I

	Element	From	To	Count	Threshold
Bin	MODE_RST	0	1	868	1
Bin	MODE_RST	1	0	32879	1
Bin	MODE_BMM	0	1	15	1
Bin	MODE_BMM	1	0	1616	1
Bin	MODE_STM	0	1	160	1
Bin	MODE_STM	1	0	1761	1
Bin	MODE_AFM	0	1	68	1
Bin	MODE_AFM	1	0	1669	1
Bin	MODE_FDE	0	1	1801	1
Bin	MODE_FDE	1	0	200	1
Bin	MODE_TTTM	0	1	55	1
Bin	MODE_TTTM	1	0	1656	1
Bin	MODE_ROM	0	1	51	1
Bin	MODE_ROM	1	0	1652	1
Bin	MODE_ACF	0	1	19	1
Bin	MODE_ACF	1	0	1620	1
Bin	MODE_TSTM	0	1	1027	1
Bin	MODE_TSTM	1	0	2627	1
Bin	MODE_RXBAM	0	1	1731	1
Bin	MODE_RXBAM	1	0	130	1
Bin	MODE_TXBBM	0	1	33	1
Bin	MODE_TXBBM	1	0	1634	1
Bin	MODE_SAM	0	1	55	1
Bin	MODE_SAM	1	0	1656	1
Bin	MODE_ERFM	0	1	153	1
Bin	MODE_ERFM	1	0	1754	1
Bin	SETTINGS_RTRLE	0	1	2454	1
Bin	SETTINGS_RTRLE	1	0	4054	1
Bin	SETTINGS_RTRTH(3)	0	1	22	1
Bin	SETTINGS_RTRTH(3)	1	0	1623	1
Bin	SETTINGS_RTRTH(2)	0	1	54	1
Bin	SETTINGS_RTRTH(2)	1	0	1655	1
Bin	SETTINGS_RTRTH(1)	0	1	22	1
Bin	SETTINGS_RTRTH(1)	1	0	1623	1
Bin	SETTINGS_RTRTH(0)	0	1	59	1
Bin	SETTINGS_RTRTH(0)	1	0	1660	1
Bin	SETTINGS_ILBP	0	1	130	1
Bin	SETTINGS_ILBP	1	0	1731	1
Bin	SETTINGS_ENA	0	1	6483	1
Bin	SETTINGS_ENA	1	0	8072	1
Bin	SETTINGS_NISOFD	0	1	130	1
Bin	SETTINGS_NISOFD	1	0	1731	1
Bin	SETTINGS_PEX	0	1	72	1
Bin	SETTINGS_PEX	1	0	1673	1
Bin	SETTINGS_TBFBO	0	1	2534	1
Bin	SETTINGS_TBFBO	1	0	944	1
Bin	SETTINGS_FDRF	0	1	4	1
Bin	SETTINGS_FDRF	1	0	1605	1
Bin	SETTINGS_PCHKE	0	1	112	1
Bin	SETTINGS_PCHKE	1	0	1713	1
Bin	COMMAND_RXRPMV	0	1	25	1
Bin	COMMAND_RXRPMV	1	0	3068	1
Bin	COMMAND_RRB	0	1	460	1
Bin	COMMAND_RRB	1	0	3068	1
Bin	COMMAND_CDO	0	1	20	1
Bin	COMMAND_CDO	1	0	3068	1
Bin	COMMAND_ERCRST	0	1	170	1
Bin	COMMAND_ERCRST	1	0	3068	1
Bin	COMMAND_RXFCRST	0	1	124	1
Bin	COMMAND_RXFCRST	1	0	3068	1
Bin	COMMAND_TXFCRST	0	1	124	1
Bin	COMMAND_TXFCRST	1	0	3068	1
Bin	COMMAND_CPEXS	0	1	60	1
Bin	COMMAND_CPEXS	1	0	3068	1
Bin	COMMAND_CRXPE	0	1	40	1
Bin	COMMAND_CRXPE	1	0	3068	1
Bin	COMMAND_CTXPE	0	1	440	1
Bin	COMMAND_CTXPE	1	0	3068	1
Bin	COMMAND_CTXDPE	0	1	40	1
Bin	COMMAND_CTXDPE	1	0	3068	1
Bin	INT_STAT_RXI	0	1	40	1
Bin	INT_STAT_RXI	1	0	1748	1
Bin	INT_STAT_TXI	0	1	42	1
Bin	INT_STAT_TXI	1	0	1748	1
Bin	INT_STAT_EWLI	0	1	30	1
Bin	INT_STAT_EWLI	1	0	1748	1
Bin	INT_STAT_DOI	0	1	16	1
Bin	INT_STAT_DOI	1	0	1748	1
Bin	INT_STAT_FCSI	0	1	80	1
Bin	INT_STAT_FCSI	1	0	1748	1
Bin	INT_STAT_ALI	0	1	5	1
Bin	INT_STAT_ALI	1	0	1748	1
Bin	INT_STAT_BEI	0	1	15	1
Bin	INT_STAT_BEI	1	0	1748	1
Bin	INT_STAT_OFI	0	1	5	1
Bin	INT_STAT_OFI	1	0	1748	1
Bin	INT_STAT_RXFI	0	1	15	1
Bin	INT_STAT_RXFI	1	0	1748	1
Bin	INT_STAT_BSI	0	1	34	1
Bin	INT_STAT_BSI	1	0	1748	1
Bin	INT_STAT_RBNEI	0	1	50	1
Bin	INT_STAT_RBNEI	1	0	1748	1
Bin	INT_STAT_TXBHCI	0	1	52	1
Bin	INT_STAT_TXBHCI	1	0	1748	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	0	1	66	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	0	1	30	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	0	1	50	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	0	1	476	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	0	1	512	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	0	1	492	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	1	0	2143	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	0	1	66	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	0	1	40	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	0	1	50	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	0	1	15	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	0	1	409	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	0	1	435	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	0	1	425	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	0	1	460	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	1	0	2076	1
Bin	BTR_PROP(6)	0	1	200	1
Bin	BTR_PROP(6)	1	0	1799	1
Bin	BTR_PROP(5)	0	1	309	1
Bin	BTR_PROP(5)	1	0	1907	1
Bin	BTR_PROP(4)	0	1	225	1
Bin	BTR_PROP(4)	1	0	1823	1
Bin	BTR_PROP(3)	0	1	273	1
Bin	BTR_PROP(3)	1	0	1871	1
Bin	BTR_PROP(2)	0	1	3822	1
Bin	BTR_PROP(2)	1	0	2222	1
Bin	BTR_PROP(1)	0	1	262	1
Bin	BTR_PROP(1)	1	0	1860	1
Bin	BTR_PROP(0)	0	1	1793	1
Bin	BTR_PROP(0)	1	0	193	1
Bin	BTR_PH1(5)	0	1	318	1
Bin	BTR_PH1(5)	1	0	1917	1
Bin	BTR_PH1(4)	0	1	254	1
Bin	BTR_PH1(4)	1	0	1853	1
Bin	BTR_PH1(3)	0	1	263	1
Bin	BTR_PH1(3)	1	0	1862	1
Bin	BTR_PH1(2)	0	1	1306	1
Bin	BTR_PH1(2)	1	0	2897	1
Bin	BTR_PH1(1)	0	1	1924	1
Bin	BTR_PH1(1)	1	0	324	1
Bin	BTR_PH1(0)	0	1	2090	1
Bin	BTR_PH1(0)	1	0	491	1
Bin	BTR_PH2(5)	0	1	204	1
Bin	BTR_PH2(5)	1	0	1803	1
Bin	BTR_PH2(4)	0	1	349	1
Bin	BTR_PH2(4)	1	0	1947	1
Bin	BTR_PH2(3)	0	1	313	1
Bin	BTR_PH2(3)	1	0	1912	1
Bin	BTR_PH2(2)	0	1	3874	1
Bin	BTR_PH2(2)	1	0	2275	1
Bin	BTR_PH2(1)	0	1	3412	1
Bin	BTR_PH2(1)	1	0	5003	1
Bin	BTR_PH2(0)	0	1	2160	1
Bin	BTR_PH2(0)	1	0	559	1
Bin	BTR_BRP(7)	0	1	13	1
Bin	BTR_BRP(7)	1	0	1614	1
Bin	BTR_BRP(6)	0	1	14	1
Bin	BTR_BRP(6)	1	0	1615	1
Bin	BTR_BRP(5)	0	1	12	1
Bin	BTR_BRP(5)	1	0	1613	1
Bin	BTR_BRP(4)	0	1	16	1
Bin	BTR_BRP(4)	1	0	1617	1
Bin	BTR_BRP(3)	0	1	4831	1
Bin	BTR_BRP(3)	1	0	3242	1
Bin	BTR_BRP(2)	0	1	930	1
Bin	BTR_BRP(2)	1	0	2524	1
Bin	BTR_BRP(1)	0	1	4762	1
Bin	BTR_BRP(1)	1	0	3170	1
Bin	BTR_BRP(0)	0	1	2317	1
Bin	BTR_BRP(0)	1	0	3915	1
Bin	BTR_SJW(4)	0	1	204	1
Bin	BTR_SJW(4)	1	0	1802	1
Bin	BTR_SJW(3)	0	1	271	1
Bin	BTR_SJW(3)	1	0	1869	1
Bin	BTR_SJW(2)	0	1	971	1
Bin	BTR_SJW(2)	1	0	2568	1
Bin	BTR_SJW(1)	0	1	2624	1
Bin	BTR_SJW(1)	1	0	1032	1
Bin	BTR_SJW(0)	0	1	3116	1
Bin	BTR_SJW(0)	1	0	4713	1
Bin	BTR_FD_PROP_FD(5)	0	1	239	1
Bin	BTR_FD_PROP_FD(5)	1	0	1837	1
Bin	BTR_FD_PROP_FD(4)	0	1	292	1
Bin	BTR_FD_PROP_FD(4)	1	0	1890	1
Bin	BTR_FD_PROP_FD(3)	0	1	278	1
Bin	BTR_FD_PROP_FD(3)	1	0	1876	1
Bin	BTR_FD_PROP_FD(2)	0	1	1184	1
Bin	BTR_FD_PROP_FD(2)	1	0	2773	1
Bin	BTR_FD_PROP_FD(1)	0	1	4706	1
Bin	BTR_FD_PROP_FD(1)	1	0	3114	1
Bin	BTR_FD_PROP_FD(0)	0	1	3888	1
Bin	BTR_FD_PROP_FD(0)	1	0	2287	1
Bin	BTR_FD_PH1_FD(4)	0	1	245	1
Bin	BTR_FD_PH1_FD(4)	1	0	1844	1
Bin	BTR_FD_PH1_FD(3)	0	1	293	1
Bin	BTR_FD_PH1_FD(3)	1	0	1892	1
Bin	BTR_FD_PH1_FD(2)	0	1	1175	1
Bin	BTR_FD_PH1_FD(2)	1	0	2765	1
Bin	BTR_FD_PH1_FD(1)	0	1	1695	1
Bin	BTR_FD_PH1_FD(1)	1	0	95	1
Bin	BTR_FD_PH1_FD(0)	0	1	3844	1
Bin	BTR_FD_PH1_FD(0)	1	0	2244	1
Bin	BTR_FD_PH2_FD(4)	0	1	288	1
Bin	BTR_FD_PH2_FD(4)	1	0	1887	1
Bin	BTR_FD_PH2_FD(3)	0	1	315	1
Bin	BTR_FD_PH2_FD(3)	1	0	1914	1
Bin	BTR_FD_PH2_FD(2)	0	1	1212	1
Bin	BTR_FD_PH2_FD(2)	1	0	2802	1
Bin	BTR_FD_PH2_FD(1)	0	1	1734	1
Bin	BTR_FD_PH2_FD(1)	1	0	134	1
Bin	BTR_FD_PH2_FD(0)	0	1	3870	1
Bin	BTR_FD_PH2_FD(0)	1	0	2269	1
Bin	BTR_FD_BRP_FD(7)	0	1	18	1
Bin	BTR_FD_BRP_FD(7)	1	0	1619	1
Bin	BTR_FD_BRP_FD(6)	0	1	29	1
Bin	BTR_FD_BRP_FD(6)	1	0	1630	1
Bin	BTR_FD_BRP_FD(5)	0	1	17	1
Bin	BTR_FD_BRP_FD(5)	1	0	1618	1
Bin	BTR_FD_BRP_FD(4)	0	1	30	1
Bin	BTR_FD_BRP_FD(4)	1	0	1631	1
Bin	BTR_FD_BRP_FD(3)	0	1	27	1
Bin	BTR_FD_BRP_FD(3)	1	0	1628	1
Bin	BTR_FD_BRP_FD(2)	0	1	4843	1
Bin	BTR_FD_BRP_FD(2)	1	0	3254	1
Bin	BTR_FD_BRP_FD(1)	0	1	757	1
Bin	BTR_FD_BRP_FD(1)	1	0	2355	1
Bin	BTR_FD_BRP_FD(0)	0	1	2600	1
Bin	BTR_FD_BRP_FD(0)	1	0	4192	1
Bin	BTR_FD_SJW_FD(4)	0	1	247	1
Bin	BTR_FD_SJW_FD(4)	1	0	1845	1
Bin	BTR_FD_SJW_FD(3)	0	1	289	1
Bin	BTR_FD_SJW_FD(3)	1	0	1887	1
Bin	BTR_FD_SJW_FD(2)	0	1	916	1
Bin	BTR_FD_SJW_FD(2)	1	0	2513	1
Bin	BTR_FD_SJW_FD(1)	0	1	2568	1
Bin	BTR_FD_SJW_FD(1)	1	0	976	1
Bin	BTR_FD_SJW_FD(0)	0	1	953	1
Bin	BTR_FD_SJW_FD(0)	1	0	2550	1
Bin	EWL_EW_LIMIT(7)	0	1	78	1
Bin	EWL_EW_LIMIT(7)	1	0	1679	1
Bin	EWL_EW_LIMIT(6)	0	1	1686	1
Bin	EWL_EW_LIMIT(6)	1	0	85	1
Bin	EWL_EW_LIMIT(5)	0	1	1672	1
Bin	EWL_EW_LIMIT(5)	1	0	71	1
Bin	EWL_EW_LIMIT(4)	0	1	72	1
Bin	EWL_EW_LIMIT(4)	1	0	1673	1
Bin	EWL_EW_LIMIT(3)	0	1	75	1
Bin	EWL_EW_LIMIT(3)	1	0	1676	1
Bin	EWL_EW_LIMIT(2)	0	1	85	1
Bin	EWL_EW_LIMIT(2)	1	0	1686	1
Bin	EWL_EW_LIMIT(1)	0	1	88	1
Bin	EWL_EW_LIMIT(1)	1	0	1689	1
Bin	EWL_EW_LIMIT(0)	0	1	81	1
Bin	EWL_EW_LIMIT(0)	1	0	1682	1
Bin	ERP_ERP_LIMIT(7)	0	1	1732	1
Bin	ERP_ERP_LIMIT(7)	1	0	131	1
Bin	ERP_ERP_LIMIT(6)	0	1	25	1
Bin	ERP_ERP_LIMIT(6)	1	0	1626	1
Bin	ERP_ERP_LIMIT(5)	0	1	21	1
Bin	ERP_ERP_LIMIT(5)	1	0	1622	1
Bin	ERP_ERP_LIMIT(4)	0	1	26	1
Bin	ERP_ERP_LIMIT(4)	1	0	1627	1
Bin	ERP_ERP_LIMIT(3)	0	1	21	1
Bin	ERP_ERP_LIMIT(3)	1	0	1622	1
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Bin	ERP_ERP_LIMIT(2)	1	0	1627	1
Bin	ERP_ERP_LIMIT(1)	0	1	28	1
Bin	ERP_ERP_LIMIT(1)	1	0	1629	1
Bin	ERP_ERP_LIMIT(0)	0	1	30	1
Bin	ERP_ERP_LIMIT(0)	1	0	1631	1
Bin	CTR_PRES_CTPV(8)	0	1	253	1
Bin	CTR_PRES_CTPV(8)	1	0	1854	1
Bin	CTR_PRES_CTPV(7)	0	1	2608	1
Bin	CTR_PRES_CTPV(7)	1	0	4209	1
Bin	CTR_PRES_CTPV(6)	0	1	733	1
Bin	CTR_PRES_CTPV(6)	1	0	2334	1
Bin	CTR_PRES_CTPV(5)	0	1	2611	1
Bin	CTR_PRES_CTPV(5)	1	0	4212	1
Bin	CTR_PRES_CTPV(4)	0	1	2773	1
Bin	CTR_PRES_CTPV(4)	1	0	4374	1
Bin	CTR_PRES_CTPV(3)	0	1	893	1
Bin	CTR_PRES_CTPV(3)	1	0	2494	1
Bin	CTR_PRES_CTPV(2)	0	1	2887	1
Bin	CTR_PRES_CTPV(2)	1	0	4488	1
Bin	CTR_PRES_CTPV(1)	0	1	1015	1
Bin	CTR_PRES_CTPV(1)	1	0	2616	1
Bin	CTR_PRES_CTPV(0)	0	1	804	1
Bin	CTR_PRES_CTPV(0)	1	0	2405	1
Bin	CTR_PRES_PTX	0	1	19125	1
Bin	CTR_PRES_PTX	1	0	44590	1
Bin	CTR_PRES_PRX	0	1	19522	1
Bin	CTR_PRES_PRX	1	0	44590	1
Bin	CTR_PRES_ENORM	0	1	6369	1
Bin	CTR_PRES_ENORM	1	0	44590	1
Bin	CTR_PRES_EFD	0	1	6369	1
Bin	CTR_PRES_EFD	1	0	44590	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	0	1	389	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	1	0	1990	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	0	1	349	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	1	0	1950	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	0	1	339	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	1	0	1940	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	0	1	365	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	1	0	1966	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	0	1	366	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	1	0	1967	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	0	1	378	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	1	0	1979	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	0	1	395	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	1	0	1996	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	0	1	366	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	1	0	1967	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	0	1	383	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	1	0	1984	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	0	1	368	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	1	0	1969	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	0	1	411	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	1	0	2012	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	0	1	97	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	1	0	1698	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	0	1	82	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	1	0	1683	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	0	1	94	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	1	0	1695	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	0	1	106	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	1	0	1707	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	0	1	118	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	1	0	1719	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	0	1	131	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	1	0	1732	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	0	1	106	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	1	0	1707	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	0	1	249	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	1	0	1850	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	0	1	250	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	1	0	1851	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	0	1	252	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	1	0	1853	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	0	1	281	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	1	0	1882	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	0	1	265	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	1	0	1866	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	0	1	278	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	1	0	1879	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	0	1	239	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	1	0	1840	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	0	1	267	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	1	0	1868	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	0	1	280	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	1	0	1881	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	0	1	242	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	1	0	1843	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	0	1	270	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	1	0	1871	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	0	1	816	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	1	0	2417	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	0	1	793	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	1	0	2394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	0	1	803	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	1	0	2404	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	0	1	791	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	1	0	2392	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	0	1	805	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	1	0	2406	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	0	1	764	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	1	0	2365	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	0	1	832	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	1	0	2433	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	0	1	772	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	1	0	2373	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	0	1	763	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	1	0	2364	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	0	1	832	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	1	0	2433	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	0	1	836	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	1	0	2437	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	0	1	395	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	1	0	1996	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	0	1	429	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	1	0	2030	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	0	1	403	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	1	0	2004	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	0	1	415	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	1	0	2016	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	0	1	415	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	1	0	2016	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	0	1	413	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	1	0	2014	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	0	1	397	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	1	0	1998	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	0	1	398	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	1	0	1999	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	0	1	402	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	1	0	2003	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	0	1	394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	1	0	1995	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	0	1	421	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	1	0	2022	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	0	1	396	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	1	0	1997	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	0	1	423	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	1	0	2024	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	0	1	378	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	1	0	1979	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	0	1	410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	1	0	2011	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	0	1	91	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	1	0	1692	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	0	1	80	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	1	0	1681	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	0	1	102	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	1	0	1703	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	0	1	91	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	1	0	1692	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	0	1	82	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	1	0	1683	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	0	1	105	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	1	0	1706	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	0	1	89	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	1	0	1690	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	0	1	22	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	1	0	1623	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	0	1	15	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	1	0	1616	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	0	1	33	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	1	0	1634	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	0	1	22	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	1	0	1623	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	0	1	36	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	1	0	1637	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	0	1	35	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	1	0	1636	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	0	1	34	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	1	0	1635	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	0	1	63	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	1	0	1664	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	0	1	66	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	1	0	1667	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	1	0	1672	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	1	0	1672	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	0	1	65	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	1	0	1666	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	0	1	68	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	1	0	1669	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	0	1	67	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	1	0	1668	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	0	1	59	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	1	0	1660	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	0	1	186	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	1	0	1787	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	0	1	191	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	1	0	1792	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	0	1	195	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	1	0	1796	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	0	1	200	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	1	0	1801	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	0	1	198	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	1	0	1799	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	0	1	204	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	1	0	1805	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	0	1	206	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	1	0	1807	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	0	1	198	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	1	0	1799	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	0	1	202	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	1	0	1803	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	0	1	213	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	1	0	1814	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	0	1	212	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	1	0	1813	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	0	1	100	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	1	0	1701	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	1	0	1707	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	0	1	92	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	1	0	1693	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	0	1	111	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	1	0	1712	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	1	0	1702	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	0	1	91	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	1	0	1692	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	0	1	103	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	1	0	1704	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	1	0	1702	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	0	1	97	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	1	0	1698	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	0	1	104	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	1	0	1705	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	0	1	95	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	1	0	1696	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	0	1	102	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	1	0	1703	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	1	0	1707	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	0	1	100	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	1	0	1701	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	0	1	107	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	1	0	1708	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	0	1	94	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	1	0	1695	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	0	1	94	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	1	0	1695	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	0	1	100	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	1	0	1701	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	0	1	86	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	1	0	1687	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	0	1	100	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	1	0	1701	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	0	1	104	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	1	0	1705	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	0	1	93	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	1	0	1694	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	0	1	98	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	1	0	1699	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	0	1	88	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	1	0	1689	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	0	1	97	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	1	0	1698	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	0	1	79	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	1	0	1680	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	0	1	87	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	1	0	1688	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	0	1	22	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	1	0	1623	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	0	1	17	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	1	0	1618	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	0	1	30	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	1	0	1631	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	0	1	21	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	1	0	1622	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	0	1	37	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	1	0	1638	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	1	0	1635	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	1	0	1635	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	1	0	1667	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	0	1	71	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	1	0	1672	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	0	1	63	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	1	0	1664	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	0	1	69	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	1	0	1670	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	1	0	1663	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	0	1	71	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	1	0	1672	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	0	1	69	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	1	0	1670	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	1	0	1663	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	1	0	1668	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	1	0	1667	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	0	1	58	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	1	0	1659	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	0	1	184	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	1	0	1785	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	0	1	182	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	1	0	1783	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	0	1	199	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	1	0	1800	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	0	1	193	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	1	0	1794	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	0	1	190	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	1	0	1791	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	0	1	207	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	1	0	1808	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	0	1	213	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	1	0	1814	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	1	0	1799	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	1	0	1799	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	0	1	203	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	1	0	1804	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	0	1	214	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	1	0	1815	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	1	0	1701	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	0	1	103	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	1	0	1704	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	1	0	1701	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	0	1	99	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	1	0	1700	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	0	1	105	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	1	0	1706	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	0	1	86	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	1	0	1687	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	1	0	1699	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	0	1	104	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	1	0	1705	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	0	1	102	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	1	0	1703	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	0	1	95	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	1	0	1696	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	0	1	96	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	1	0	1697	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	0	1	105	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	1	0	1706	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	0	1	110	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	1	0	1711	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	1	0	1699	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	0	1	95	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	1	0	1696	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	1	0	1602	1
Bin	FILTER_CONTROL_FANB	0	1	2052	1
Bin	FILTER_CONTROL_FANB	1	0	451	1
Bin	FILTER_CONTROL_FANE	0	1	2029	1
Bin	FILTER_CONTROL_FANE	1	0	428	1
Bin	FILTER_CONTROL_FAFB	0	1	2060	1
Bin	FILTER_CONTROL_FAFB	1	0	459	1
Bin	FILTER_CONTROL_FAFE	0	1	2029	1
Bin	FILTER_CONTROL_FAFE	1	0	428	1
Bin	FILTER_CONTROL_FBNB	0	1	106	1
Bin	FILTER_CONTROL_FBNB	1	0	1707	1
Bin	FILTER_CONTROL_FBNE	0	1	105	1
Bin	FILTER_CONTROL_FBNE	1	0	1706	1
Bin	FILTER_CONTROL_FBFB	0	1	107	1
Bin	FILTER_CONTROL_FBFB	1	0	1708	1
Bin	FILTER_CONTROL_FBFE	0	1	105	1
Bin	FILTER_CONTROL_FBFE	1	0	1706	1
Bin	FILTER_CONTROL_FCNB	0	1	106	1
Bin	FILTER_CONTROL_FCNB	1	0	1707	1
Bin	FILTER_CONTROL_FCNE	0	1	105	1
Bin	FILTER_CONTROL_FCNE	1	0	1706	1
Bin	FILTER_CONTROL_FCFB	0	1	107	1
Bin	FILTER_CONTROL_FCFB	1	0	1708	1
Bin	FILTER_CONTROL_FCFE	0	1	105	1
Bin	FILTER_CONTROL_FCFE	1	0	1706	1
Bin	FILTER_CONTROL_FRNB	0	1	6	1
Bin	FILTER_CONTROL_FRNB	1	0	1607	1
Bin	FILTER_CONTROL_FRNE	0	1	5	1
Bin	FILTER_CONTROL_FRNE	1	0	1606	1
Bin	FILTER_CONTROL_FRFB	0	1	6	1
Bin	FILTER_CONTROL_FRFB	1	0	1607	1
Bin	FILTER_CONTROL_FRFE	0	1	5	1
Bin	FILTER_CONTROL_FRFE	1	0	1606	1
Bin	RX_SETTINGS_RTSOP	0	1	5	1
Bin	RX_SETTINGS_RTSOP	1	0	1606	1
Bin	RX_DATA_READ	0	1	51790	1
Bin	RX_DATA_READ	1	0	53391	1
Bin	TX_COMMAND_TXCE	0	1	354	1
Bin	TX_COMMAND_TXCE	1	0	25076	1
Bin	TX_COMMAND_TXCR	0	1	21387	1
Bin	TX_COMMAND_TXCR	1	0	25076	1
Bin	TX_COMMAND_TXCA	0	1	1734	1
Bin	TX_COMMAND_TXCA	1	0	25076	1
Bin	TX_COMMAND_TXB1	0	1	6553	1
Bin	TX_COMMAND_TXB1	1	0	8149	1
Bin	TX_COMMAND_TXB2	0	1	5587	1
Bin	TX_COMMAND_TXB2	1	0	7188	1
Bin	TX_COMMAND_TXB3	0	1	332	1
Bin	TX_COMMAND_TXB3	1	0	1933	1
Bin	TX_COMMAND_TXB4	0	1	345	1
Bin	TX_COMMAND_TXB4	1	0	1946	1
Bin	TX_COMMAND_TXB5	0	1	91	1
Bin	TX_COMMAND_TXB5	1	0	1692	1
Bin	TX_COMMAND_TXB6	0	1	73	1
Bin	TX_COMMAND_TXB6	1	0	1674	1
Bin	TX_COMMAND_TXB7	0	1	87	1
Bin	TX_COMMAND_TXB7	1	0	1688	1
Bin	TX_COMMAND_TXB8	0	1	74	1
Bin	TX_COMMAND_TXB8	1	0	1675	1
Bin	TX_PRIORITY_TXT1P(2)	0	1	105	1
Bin	TX_PRIORITY_TXT1P(2)	1	0	1706	1
Bin	TX_PRIORITY_TXT1P(1)	0	1	111	1
Bin	TX_PRIORITY_TXT1P(1)	1	0	1712	1
Bin	TX_PRIORITY_TXT1P(0)	0	1	1723	1
Bin	TX_PRIORITY_TXT1P(0)	1	0	122	1
Bin	TX_PRIORITY_TXT2P(2)	0	1	94	1
Bin	TX_PRIORITY_TXT2P(2)	1	0	1695	1
Bin	TX_PRIORITY_TXT2P(1)	0	1	131	1
Bin	TX_PRIORITY_TXT2P(1)	1	0	1732	1
Bin	TX_PRIORITY_TXT2P(0)	0	1	124	1
Bin	TX_PRIORITY_TXT2P(0)	1	0	1725	1
Bin	TX_PRIORITY_TXT3P(2)	0	1	72	1
Bin	TX_PRIORITY_TXT3P(2)	1	0	1673	1
Bin	TX_PRIORITY_TXT3P(1)	0	1	103	1
Bin	TX_PRIORITY_TXT3P(1)	1	0	1704	1
Bin	TX_PRIORITY_TXT3P(0)	0	1	96	1
Bin	TX_PRIORITY_TXT3P(0)	1	0	1697	1
Bin	TX_PRIORITY_TXT4P(2)	0	1	77	1
Bin	TX_PRIORITY_TXT4P(2)	1	0	1678	1
Bin	TX_PRIORITY_TXT4P(1)	0	1	91	1
Bin	TX_PRIORITY_TXT4P(1)	1	0	1692	1
Bin	TX_PRIORITY_TXT4P(0)	0	1	99	1
Bin	TX_PRIORITY_TXT4P(0)	1	0	1700	1
Bin	TX_PRIORITY_TXT5P(2)	0	1	23	1
Bin	TX_PRIORITY_TXT5P(2)	1	0	1624	1
Bin	TX_PRIORITY_TXT5P(1)	0	1	33	1
Bin	TX_PRIORITY_TXT5P(1)	1	0	1634	1
Bin	TX_PRIORITY_TXT5P(0)	0	1	29	1
Bin	TX_PRIORITY_TXT5P(0)	1	0	1630	1
Bin	TX_PRIORITY_TXT6P(2)	0	1	28	1
Bin	TX_PRIORITY_TXT6P(2)	1	0	1629	1
Bin	TX_PRIORITY_TXT6P(1)	0	1	31	1
Bin	TX_PRIORITY_TXT6P(1)	1	0	1632	1
Bin	TX_PRIORITY_TXT6P(0)	0	1	33	1
Bin	TX_PRIORITY_TXT6P(0)	1	0	1634	1
Bin	TX_PRIORITY_TXT7P(2)	0	1	26	1
Bin	TX_PRIORITY_TXT7P(2)	1	0	1627	1
Bin	TX_PRIORITY_TXT7P(1)	0	1	27	1
Bin	TX_PRIORITY_TXT7P(1)	1	0	1628	1
Bin	TX_PRIORITY_TXT7P(0)	0	1	31	1
Bin	TX_PRIORITY_TXT7P(0)	1	0	1632	1
Bin	TX_PRIORITY_TXT8P(2)	0	1	27	1
Bin	TX_PRIORITY_TXT8P(2)	1	0	1628	1
Bin	TX_PRIORITY_TXT8P(1)	0	1	31	1
Bin	TX_PRIORITY_TXT8P(1)	1	0	1632	1
Bin	TX_PRIORITY_TXT8P(0)	0	1	28	1
Bin	TX_PRIORITY_TXT8P(0)	1	0	1629	1
Bin	SSP_CFG_SSP_OFFSET(7)	0	1	24	1
Bin	SSP_CFG_SSP_OFFSET(7)	1	0	1625	1
Bin	SSP_CFG_SSP_OFFSET(6)	0	1	23	1
Bin	SSP_CFG_SSP_OFFSET(6)	1	0	1624	1
Bin	SSP_CFG_SSP_OFFSET(5)	0	1	48	1
Bin	SSP_CFG_SSP_OFFSET(5)	1	0	1649	1
Bin	SSP_CFG_SSP_OFFSET(4)	0	1	50	1
Bin	SSP_CFG_SSP_OFFSET(4)	1	0	1651	1
Bin	SSP_CFG_SSP_OFFSET(3)	0	1	4306	1
Bin	SSP_CFG_SSP_OFFSET(3)	1	0	2716	1
Bin	SSP_CFG_SSP_OFFSET(2)	0	1	535	1
Bin	SSP_CFG_SSP_OFFSET(2)	1	0	2135	1
Bin	SSP_CFG_SSP_OFFSET(1)	0	1	2902	1
Bin	SSP_CFG_SSP_OFFSET(1)	1	0	1313	1
Bin	SSP_CFG_SSP_OFFSET(0)	0	1	2397	1
Bin	SSP_CFG_SSP_OFFSET(0)	1	0	3997	1
Bin	SSP_CFG_SSP_SRC(1)	0	1	45	1
Bin	SSP_CFG_SSP_SRC(1)	1	0	1646	1
Bin	SSP_CFG_SSP_SRC(0)	0	1	815	1
Bin	SSP_CFG_SSP_SRC(0)	1	0	2405	1

Signal:

MR_CTRL_IN

	Element	From	To	Count	Threshold
Bin	DEVICE_ID_DEVICE_ID(15)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(14)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(13)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(12)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(11)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(10)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(9)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(8)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(7)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(6)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(5)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(4)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(3)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(2)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(1)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(0)	0	1	1601	1
Bin	VERSION_VER_MINOR(7)	1	0	1601	1
Bin	VERSION_VER_MINOR(6)	1	0	1601	1
Bin	VERSION_VER_MINOR(5)	1	0	1601	1
Bin	VERSION_VER_MINOR(4)	1	0	1601	1
Bin	VERSION_VER_MINOR(3)	1	0	1601	1
Bin	VERSION_VER_MINOR(2)	0	1	1601	1
Bin	VERSION_VER_MINOR(1)	0	1	1601	1
Bin	VERSION_VER_MINOR(0)	0	1	1601	1
Bin	VERSION_VER_MAJOR(7)	1	0	1601	1
Bin	VERSION_VER_MAJOR(6)	1	0	1601	1
Bin	VERSION_VER_MAJOR(5)	1	0	1601	1
Bin	VERSION_VER_MAJOR(4)	1	0	1601	1
Bin	VERSION_VER_MAJOR(3)	1	0	1601	1
Bin	VERSION_VER_MAJOR(2)	1	0	1601	1
Bin	VERSION_VER_MAJOR(1)	0	1	1601	1
Bin	VERSION_VER_MAJOR(0)	1	0	1601	1
Bin	STATUS_RXNE	0	1	9001	1
Bin	STATUS_RXNE	1	0	8999	1
Bin	STATUS_DOR	0	1	31	1
Bin	STATUS_DOR	1	0	1632	1
Bin	STATUS_TXNF	0	1	2480	1
Bin	STATUS_TXNF	1	0	2480	1
Bin	STATUS_EFT	0	1	27135	1
Bin	STATUS_EFT	1	0	28729	1
Bin	STATUS_RXS	0	1	30908	1
Bin	STATUS_RXS	1	0	32502	1
Bin	STATUS_TXS	0	1	20317	1
Bin	STATUS_TXS	1	0	21917	1
Bin	STATUS_EWL	0	1	778	1
Bin	STATUS_EWL	1	0	2378	1
Bin	STATUS_IDLE	0	1	51454	1
Bin	STATUS_IDLE	1	0	51462	1
Bin	STATUS_PEXS	0	1	75	1
Bin	STATUS_PEXS	1	0	1676	1
Bin	STATUS_RXPE	0	1	9	1
Bin	STATUS_RXPE	1	0	1610	1
Bin	STATUS_TXPE	0	1	317	1
Bin	STATUS_TXPE	1	0	1918	1
Bin	STATUS_TXDPE	0	1	44	1
Bin	STATUS_TXDPE	1	0	1645	1
Bin	STATUS_STCNT	0	1	660	1
Bin	STATUS_STCNT	1	0	941	1
Bin	STATUS_STRGS	0	1	1601	1
Bin	STATUS_SPRT	0	1	660	1
Bin	STATUS_SPRT	1	0	941	1
Bin	INT_STAT_RXI	0	1	808	1
Bin	INT_STAT_RXI	1	0	2407	1
Bin	INT_STAT_TXI	0	1	1215	1
Bin	INT_STAT_TXI	1	0	2812	1
Bin	INT_STAT_EWLI	0	1	587	1
Bin	INT_STAT_EWLI	1	0	2187	1
Bin	INT_STAT_DOI	0	1	21	1
Bin	INT_STAT_DOI	1	0	1622	1
Bin	INT_STAT_FCSI	0	1	3304	1
Bin	INT_STAT_FCSI	1	0	4893	1
Bin	INT_STAT_ALI	0	1	99	1
Bin	INT_STAT_ALI	1	0	1698	1
Bin	INT_STAT_BEI	0	1	1417	1
Bin	INT_STAT_BEI	1	0	3010	1
Bin	INT_STAT_OFI	0	1	152	1
Bin	INT_STAT_OFI	1	0	1753	1
Bin	INT_STAT_RXFI	0	1	20	1
Bin	INT_STAT_RXFI	1	0	1621	1
Bin	INT_STAT_BSI	0	1	1299	1
Bin	INT_STAT_BSI	1	0	2894	1
Bin	INT_STAT_RBNEI	0	1	936	1
Bin	INT_STAT_RBNEI	1	0	2535	1
Bin	INT_STAT_TXBHCI	0	1	1680	1
Bin	INT_STAT_TXBHCI	1	0	3276	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	0	1	66	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	1	0	1667	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	0	1	30	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	1	0	1631	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	0	1	50	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	1	0	1651	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	1	0	1621	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	1	0	1616	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	0	1	22	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	1	0	1623	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	0	1	20	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	1	0	1621	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	0	1	20	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	1	0	1621	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	1	0	1611	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	1	0	1611	1
Bin	FAULT_STATE_ERA	0	1	8426	1
Bin	FAULT_STATE_ERA	1	0	8415	1
Bin	FAULT_STATE_ERP	0	1	761	1
Bin	FAULT_STATE_ERP	1	0	2362	1
Bin	FAULT_STATE_BOF	0	1	8227	1
Bin	FAULT_STATE_BOF	1	0	8238	1
Bin	REC_REC_VAL(8)	0	1	126	1
Bin	REC_REC_VAL(8)	1	0	1727	1
Bin	REC_REC_VAL(7)	0	1	344	1
Bin	REC_REC_VAL(7)	1	0	1945	1
Bin	REC_REC_VAL(6)	0	1	262	1
Bin	REC_REC_VAL(6)	1	0	1860	1
Bin	REC_REC_VAL(5)	0	1	343	1
Bin	REC_REC_VAL(5)	1	0	1943	1
Bin	REC_REC_VAL(4)	0	1	501	1
Bin	REC_REC_VAL(4)	1	0	2101	1
Bin	REC_REC_VAL(3)	0	1	680	1
Bin	REC_REC_VAL(3)	1	0	2280	1
Bin	REC_REC_VAL(2)	0	1	639	1
Bin	REC_REC_VAL(2)	1	0	2240	1
Bin	REC_REC_VAL(1)	0	1	1198	1
Bin	REC_REC_VAL(1)	1	0	2799	1
Bin	REC_REC_VAL(0)	0	1	11242	1
Bin	REC_REC_VAL(0)	1	0	12836	1
Bin	TEC_TEC_VAL(8)	0	1	246	1
Bin	TEC_TEC_VAL(8)	1	0	1847	1
Bin	TEC_TEC_VAL(7)	0	1	506	1
Bin	TEC_TEC_VAL(7)	1	0	2107	1
Bin	TEC_TEC_VAL(6)	0	1	504	1
Bin	TEC_TEC_VAL(6)	1	0	2105	1
Bin	TEC_TEC_VAL(5)	0	1	787	1
Bin	TEC_TEC_VAL(5)	1	0	2388	1
Bin	TEC_TEC_VAL(4)	0	1	1957	1
Bin	TEC_TEC_VAL(4)	1	0	3557	1
Bin	TEC_TEC_VAL(3)	0	1	12521	1
Bin	TEC_TEC_VAL(3)	1	0	14122	1
Bin	TEC_TEC_VAL(2)	0	1	2978	1
Bin	TEC_TEC_VAL(2)	1	0	4579	1
Bin	TEC_TEC_VAL(1)	0	1	3314	1
Bin	TEC_TEC_VAL(1)	1	0	4915	1
Bin	TEC_TEC_VAL(0)	0	1	3548	1
Bin	TEC_TEC_VAL(0)	1	0	5149	1
Bin	ERR_NORM_ERR_NORM_VAL(15)	0	1	67	1
Bin	ERR_NORM_ERR_NORM_VAL(15)	1	0	1665	1
Bin	ERR_NORM_ERR_NORM_VAL(14)	0	1	65	1
Bin	ERR_NORM_ERR_NORM_VAL(14)	1	0	1663	1
Bin	ERR_NORM_ERR_NORM_VAL(13)	0	1	66	1
Bin	ERR_NORM_ERR_NORM_VAL(13)	1	0	1662	1
Bin	ERR_NORM_ERR_NORM_VAL(12)	0	1	61	1
Bin	ERR_NORM_ERR_NORM_VAL(12)	1	0	1659	1
Bin	ERR_NORM_ERR_NORM_VAL(11)	0	1	71	1
Bin	ERR_NORM_ERR_NORM_VAL(11)	1	0	1670	1
Bin	ERR_NORM_ERR_NORM_VAL(10)	0	1	67	1
Bin	ERR_NORM_ERR_NORM_VAL(10)	1	0	1665	1
Bin	ERR_NORM_ERR_NORM_VAL(9)	0	1	54	1
Bin	ERR_NORM_ERR_NORM_VAL(9)	1	0	1654	1
Bin	ERR_NORM_ERR_NORM_VAL(8)	0	1	71	1
Bin	ERR_NORM_ERR_NORM_VAL(8)	1	0	1668	1
Bin	ERR_NORM_ERR_NORM_VAL(7)	0	1	83	1
Bin	ERR_NORM_ERR_NORM_VAL(7)	1	0	1682	1
Bin	ERR_NORM_ERR_NORM_VAL(6)	0	1	97	1
Bin	ERR_NORM_ERR_NORM_VAL(6)	1	0	1695	1
Bin	ERR_NORM_ERR_NORM_VAL(5)	0	1	150	1
Bin	ERR_NORM_ERR_NORM_VAL(5)	1	0	1747	1
Bin	ERR_NORM_ERR_NORM_VAL(4)	0	1	271	1
Bin	ERR_NORM_ERR_NORM_VAL(4)	1	0	1869	1
Bin	ERR_NORM_ERR_NORM_VAL(3)	0	1	605	1
Bin	ERR_NORM_ERR_NORM_VAL(3)	1	0	2200	1
Bin	ERR_NORM_ERR_NORM_VAL(2)	0	1	1369	1
Bin	ERR_NORM_ERR_NORM_VAL(2)	1	0	2967	1
Bin	ERR_NORM_ERR_NORM_VAL(1)	0	1	3083	1
Bin	ERR_NORM_ERR_NORM_VAL(1)	1	0	4677	1
Bin	ERR_NORM_ERR_NORM_VAL(0)	0	1	11506	1
Bin	ERR_NORM_ERR_NORM_VAL(0)	1	0	13100	1
Bin	ERR_FD_ERR_FD_VAL(15)	0	1	59	1
Bin	ERR_FD_ERR_FD_VAL(15)	1	0	1657	1
Bin	ERR_FD_ERR_FD_VAL(14)	0	1	68	1
Bin	ERR_FD_ERR_FD_VAL(14)	1	0	1666	1
Bin	ERR_FD_ERR_FD_VAL(13)	0	1	70	1
Bin	ERR_FD_ERR_FD_VAL(13)	1	0	1669	1
Bin	ERR_FD_ERR_FD_VAL(12)	0	1	66	1
Bin	ERR_FD_ERR_FD_VAL(12)	1	0	1665	1
Bin	ERR_FD_ERR_FD_VAL(11)	0	1	63	1
Bin	ERR_FD_ERR_FD_VAL(11)	1	0	1663	1
Bin	ERR_FD_ERR_FD_VAL(10)	0	1	68	1
Bin	ERR_FD_ERR_FD_VAL(10)	1	0	1666	1
Bin	ERR_FD_ERR_FD_VAL(9)	0	1	77	1
Bin	ERR_FD_ERR_FD_VAL(9)	1	0	1674	1
Bin	ERR_FD_ERR_FD_VAL(8)	0	1	90	1
Bin	ERR_FD_ERR_FD_VAL(8)	1	0	1688	1
Bin	ERR_FD_ERR_FD_VAL(7)	0	1	99	1
Bin	ERR_FD_ERR_FD_VAL(7)	1	0	1698	1
Bin	ERR_FD_ERR_FD_VAL(6)	0	1	126	1
Bin	ERR_FD_ERR_FD_VAL(6)	1	0	1723	1
Bin	ERR_FD_ERR_FD_VAL(5)	0	1	212	1
Bin	ERR_FD_ERR_FD_VAL(5)	1	0	1809	1
Bin	ERR_FD_ERR_FD_VAL(4)	0	1	363	1
Bin	ERR_FD_ERR_FD_VAL(4)	1	0	1962	1
Bin	ERR_FD_ERR_FD_VAL(3)	0	1	679	1
Bin	ERR_FD_ERR_FD_VAL(3)	1	0	2278	1
Bin	ERR_FD_ERR_FD_VAL(2)	0	1	1288	1
Bin	ERR_FD_ERR_FD_VAL(2)	1	0	2888	1
Bin	ERR_FD_ERR_FD_VAL(1)	0	1	2512	1
Bin	ERR_FD_ERR_FD_VAL(1)	1	0	4112	1
Bin	ERR_FD_ERR_FD_VAL(0)	0	1	5598	1
Bin	ERR_FD_ERR_FD_VAL(0)	1	0	7196	1
Bin	FILTER_STATUS_SFA	0	1	660	1
Bin	FILTER_STATUS_SFA	1	0	941	1
Bin	FILTER_STATUS_SFB	0	1	165	1
Bin	FILTER_STATUS_SFB	1	0	1436	1
Bin	FILTER_STATUS_SFC	0	1	165	1
Bin	FILTER_STATUS_SFC	1	0	1436	1
Bin	FILTER_STATUS_SFR	0	1	165	1
Bin	FILTER_STATUS_SFR	1	0	1436	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(12)	0	1	165	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(12)	1	0	1436	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(11)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(10)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(9)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(8)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(7)	0	1	495	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(7)	1	0	1106	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(6)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(5)	0	1	941	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(5)	1	0	660	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(4)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(3)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(2)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(1)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(0)	1	0	1601	1
Bin	RX_MEM_INFO_RX_MEM_FREE(12)	0	1	1239	1
Bin	RX_MEM_INFO_RX_MEM_FREE(12)	1	0	49652	1
Bin	RX_MEM_INFO_RX_MEM_FREE(11)	0	1	1076	1
Bin	RX_MEM_INFO_RX_MEM_FREE(11)	1	0	49819	1
Bin	RX_MEM_INFO_RX_MEM_FREE(10)	0	1	1083	1
Bin	RX_MEM_INFO_RX_MEM_FREE(10)	1	0	49826	1
Bin	RX_MEM_INFO_RX_MEM_FREE(9)	0	1	1097	1
Bin	RX_MEM_INFO_RX_MEM_FREE(9)	1	0	49840	1
Bin	RX_MEM_INFO_RX_MEM_FREE(8)	0	1	1125	1
Bin	RX_MEM_INFO_RX_MEM_FREE(8)	1	0	49868	1
Bin	RX_MEM_INFO_RX_MEM_FREE(7)	0	1	4532	1
Bin	RX_MEM_INFO_RX_MEM_FREE(7)	1	0	30351	1
Bin	RX_MEM_INFO_RX_MEM_FREE(6)	0	1	4159	1
Bin	RX_MEM_INFO_RX_MEM_FREE(6)	1	0	30968	1
Bin	RX_MEM_INFO_RX_MEM_FREE(5)	0	1	8826	1
Bin	RX_MEM_INFO_RX_MEM_FREE(5)	1	0	8547	1
Bin	RX_MEM_INFO_RX_MEM_FREE(4)	0	1	8414	1
Bin	RX_MEM_INFO_RX_MEM_FREE(4)	1	0	10013	1
Bin	RX_MEM_INFO_RX_MEM_FREE(3)	0	1	10005	1
Bin	RX_MEM_INFO_RX_MEM_FREE(3)	1	0	11604	1
Bin	RX_MEM_INFO_RX_MEM_FREE(2)	0	1	12209	1
Bin	RX_MEM_INFO_RX_MEM_FREE(2)	1	0	13808	1
Bin	RX_MEM_INFO_RX_MEM_FREE(1)	0	1	16073	1
Bin	RX_MEM_INFO_RX_MEM_FREE(1)	1	0	17674	1
Bin	RX_MEM_INFO_RX_MEM_FREE(0)	0	1	27447	1
Bin	RX_MEM_INFO_RX_MEM_FREE(0)	1	0	29048	1
Bin	RX_POINTERS_RX_WPP(11)	0	1	5	1
Bin	RX_POINTERS_RX_WPP(11)	1	0	11743	1
Bin	RX_POINTERS_RX_WPP(10)	0	1	11	1
Bin	RX_POINTERS_RX_WPP(10)	1	0	11749	1
Bin	RX_POINTERS_RX_WPP(9)	0	1	23	1
Bin	RX_POINTERS_RX_WPP(9)	1	0	11761	1
Bin	RX_POINTERS_RX_WPP(8)	0	1	45	1
Bin	RX_POINTERS_RX_WPP(8)	1	0	11783	1
Bin	RX_POINTERS_RX_WPP(7)	0	1	89	1
Bin	RX_POINTERS_RX_WPP(7)	1	0	11827	1
Bin	RX_POINTERS_RX_WPP(6)	0	1	311	1
Bin	RX_POINTERS_RX_WPP(6)	1	0	6965	1
Bin	RX_POINTERS_RX_WPP(5)	0	1	669	1
Bin	RX_POINTERS_RX_WPP(5)	1	0	7323	1
Bin	RX_POINTERS_RX_WPP(4)	0	1	1971	1
Bin	RX_POINTERS_RX_WPP(4)	1	0	3572	1
Bin	RX_POINTERS_RX_WPP(3)	0	1	3777	1
Bin	RX_POINTERS_RX_WPP(3)	1	0	5378	1
Bin	RX_POINTERS_RX_WPP(2)	0	1	6171	1
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Bin	TS_INFO_TS_BITS(0)	0	1	1601	1
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Bin	TRV_DELAY_TRV_DELAY_VALUE(5)	0	1	73	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(5)	1	0	1674	1
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Bin	TRV_DELAY_TRV_DELAY_VALUE(2)	1	0	1680	1
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Bin	TRV_DELAY_TRV_DELAY_VALUE(1)	1	0	3746	1
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Bin	TRV_DELAY_TRV_DELAY_VALUE(0)	1	0	1657	1
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Bin	RX_FR_CTR_RX_FR_CTR_VAL(29)	0	1	51	1
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Bin	RX_FR_CTR_RX_FR_CTR_VAL(28)	1	0	1648	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(27)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(27)	1	0	1652	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(26)	0	1	49	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(26)	1	0	1650	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(25)	0	1	49	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(25)	1	0	1647	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(24)	0	1	57	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(24)	1	0	1656	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(23)	0	1	49	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(23)	1	0	1650	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(22)	0	1	49	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(22)	1	0	1650	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(21)	0	1	54	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(21)	1	0	1653	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(20)	0	1	57	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(20)	1	0	1656	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(19)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(19)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(18)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(18)	1	0	1652	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(17)	0	1	55	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(17)	1	0	1654	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(16)	0	1	54	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(16)	1	0	1653	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(15)	0	1	54	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(15)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(14)	0	1	47	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(14)	1	0	1647	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(13)	0	1	57	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(13)	1	0	1656	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(12)	0	1	61	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(12)	1	0	1660	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(11)	0	1	50	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(11)	1	0	1648	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(10)	0	1	54	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(10)	1	0	1652	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(9)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(9)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(8)	0	1	66	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(8)	1	0	1665	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(7)	0	1	87	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(7)	1	0	1686	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(6)	0	1	113	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(6)	1	0	1712	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(5)	0	1	215	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(5)	1	0	1814	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(4)	0	1	353	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(4)	1	0	1953	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(3)	0	1	747	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(3)	1	0	2345	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(2)	0	1	1493	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(2)	1	0	3092	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(1)	0	1	2963	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(1)	1	0	4561	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(0)	0	1	5921	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(0)	1	0	7521	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(31)	0	1	101	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(31)	1	0	1702	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(30)	0	1	106	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(30)	1	0	1707	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(29)	0	1	110	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(29)	1	0	1711	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(28)	0	1	98	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(28)	1	0	1699	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(27)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(27)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(26)	0	1	101	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(26)	1	0	1702	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(25)	0	1	99	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(25)	1	0	1700	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(24)	0	1	97	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(24)	1	0	1698	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(23)	0	1	102	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(23)	1	0	1703	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(22)	0	1	100	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(22)	1	0	1701	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(21)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(21)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(20)	0	1	108	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(20)	1	0	1709	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(19)	0	1	97	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(19)	1	0	1698	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(18)	0	1	98	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(18)	1	0	1699	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(17)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(17)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(16)	0	1	111	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(16)	1	0	1712	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(15)	0	1	102	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(15)	1	0	1703	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(14)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(14)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(13)	0	1	91	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(13)	1	0	1692	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(12)	0	1	99	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(12)	1	0	1700	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(11)	0	1	98	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(11)	1	0	1699	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(10)	0	1	96	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(10)	1	0	1697	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(9)	0	1	106	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(9)	1	0	1707	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(8)	0	1	104	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(8)	1	0	1705	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(7)	0	1	103	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(7)	1	0	1704	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(6)	0	1	108	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(6)	1	0	1709	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(5)	0	1	109	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(5)	1	0	1710	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(4)	0	1	152	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(4)	1	0	1753	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(3)	0	1	258	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(3)	1	0	1859	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(2)	0	1	619	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(2)	1	0	2220	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(1)	0	1	1052	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(1)	1	0	2653	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(0)	0	1	2203	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(0)	1	0	3804	1
Bin	DEBUG_REGISTER_STUFF_COUNT(2)	0	1	33452	1
Bin	DEBUG_REGISTER_STUFF_COUNT(2)	1	0	35053	1
Bin	DEBUG_REGISTER_STUFF_COUNT(1)	0	1	70940	1
Bin	DEBUG_REGISTER_STUFF_COUNT(1)	1	0	72538	1
Bin	DEBUG_REGISTER_STUFF_COUNT(0)	0	1	141315	1
Bin	DEBUG_REGISTER_STUFF_COUNT(0)	1	0	142914	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(2)	0	1	117682	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(2)	1	0	119283	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(1)	0	1	242662	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(1)	1	0	244257	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(0)	0	1	484884	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(0)	1	0	486480	1
Bin	DEBUG_REGISTER_PC_ARB	0	1	55723	1
Bin	DEBUG_REGISTER_PC_ARB	1	0	57324	1
Bin	DEBUG_REGISTER_PC_CON	0	1	50970	1
Bin	DEBUG_REGISTER_PC_CON	1	0	52571	1
Bin	DEBUG_REGISTER_PC_DAT	0	1	36820	1
Bin	DEBUG_REGISTER_PC_DAT	1	0	38421	1
Bin	DEBUG_REGISTER_PC_STC	0	1	13502	1
Bin	DEBUG_REGISTER_PC_STC	1	0	15103	1
Bin	DEBUG_REGISTER_PC_CRC	0	1	31213	1
Bin	DEBUG_REGISTER_PC_CRC	1	0	32814	1
Bin	DEBUG_REGISTER_PC_CRCD	0	1	29735	1
Bin	DEBUG_REGISTER_PC_CRCD	1	0	31336	1
Bin	DEBUG_REGISTER_PC_ACK	0	1	29588	1
Bin	DEBUG_REGISTER_PC_ACK	1	0	31189	1
Bin	DEBUG_REGISTER_PC_ACKD	0	1	28165	1
Bin	DEBUG_REGISTER_PC_ACKD	1	0	29766	1
Bin	DEBUG_REGISTER_PC_EOF	0	1	27273	1
Bin	DEBUG_REGISTER_PC_EOF	1	0	28874	1
Bin	DEBUG_REGISTER_PC_INT	0	1	51716	1
Bin	DEBUG_REGISTER_PC_INT	1	0	53316	1
Bin	DEBUG_REGISTER_PC_SUSP	0	1	2779	1
Bin	DEBUG_REGISTER_PC_SUSP	1	0	4380	1
Bin	DEBUG_REGISTER_PC_OVR	0	1	529	1
Bin	DEBUG_REGISTER_PC_OVR	1	0	2130	1
Bin	DEBUG_REGISTER_PC_SOF	0	1	24924	1
Bin	DEBUG_REGISTER_PC_SOF	1	0	26525	1
Bin	YOLO_REG_YOLO_VAL(31)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(30)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(29)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(28)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(27)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(26)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(25)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(24)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(23)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(22)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(21)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(20)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(19)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(18)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(17)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(16)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(15)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(14)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(13)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(12)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(11)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(10)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(9)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(8)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(7)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(6)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(5)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(4)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(3)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(2)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(1)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(0)	0	1	1601	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(31)	0	1	43	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(31)	1	0	1643	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(30)	0	1	68	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(30)	1	0	1657	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(29)	0	1	60	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(29)	1	0	1656	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(28)	0	1	56	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(28)	1	0	1650	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(27)	0	1	60	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(27)	1	0	1653	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(26)	0	1	68	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(26)	1	0	1661	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(25)	0	1	61	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(25)	1	0	1654	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(24)	0	1	65	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(24)	1	0	1656	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(23)	0	1	80	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(23)	1	0	1664	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(22)	0	1	115	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(22)	1	0	1681	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(21)	0	1	155	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(21)	1	0	1721	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(20)	0	1	253	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(20)	1	0	1804	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(19)	0	1	540	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(19)	1	0	1991	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(18)	0	1	1001	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(18)	1	0	2479	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(17)	0	1	2081	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(17)	1	0	3417	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(16)	0	1	4185	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(16)	1	0	5438	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(15)	0	1	8268	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(15)	1	0	9537	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(14)	0	1	16605	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(14)	1	0	17754	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(13)	0	1	33247	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(13)	1	0	34309	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(12)	0	1	66551	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(12)	1	0	67500	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(11)	0	1	133055	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(11)	1	0	133977	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(10)	0	1	266193	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(10)	1	0	266979	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(9)	0	1	532264	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(9)	1	0	533095	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(8)	0	1	1064501	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(8)	1	0	1065312	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(7)	0	1	2128946	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(7)	1	0	2129759	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(6)	0	1	4257855	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(6)	1	0	4258653	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(5)	0	1	8515658	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(5)	1	0	8516449	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(4)	0	1	17031259	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(4)	1	0	17032062	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(3)	0	1	34062445	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(3)	1	0	34063255	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(2)	0	1	68124856	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(2)	1	0	68125653	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(1)	0	1	136249666	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(1)	1	0	136250439	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(0)	0	1	272499261	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(0)	1	0	272500058	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(31)	0	1	20	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(31)	1	0	1618	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(30)	0	1	74	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(30)	1	0	1665	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(29)	0	1	67	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(29)	1	0	1660	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(28)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(28)	1	0	1658	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(27)	0	1	64	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(27)	1	0	1657	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(26)	0	1	72	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(26)	1	0	1662	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(25)	0	1	62	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(25)	1	0	1655	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(24)	0	1	66	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(24)	1	0	1658	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(23)	0	1	63	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(23)	1	0	1654	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(22)	0	1	73	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(22)	1	0	1664	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(21)	0	1	69	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(21)	1	0	1662	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(20)	0	1	70	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(20)	1	0	1661	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(19)	0	1	69	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(19)	1	0	1662	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(18)	0	1	67	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(18)	1	0	1658	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(17)	0	1	61	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(17)	1	0	1653	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(16)	0	1	77	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(16)	1	0	1669	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(15)	0	1	69	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(15)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(14)	0	1	70	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(14)	1	0	1660	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(13)	0	1	74	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(13)	1	0	1664	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(12)	0	1	72	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(12)	1	0	1657	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(11)	0	1	74	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(11)	1	0	1663	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(10)	0	1	59	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(10)	1	0	1655	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(9)	0	1	66	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(9)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(8)	0	1	73	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(8)	1	0	1663	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(7)	0	1	77	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(7)	1	0	1665	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(6)	0	1	61	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(6)	1	0	1652	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(5)	0	1	63	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(5)	1	0	1653	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(4)	0	1	61	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(4)	1	0	1653	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(3)	0	1	62	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(3)	1	0	1651	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(2)	0	1	66	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(2)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(1)	0	1	68	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(1)	1	0	1660	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(0)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(0)	1	0	1658	1

Signal:

MR_TST_OUT_I

	Element	From	To	Count	Threshold
Bin	TST_CONTROL_TMAENA	0	1	648	1
Bin	TST_CONTROL_TMAENA	1	0	2249	1
Bin	TST_CONTROL_TWRSTB	0	1	32343	1
Bin	TST_CONTROL_TWRSTB	1	0	35235	1
Bin	TST_DEST_TST_ADDR(15)	0	1	5	1
Bin	TST_DEST_TST_ADDR(15)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(14)	0	1	5	1
Bin	TST_DEST_TST_ADDR(14)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(13)	0	1	5	1
Bin	TST_DEST_TST_ADDR(13)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(12)	0	1	5	1
Bin	TST_DEST_TST_ADDR(12)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(11)	0	1	15	1
Bin	TST_DEST_TST_ADDR(11)	1	0	1616	1
Bin	TST_DEST_TST_ADDR(10)	0	1	25	1
Bin	TST_DEST_TST_ADDR(10)	1	0	1626	1
Bin	TST_DEST_TST_ADDR(9)	0	1	45	1
Bin	TST_DEST_TST_ADDR(9)	1	0	1646	1
Bin	TST_DEST_TST_ADDR(8)	0	1	85	1
Bin	TST_DEST_TST_ADDR(8)	1	0	1686	1
Bin	TST_DEST_TST_ADDR(7)	0	1	165	1
Bin	TST_DEST_TST_ADDR(7)	1	0	1766	1
Bin	TST_DEST_TST_ADDR(6)	0	1	355	1
Bin	TST_DEST_TST_ADDR(6)	1	0	1956	1
Bin	TST_DEST_TST_ADDR(5)	0	1	705	1
Bin	TST_DEST_TST_ADDR(5)	1	0	2306	1
Bin	TST_DEST_TST_ADDR(4)	0	1	3617	1
Bin	TST_DEST_TST_ADDR(4)	1	0	5218	1
Bin	TST_DEST_TST_ADDR(3)	0	1	5036	1
Bin	TST_DEST_TST_ADDR(3)	1	0	6637	1
Bin	TST_DEST_TST_ADDR(2)	0	1	10348	1
Bin	TST_DEST_TST_ADDR(2)	1	0	11949	1
Bin	TST_DEST_TST_ADDR(1)	0	1	22453	1
Bin	TST_DEST_TST_ADDR(1)	1	0	24054	1
Bin	TST_DEST_TST_ADDR(0)	0	1	44900	1
Bin	TST_DEST_TST_ADDR(0)	1	0	46501	1
Bin	TST_DEST_TST_MTGT(3)	0	1	236	1
Bin	TST_DEST_TST_MTGT(3)	1	0	1837	1
Bin	TST_DEST_TST_MTGT(2)	0	1	373	1
Bin	TST_DEST_TST_MTGT(2)	1	0	1974	1
Bin	TST_DEST_TST_MTGT(1)	0	1	514	1
Bin	TST_DEST_TST_MTGT(1)	1	0	2115	1
Bin	TST_DEST_TST_MTGT(0)	0	1	979	1
Bin	TST_DEST_TST_MTGT(0)	1	0	2580	1
Bin	TST_WDATA_TST_WDATA(31)	0	1	1524	1
Bin	TST_WDATA_TST_WDATA(31)	1	0	3125	1
Bin	TST_WDATA_TST_WDATA(30)	0	1	1474	1
Bin	TST_WDATA_TST_WDATA(30)	1	0	3075	1
Bin	TST_WDATA_TST_WDATA(29)	0	1	1522	1
Bin	TST_WDATA_TST_WDATA(29)	1	0	3123	1
Bin	TST_WDATA_TST_WDATA(28)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(28)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(27)	0	1	1638	1
Bin	TST_WDATA_TST_WDATA(27)	1	0	3239	1
Bin	TST_WDATA_TST_WDATA(26)	0	1	1628	1
Bin	TST_WDATA_TST_WDATA(26)	1	0	3229	1
Bin	TST_WDATA_TST_WDATA(25)	0	1	1652	1
Bin	TST_WDATA_TST_WDATA(25)	1	0	3253	1
Bin	TST_WDATA_TST_WDATA(24)	0	1	1686	1
Bin	TST_WDATA_TST_WDATA(24)	1	0	3287	1
Bin	TST_WDATA_TST_WDATA(23)	0	1	1580	1
Bin	TST_WDATA_TST_WDATA(23)	1	0	3181	1
Bin	TST_WDATA_TST_WDATA(22)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(22)	1	0	3130	1
Bin	TST_WDATA_TST_WDATA(21)	0	1	1580	1
Bin	TST_WDATA_TST_WDATA(21)	1	0	3181	1
Bin	TST_WDATA_TST_WDATA(20)	0	1	1659	1
Bin	TST_WDATA_TST_WDATA(20)	1	0	3260	1
Bin	TST_WDATA_TST_WDATA(19)	0	1	1673	1
Bin	TST_WDATA_TST_WDATA(19)	1	0	3274	1
Bin	TST_WDATA_TST_WDATA(18)	0	1	1660	1
Bin	TST_WDATA_TST_WDATA(18)	1	0	3261	1
Bin	TST_WDATA_TST_WDATA(17)	0	1	1624	1
Bin	TST_WDATA_TST_WDATA(17)	1	0	3225	1
Bin	TST_WDATA_TST_WDATA(16)	0	1	1658	1
Bin	TST_WDATA_TST_WDATA(16)	1	0	3259	1
Bin	TST_WDATA_TST_WDATA(15)	0	1	1598	1
Bin	TST_WDATA_TST_WDATA(15)	1	0	3199	1
Bin	TST_WDATA_TST_WDATA(14)	0	1	1523	1
Bin	TST_WDATA_TST_WDATA(14)	1	0	3124	1
Bin	TST_WDATA_TST_WDATA(13)	0	1	1588	1
Bin	TST_WDATA_TST_WDATA(13)	1	0	3189	1
Bin	TST_WDATA_TST_WDATA(12)	0	1	1665	1
Bin	TST_WDATA_TST_WDATA(12)	1	0	3266	1
Bin	TST_WDATA_TST_WDATA(11)	0	1	1665	1
Bin	TST_WDATA_TST_WDATA(11)	1	0	3266	1
Bin	TST_WDATA_TST_WDATA(10)	0	1	1644	1
Bin	TST_WDATA_TST_WDATA(10)	1	0	3245	1
Bin	TST_WDATA_TST_WDATA(9)	0	1	1680	1
Bin	TST_WDATA_TST_WDATA(9)	1	0	3281	1
Bin	TST_WDATA_TST_WDATA(8)	0	1	1711	1
Bin	TST_WDATA_TST_WDATA(8)	1	0	3312	1
Bin	TST_WDATA_TST_WDATA(7)	0	1	1605	1
Bin	TST_WDATA_TST_WDATA(7)	1	0	3206	1
Bin	TST_WDATA_TST_WDATA(6)	0	1	1553	1
Bin	TST_WDATA_TST_WDATA(6)	1	0	3154	1
Bin	TST_WDATA_TST_WDATA(5)	0	1	1586	1
Bin	TST_WDATA_TST_WDATA(5)	1	0	3187	1
Bin	TST_WDATA_TST_WDATA(4)	0	1	1660	1
Bin	TST_WDATA_TST_WDATA(4)	1	0	3261	1
Bin	TST_WDATA_TST_WDATA(3)	0	1	1643	1
Bin	TST_WDATA_TST_WDATA(3)	1	0	3244	1
Bin	TST_WDATA_TST_WDATA(2)	0	1	1661	1
Bin	TST_WDATA_TST_WDATA(2)	1	0	3262	1
Bin	TST_WDATA_TST_WDATA(1)	0	1	1697	1
Bin	TST_WDATA_TST_WDATA(1)	1	0	3298	1
Bin	TST_WDATA_TST_WDATA(0)	0	1	1695	1
Bin	TST_WDATA_TST_WDATA(0)	1	0	3296	1

Signal:

MR_TST_IN

	Element	From	To	Count	Threshold
Bin	TST_RDATA_TST_RDATA(31)	0	1	24008	1
Bin	TST_RDATA_TST_RDATA(31)	1	0	21102	1
Bin	TST_RDATA_TST_RDATA(30)	0	1	15026	1
Bin	TST_RDATA_TST_RDATA(30)	1	0	21139	1
Bin	TST_RDATA_TST_RDATA(29)	0	1	19384	1
Bin	TST_RDATA_TST_RDATA(29)	1	0	16478	1
Bin	TST_RDATA_TST_RDATA(28)	0	1	19767	1
Bin	TST_RDATA_TST_RDATA(28)	1	0	25880	1
Bin	TST_RDATA_TST_RDATA(27)	0	1	19869	1
Bin	TST_RDATA_TST_RDATA(27)	1	0	16963	1
Bin	TST_RDATA_TST_RDATA(26)	0	1	19815	1
Bin	TST_RDATA_TST_RDATA(26)	1	0	25928	1
Bin	TST_RDATA_TST_RDATA(25)	0	1	24459	1
Bin	TST_RDATA_TST_RDATA(25)	1	0	21553	1
Bin	TST_RDATA_TST_RDATA(24)	0	1	15515	1
Bin	TST_RDATA_TST_RDATA(24)	1	0	21628	1
Bin	TST_RDATA_TST_RDATA(23)	0	1	24270	1
Bin	TST_RDATA_TST_RDATA(23)	1	0	21364	1
Bin	TST_RDATA_TST_RDATA(22)	0	1	15248	1
Bin	TST_RDATA_TST_RDATA(22)	1	0	21361	1
Bin	TST_RDATA_TST_RDATA(21)	0	1	19742	1
Bin	TST_RDATA_TST_RDATA(21)	1	0	16836	1
Bin	TST_RDATA_TST_RDATA(20)	0	1	19820	1
Bin	TST_RDATA_TST_RDATA(20)	1	0	25933	1
Bin	TST_RDATA_TST_RDATA(19)	0	1	19961	1
Bin	TST_RDATA_TST_RDATA(19)	1	0	17055	1
Bin	TST_RDATA_TST_RDATA(18)	0	1	19943	1
Bin	TST_RDATA_TST_RDATA(18)	1	0	26056	1
Bin	TST_RDATA_TST_RDATA(17)	0	1	24384	1
Bin	TST_RDATA_TST_RDATA(17)	1	0	21478	1
Bin	TST_RDATA_TST_RDATA(16)	0	1	15261	1
Bin	TST_RDATA_TST_RDATA(16)	1	0	21374	1
Bin	TST_RDATA_TST_RDATA(15)	0	1	24180	1
Bin	TST_RDATA_TST_RDATA(15)	1	0	21274	1
Bin	TST_RDATA_TST_RDATA(14)	0	1	15199	1
Bin	TST_RDATA_TST_RDATA(14)	1	0	21312	1
Bin	TST_RDATA_TST_RDATA(13)	0	1	19671	1
Bin	TST_RDATA_TST_RDATA(13)	1	0	16765	1
Bin	TST_RDATA_TST_RDATA(12)	0	1	19754	1
Bin	TST_RDATA_TST_RDATA(12)	1	0	25867	1
Bin	TST_RDATA_TST_RDATA(11)	0	1	19865	1
Bin	TST_RDATA_TST_RDATA(11)	1	0	16959	1
Bin	TST_RDATA_TST_RDATA(10)	0	1	19770	1
Bin	TST_RDATA_TST_RDATA(10)	1	0	25883	1
Bin	TST_RDATA_TST_RDATA(9)	0	1	24487	1
Bin	TST_RDATA_TST_RDATA(9)	1	0	21581	1
Bin	TST_RDATA_TST_RDATA(8)	0	1	15360	1
Bin	TST_RDATA_TST_RDATA(8)	1	0	21473	1
Bin	TST_RDATA_TST_RDATA(7)	0	1	24311	1
Bin	TST_RDATA_TST_RDATA(7)	1	0	21405	1
Bin	TST_RDATA_TST_RDATA(6)	0	1	15276	1
Bin	TST_RDATA_TST_RDATA(6)	1	0	21389	1
Bin	TST_RDATA_TST_RDATA(5)	0	1	19636	1
Bin	TST_RDATA_TST_RDATA(5)	1	0	16730	1
Bin	TST_RDATA_TST_RDATA(4)	0	1	19726	1
Bin	TST_RDATA_TST_RDATA(4)	1	0	25839	1
Bin	TST_RDATA_TST_RDATA(3)	0	1	19890	1
Bin	TST_RDATA_TST_RDATA(3)	1	0	16984	1
Bin	TST_RDATA_TST_RDATA(2)	0	1	19821	1
Bin	TST_RDATA_TST_RDATA(2)	1	0	25934	1
Bin	TST_RDATA_TST_RDATA(1)	0	1	24534	1
Bin	TST_RDATA_TST_RDATA(1)	1	0	21628	1
Bin	TST_RDATA_TST_RDATA(0)	0	1	15397	1
Bin	TST_RDATA_TST_RDATA(0)	1	0	21510	1

Signal:

MR_TST_RDATA_TST_RDATA_TXB_I

	Element	From	To	Count	Threshold
Bin	(7)(31)	0	1	121	1
Bin	(7)(31)	1	0	14581	1
Bin	(7)(30)	0	1	116	1
Bin	(7)(30)	1	0	14576	1
Bin	(7)(29)	0	1	115	1
Bin	(7)(29)	1	0	14575	1
Bin	(7)(28)	0	1	122	1
Bin	(7)(28)	1	0	14582	1
Bin	(7)(27)	0	1	124	1
Bin	(7)(27)	1	0	14584	1
Bin	(7)(26)	0	1	117	1
Bin	(7)(26)	1	0	14577	1
Bin	(7)(25)	0	1	123	1
Bin	(7)(25)	1	0	14583	1
Bin	(7)(24)	0	1	120	1
Bin	(7)(24)	1	0	14580	1
Bin	(7)(23)	0	1	131	1
Bin	(7)(23)	1	0	14591	1
Bin	(7)(22)	0	1	126	1
Bin	(7)(22)	1	0	14586	1
Bin	(7)(21)	0	1	128	1
Bin	(7)(21)	1	0	14588	1
Bin	(7)(20)	0	1	123	1
Bin	(7)(20)	1	0	14583	1
Bin	(7)(19)	0	1	112	1
Bin	(7)(19)	1	0	14572	1
Bin	(7)(18)	0	1	128	1
Bin	(7)(18)	1	0	14588	1
Bin	(7)(17)	0	1	128	1
Bin	(7)(17)	1	0	14588	1
Bin	(7)(16)	0	1	113	1
Bin	(7)(16)	1	0	14573	1
Bin	(7)(15)	0	1	122	1
Bin	(7)(15)	1	0	14582	1
Bin	(7)(14)	0	1	122	1
Bin	(7)(14)	1	0	14582	1
Bin	(7)(13)	0	1	124	1
Bin	(7)(13)	1	0	14604	1
Bin	(7)(12)	0	1	122	1
Bin	(7)(12)	1	0	14582	1
Bin	(7)(11)	0	1	123	1
Bin	(7)(11)	1	0	14583	1
Bin	(7)(10)	0	1	121	1
Bin	(7)(10)	1	0	14581	1
Bin	(7)(9)	0	1	118	1
Bin	(7)(9)	1	0	14892	1
Bin	(7)(8)	0	1	110	1
Bin	(7)(8)	1	0	14570	1
Bin	(7)(7)	0	1	122	1
Bin	(7)(7)	1	0	14896	1
Bin	(7)(6)	0	1	117	1
Bin	(7)(6)	1	0	14891	1
Bin	(7)(5)	0	1	123	1
Bin	(7)(5)	1	0	14583	1
Bin	(7)(4)	0	1	127	1
Bin	(7)(4)	1	0	14587	1
Bin	(7)(3)	0	1	124	1
Bin	(7)(3)	1	0	14898	1
Bin	(7)(2)	0	1	121	1
Bin	(7)(2)	1	0	14581	1
Bin	(7)(1)	0	1	121	1
Bin	(7)(1)	1	0	14584	1
Bin	(7)(0)	0	1	126	1
Bin	(7)(0)	1	0	14586	1
Bin	(6)(31)	0	1	122	1
Bin	(6)(31)	1	0	13923	1
Bin	(6)(30)	0	1	124	1
Bin	(6)(30)	1	0	14373	1
Bin	(6)(29)	0	1	119	1
Bin	(6)(29)	1	0	14368	1
Bin	(6)(28)	0	1	131	1
Bin	(6)(28)	1	0	14408	1
Bin	(6)(27)	0	1	131	1
Bin	(6)(27)	1	0	13989	1
Bin	(6)(26)	0	1	134	1
Bin	(6)(26)	1	0	14407	1
Bin	(6)(25)	0	1	137	1
Bin	(6)(25)	1	0	14462	1
Bin	(6)(24)	0	1	134	1
Bin	(6)(24)	1	0	14407	1
Bin	(6)(23)	0	1	143	1
Bin	(6)(23)	1	0	14473	1
Bin	(6)(22)	0	1	130	1
Bin	(6)(22)	1	0	13955	1
Bin	(6)(21)	0	1	135	1
Bin	(6)(21)	1	0	14384	1
Bin	(6)(20)	0	1	143	1
Bin	(6)(20)	1	0	14421	1
Bin	(6)(19)	0	1	131	1
Bin	(6)(19)	1	0	14461	1
Bin	(6)(18)	0	1	138	1
Bin	(6)(18)	1	0	14444	1
Bin	(6)(17)	0	1	134	1
Bin	(6)(17)	1	0	14383	1
Bin	(6)(16)	0	1	115	1
Bin	(6)(16)	1	0	13916	1
Bin	(6)(15)	0	1	135	1
Bin	(6)(15)	1	0	13979	1
Bin	(6)(14)	0	1	113	1
Bin	(6)(14)	1	0	13957	1
Bin	(6)(13)	0	1	125	1
Bin	(6)(13)	1	0	14417	1
Bin	(6)(12)	0	1	122	1
Bin	(6)(12)	1	0	13966	1
Bin	(6)(11)	0	1	126	1
Bin	(6)(11)	1	0	13927	1
Bin	(6)(10)	0	1	125	1
Bin	(6)(10)	1	0	14374	1
Bin	(6)(9)	0	1	129	1
Bin	(6)(9)	1	0	13953	1
Bin	(6)(8)	0	1	131	1
Bin	(6)(8)	1	0	14447	1
Bin	(6)(7)	0	1	135	1
Bin	(6)(7)	1	0	14407	1
Bin	(6)(6)	0	1	132	1
Bin	(6)(6)	1	0	14433	1
Bin	(6)(5)	0	1	129	1
Bin	(6)(5)	1	0	14424	1
Bin	(6)(4)	0	1	123	1
Bin	(6)(4)	1	0	14374	1
Bin	(6)(3)	0	1	127	1
Bin	(6)(3)	1	0	14405	1
Bin	(6)(2)	0	1	123	1
Bin	(6)(2)	1	0	14662	1
Bin	(6)(1)	0	1	134	1
Bin	(6)(1)	1	0	14268	1
Bin	(6)(0)	0	1	120	1
Bin	(6)(0)	1	0	13944	1
Bin	(5)(31)	0	1	128	1
Bin	(5)(31)	1	0	13670	1
Bin	(5)(30)	0	1	122	1
Bin	(5)(30)	1	0	13664	1
Bin	(5)(29)	0	1	124	1
Bin	(5)(29)	1	0	13675	1
Bin	(5)(28)	0	1	119	1
Bin	(5)(28)	1	0	13666	1
Bin	(5)(27)	0	1	123	1
Bin	(5)(27)	1	0	14571	1
Bin	(5)(26)	0	1	125	1
Bin	(5)(26)	1	0	14487	1
Bin	(5)(25)	0	1	136	1
Bin	(5)(25)	1	0	13592	1
Bin	(5)(24)	0	1	125	1
Bin	(5)(24)	1	0	13581	1
Bin	(5)(23)	0	1	132	1
Bin	(5)(23)	1	0	14546	1
Bin	(5)(22)	0	1	118	1
Bin	(5)(22)	1	0	13574	1
Bin	(5)(21)	0	1	117	1
Bin	(5)(21)	1	0	14565	1
Bin	(5)(20)	0	1	126	1
Bin	(5)(20)	1	0	13582	1
Bin	(5)(19)	0	1	131	1
Bin	(5)(19)	1	0	14493	1
Bin	(5)(18)	0	1	126	1
Bin	(5)(18)	1	0	13582	1
Bin	(5)(17)	0	1	123	1
Bin	(5)(17)	1	0	13579	1
Bin	(5)(16)	0	1	131	1
Bin	(5)(16)	1	0	14493	1
Bin	(5)(15)	0	1	113	1
Bin	(5)(15)	1	0	14475	1
Bin	(5)(14)	0	1	130	1
Bin	(5)(14)	1	0	13586	1
Bin	(5)(13)	0	1	124	1
Bin	(5)(13)	1	0	13666	1
Bin	(5)(12)	0	1	120	1
Bin	(5)(12)	1	0	13662	1
Bin	(5)(11)	0	1	113	1
Bin	(5)(11)	1	0	13655	1
Bin	(5)(10)	0	1	120	1
Bin	(5)(10)	1	0	13576	1
Bin	(5)(9)	0	1	134	1
Bin	(5)(9)	1	0	14501	1
Bin	(5)(8)	0	1	124	1
Bin	(5)(8)	1	0	14486	1
Bin	(5)(7)	0	1	134	1
Bin	(5)(7)	1	0	13944	1
Bin	(5)(6)	0	1	120	1
Bin	(5)(6)	1	0	13576	1
Bin	(5)(5)	0	1	120	1
Bin	(5)(5)	1	0	14568	1
Bin	(5)(4)	0	1	122	1
Bin	(5)(4)	1	0	14570	1
Bin	(5)(3)	0	1	131	1
Bin	(5)(3)	1	0	14498	1
Bin	(5)(2)	0	1	131	1
Bin	(5)(2)	1	0	13936	1
Bin	(5)(1)	0	1	128	1
Bin	(5)(1)	1	0	13847	1
Bin	(5)(0)	0	1	128	1
Bin	(5)(0)	1	0	14839	1
Bin	(4)(31)	0	1	124	1
Bin	(4)(31)	1	0	12908	1
Bin	(4)(30)	0	1	123	1
Bin	(4)(30)	1	0	14255	1
Bin	(4)(29)	0	1	113	1
Bin	(4)(29)	1	0	12950	1
Bin	(4)(28)	0	1	132	1
Bin	(4)(28)	1	0	12947	1
Bin	(4)(27)	0	1	139	1
Bin	(4)(27)	1	0	12943	1
Bin	(4)(26)	0	1	132	1
Bin	(4)(26)	1	0	14280	1
Bin	(4)(25)	0	1	134	1
Bin	(4)(25)	1	0	12933	1
Bin	(4)(24)	0	1	134	1
Bin	(4)(24)	1	0	14321	1
Bin	(4)(23)	0	1	135	1
Bin	(4)(23)	1	0	14328	1
Bin	(4)(22)	0	1	139	1
Bin	(4)(22)	1	0	12978	1
Bin	(4)(21)	0	1	142	1
Bin	(4)(21)	1	0	14296	1
Bin	(4)(20)	0	1	134	1
Bin	(4)(20)	1	0	14282	1
Bin	(4)(19)	0	1	128	1
Bin	(4)(19)	1	0	14290	1
Bin	(4)(18)	0	1	140	1
Bin	(4)(18)	1	0	14562	1
Bin	(4)(17)	0	1	133	1
Bin	(4)(17)	1	0	12923	1
Bin	(4)(16)	0	1	134	1
Bin	(4)(16)	1	0	12948	1
Bin	(4)(15)	0	1	123	1
Bin	(4)(15)	1	0	12891	1
Bin	(4)(14)	0	1	133	1
Bin	(4)(14)	1	0	14265	1
Bin	(4)(13)	0	1	134	1
Bin	(4)(13)	1	0	14272	1
Bin	(4)(12)	0	1	131	1
Bin	(4)(12)	1	0	14279	1
Bin	(4)(11)	0	1	135	1
Bin	(4)(11)	1	0	12909	1
Bin	(4)(10)	0	1	137	1
Bin	(4)(10)	1	0	14291	1
Bin	(4)(9)	0	1	133	1
Bin	(4)(9)	1	0	13049	1
Bin	(4)(8)	0	1	132	1
Bin	(4)(8)	1	0	12922	1
Bin	(4)(7)	0	1	135	1
Bin	(4)(7)	1	0	14421	1
Bin	(4)(6)	0	1	137	1
Bin	(4)(6)	1	0	14311	1
Bin	(4)(5)	0	1	138	1
Bin	(4)(5)	1	0	14312	1
Bin	(4)(4)	0	1	124	1
Bin	(4)(4)	1	0	12908	1
Bin	(4)(3)	0	1	127	1
Bin	(4)(3)	1	0	12895	1
Bin	(4)(2)	0	1	132	1
Bin	(4)(2)	1	0	12900	1
Bin	(4)(1)	0	1	134	1
Bin	(4)(1)	1	0	14292	1
Bin	(4)(0)	0	1	134	1
Bin	(4)(0)	1	0	13034	1
Bin	(3)(31)	0	1	480	1
Bin	(3)(31)	1	0	12191	1
Bin	(3)(30)	0	1	480	1
Bin	(3)(30)	1	0	12191	1
Bin	(3)(29)	0	1	456	1
Bin	(3)(29)	1	0	10387	1
Bin	(3)(28)	0	1	505	1
Bin	(3)(28)	1	0	12484	1
Bin	(3)(27)	0	1	503	1
Bin	(3)(27)	1	0	12850	1
Bin	(3)(26)	0	1	506	1
Bin	(3)(26)	1	0	10549	1
Bin	(3)(25)	0	1	509	1
Bin	(3)(25)	1	0	12687	1
Bin	(3)(24)	0	1	493	1
Bin	(3)(24)	1	0	12234	1
Bin	(3)(23)	0	1	515	1
Bin	(3)(23)	1	0	12505	1
Bin	(3)(22)	0	1	502	1
Bin	(3)(22)	1	0	12576	1
Bin	(3)(21)	0	1	531	1
Bin	(3)(21)	1	0	12513	1
Bin	(3)(20)	0	1	517	1
Bin	(3)(20)	1	0	10803	1
Bin	(3)(19)	0	1	512	1
Bin	(3)(19)	1	0	10752	1
Bin	(3)(18)	0	1	526	1
Bin	(3)(18)	1	0	10745	1
Bin	(3)(17)	0	1	493	1
Bin	(3)(17)	1	0	12212	1
Bin	(3)(16)	0	1	483	1
Bin	(3)(16)	1	0	12432	1
Bin	(3)(15)	0	1	512	1
Bin	(3)(15)	1	0	12446	1
Bin	(3)(14)	0	1	510	1
Bin	(3)(14)	1	0	12719	1
Bin	(3)(13)	0	1	512	1
Bin	(3)(13)	1	0	12710	1
Bin	(3)(12)	0	1	497	1
Bin	(3)(12)	1	0	12222	1
Bin	(3)(11)	0	1	498	1
Bin	(3)(11)	1	0	12211	1
Bin	(3)(10)	0	1	514	1
Bin	(3)(10)	1	0	10673	1
Bin	(3)(9)	0	1	507	1
Bin	(3)(9)	1	0	10400	1
Bin	(3)(8)	0	1	516	1
Bin	(3)(8)	1	0	12730	1
Bin	(3)(7)	0	1	519	1
Bin	(3)(7)	1	0	12734	1
Bin	(3)(6)	0	1	491	1
Bin	(3)(6)	1	0	10873	1
Bin	(3)(5)	0	1	507	1
Bin	(3)(5)	1	0	12705	1
Bin	(3)(4)	0	1	503	1
Bin	(3)(4)	1	0	12452	1
Bin	(3)(3)	0	1	501	1
Bin	(3)(3)	1	0	12536	1
Bin	(3)(2)	0	1	496	1
Bin	(3)(2)	1	0	12211	1
Bin	(3)(1)	0	1	512	1
Bin	(3)(1)	1	0	12277	1
Bin	(3)(0)	0	1	499	1
Bin	(3)(0)	1	0	12411	1
Bin	(2)(31)	0	1	493	1
Bin	(2)(31)	1	0	9279	1
Bin	(2)(30)	0	1	492	1
Bin	(2)(30)	1	0	11650	1
Bin	(2)(29)	0	1	482	1
Bin	(2)(29)	1	0	11093	1
Bin	(2)(28)	0	1	560	1
Bin	(2)(28)	1	0	8721	1
Bin	(2)(27)	0	1	533	1
Bin	(2)(27)	1	0	9040	1
Bin	(2)(26)	0	1	552	1
Bin	(2)(26)	1	0	11401	1
Bin	(2)(25)	0	1	552	1
Bin	(2)(25)	1	0	8555	1
Bin	(2)(24)	0	1	565	1
Bin	(2)(24)	1	0	11522	1
Bin	(2)(23)	0	1	572	1
Bin	(2)(23)	1	0	8817	1
Bin	(2)(22)	0	1	537	1
Bin	(2)(22)	1	0	11410	1
Bin	(2)(21)	0	1	560	1
Bin	(2)(21)	1	0	10891	1
Bin	(2)(20)	0	1	540	1
Bin	(2)(20)	1	0	10841	1
Bin	(2)(19)	0	1	573	1
Bin	(2)(19)	1	0	9102	1
Bin	(2)(18)	0	1	574	1
Bin	(2)(18)	1	0	9586	1
Bin	(2)(17)	0	1	519	1
Bin	(2)(17)	1	0	11400	1
Bin	(2)(16)	0	1	527	1
Bin	(2)(16)	1	0	9040	1
Bin	(2)(15)	0	1	525	1
Bin	(2)(15)	1	0	10879	1
Bin	(2)(14)	0	1	529	1
Bin	(2)(14)	1	0	10961	1
Bin	(2)(13)	0	1	516	1
Bin	(2)(13)	1	0	8541	1
Bin	(2)(12)	0	1	524	1
Bin	(2)(12)	1	0	10783	1
Bin	(2)(11)	0	1	525	1
Bin	(2)(11)	1	0	8565	1
Bin	(2)(10)	0	1	506	1
Bin	(2)(10)	1	0	9436	1
Bin	(2)(9)	0	1	528	1
Bin	(2)(9)	1	0	11277	1
Bin	(2)(8)	0	1	518	1
Bin	(2)(8)	1	0	9103	1
Bin	(2)(7)	0	1	573	1
Bin	(2)(7)	1	0	11245	1
Bin	(2)(6)	0	1	554	1
Bin	(2)(6)	1	0	9522	1
Bin	(2)(5)	0	1	510	1
Bin	(2)(5)	1	0	8812	1
Bin	(2)(4)	0	1	529	1
Bin	(2)(4)	1	0	11085	1
Bin	(2)(3)	0	1	536	1
Bin	(2)(3)	1	0	10001	1
Bin	(2)(2)	0	1	549	1
Bin	(2)(2)	1	0	11435	1
Bin	(2)(1)	0	1	562	1
Bin	(2)(1)	1	0	9719	1
Bin	(2)(0)	0	1	528	1
Bin	(2)(0)	1	0	10823	1
Bin	(1)(31)	0	1	592	1
Bin	(1)(31)	1	0	7959	1
Bin	(1)(30)	0	1	585	1
Bin	(1)(30)	1	0	7300	1
Bin	(1)(29)	0	1	591	1
Bin	(1)(29)	1	0	10042	1
Bin	(1)(28)	0	1	622	1
Bin	(1)(28)	1	0	8265	1
Bin	(1)(27)	0	1	629	1
Bin	(1)(27)	1	0	9927	1
Bin	(1)(26)	0	1	625	1
Bin	(1)(26)	1	0	7354	1
Bin	(1)(25)	0	1	608	1
Bin	(1)(25)	1	0	8309	1
Bin	(1)(24)	0	1	649	1
Bin	(1)(24)	1	0	5725	1
Bin	(1)(23)	0	1	605	1
Bin	(1)(23)	1	0	6528	1
Bin	(1)(22)	0	1	634	1
Bin	(1)(22)	1	0	9384	1
Bin	(1)(21)	0	1	623	1
Bin	(1)(21)	1	0	10088	1
Bin	(1)(20)	0	1	616	1
Bin	(1)(20)	1	0	7428	1
Bin	(1)(19)	0	1	626	1
Bin	(1)(19)	1	0	8427	1
Bin	(1)(18)	0	1	624	1
Bin	(1)(18)	1	0	9260	1
Bin	(1)(17)	0	1	614	1
Bin	(1)(17)	1	0	9002	1
Bin	(1)(16)	0	1	588	1
Bin	(1)(16)	1	0	7384	1
Bin	(1)(15)	0	1	624	1
Bin	(1)(15)	1	0	7293	1
Bin	(1)(14)	0	1	601	1
Bin	(1)(14)	1	0	7994	1
Bin	(1)(13)	0	1	611	1
Bin	(1)(13)	1	0	9924	1
Bin	(1)(12)	0	1	613	1
Bin	(1)(12)	1	0	10088	1
Bin	(1)(11)	0	1	608	1
Bin	(1)(11)	1	0	8143	1
Bin	(1)(10)	0	1	615	1
Bin	(1)(10)	1	0	6513	1
Bin	(1)(9)	0	1	630	1
Bin	(1)(9)	1	0	10934	1
Bin	(1)(8)	0	1	595	1
Bin	(1)(8)	1	0	6201	1
Bin	(1)(7)	0	1	627	1
Bin	(1)(7)	1	0	10188	1
Bin	(1)(6)	0	1	628	1
Bin	(1)(6)	1	0	8546	1
Bin	(1)(5)	0	1	610	1
Bin	(1)(5)	1	0	8501	1
Bin	(1)(4)	0	1	614	1
Bin	(1)(4)	1	0	7500	1
Bin	(1)(3)	0	1	614	1
Bin	(1)(3)	1	0	10417	1
Bin	(1)(2)	0	1	616	1
Bin	(1)(2)	1	0	8999	1
Bin	(1)(1)	0	1	618	1
Bin	(1)(1)	1	0	7360	1
Bin	(1)(0)	0	1	608	1
Bin	(1)(0)	1	0	7512	1
Bin	(0)(31)	0	1	584	1
Bin	(0)(31)	1	0	8478	1
Bin	(0)(30)	0	1	577	1
Bin	(0)(30)	1	0	7555	1
Bin	(0)(29)	0	1	579	1
Bin	(0)(29)	1	0	7304	1
Bin	(0)(28)	0	1	648	1
Bin	(0)(28)	1	0	7446	1
Bin	(0)(27)	0	1	636	1
Bin	(0)(27)	1	0	7437	1
Bin	(0)(26)	0	1	655	1
Bin	(0)(26)	1	0	7747	1
Bin	(0)(25)	0	1	646	1
Bin	(0)(25)	1	0	2370	1
Bin	(0)(24)	0	1	635	1
Bin	(0)(24)	1	0	9025	1
Bin	(0)(23)	0	1	656	1
Bin	(0)(23)	1	0	7471	1
Bin	(0)(22)	0	1	637	1
Bin	(0)(22)	1	0	8691	1
Bin	(0)(21)	0	1	659	1
Bin	(0)(21)	1	0	3236	1
Bin	(0)(20)	0	1	654	1
Bin	(0)(20)	1	0	4067	1
Bin	(0)(19)	0	1	662	1
Bin	(0)(19)	1	0	5433	1
Bin	(0)(18)	0	1	663	1
Bin	(0)(18)	1	0	4537	1
Bin	(0)(17)	0	1	634	1
Bin	(0)(17)	1	0	9037	1
Bin	(0)(16)	0	1	600	1
Bin	(0)(16)	1	0	4426	1
Bin	(0)(15)	0	1	629	1
Bin	(0)(15)	1	0	6953	1
Bin	(0)(14)	0	1	625	1
Bin	(0)(14)	1	0	7333	1
Bin	(0)(13)	0	1	619	1
Bin	(0)(13)	1	0	3045	1
Bin	(0)(12)	0	1	633	1
Bin	(0)(12)	1	0	5822	1
Bin	(0)(11)	0	1	609	1
Bin	(0)(11)	1	0	8278	1
Bin	(0)(10)	0	1	624	1
Bin	(0)(10)	1	0	5889	1
Bin	(0)(9)	0	1	625	1
Bin	(0)(9)	1	0	8630	1
Bin	(0)(8)	0	1	614	1
Bin	(0)(8)	1	0	4719	1
Bin	(0)(7)	0	1	648	1
Bin	(0)(7)	1	0	9229	1
Bin	(0)(6)	0	1	646	1
Bin	(0)(6)	1	0	7671	1
Bin	(0)(5)	0	1	644	1
Bin	(0)(5)	1	0	8745	1
Bin	(0)(4)	0	1	608	1
Bin	(0)(4)	1	0	3695	1
Bin	(0)(3)	0	1	641	1
Bin	(0)(3)	1	0	8015	1
Bin	(0)(2)	0	1	630	1
Bin	(0)(2)	1	0	6029	1
Bin	(0)(1)	0	1	642	1
Bin	(0)(1)	1	0	9100	1
Bin	(0)(0)	0	1	625	1
Bin	(0)(0)	1	0	8748	1

Signal:

CONTROL_REGISTERS_CS

	From	To	Count	Threshold
Bin	0	1	19215496	1
Bin	1	0	19217097	1

Signal:

CONTROL_REGISTERS_CS_REG

	From	To	Count	Threshold
Bin	0	1	10177931	1
Bin	1	0	10179531	1

Signal:

TEST_REGISTERS_CS

	From	To	Count	Threshold
Bin	0	1	313176	1
Bin	1	0	314777	1

Signal:

TEST_REGISTERS_CS_REG

	From	To	Count	Threshold
Bin	0	1	96154	1
Bin	1	0	97755	1

Signal:

CONTROL_REGISTERS_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	5426	1
Bin	(31)	1	0	7027	1
Bin	(30)	0	1	5757	1
Bin	(30)	1	0	7358	1
Bin	(29)	0	1	5598	1
Bin	(29)	1	0	7199	1
Bin	(28)	0	1	11395	1
Bin	(28)	1	0	12996	1
Bin	(27)	0	1	12765	1
Bin	(27)	1	0	14366	1
Bin	(26)	0	1	11909	1
Bin	(26)	1	0	13510	1
Bin	(25)	0	1	19582	1
Bin	(25)	1	0	21183	1
Bin	(24)	0	1	16278	1
Bin	(24)	1	0	17879	1
Bin	(23)	0	1	20501	1
Bin	(23)	1	0	22102	1
Bin	(22)	0	1	28980	1
Bin	(22)	1	0	30580	1
Bin	(21)	0	1	17139	1
Bin	(21)	1	0	18740	1
Bin	(20)	0	1	21326	1
Bin	(20)	1	0	22927	1
Bin	(19)	0	1	22881	1
Bin	(19)	1	0	24482	1
Bin	(18)	0	1	73786	1
Bin	(18)	1	0	75387	1
Bin	(17)	0	1	62996	1
Bin	(17)	1	0	64597	1
Bin	(16)	0	1	62083	1
Bin	(16)	1	0	63675	1
Bin	(15)	0	1	31129	1
Bin	(15)	1	0	32721	1
Bin	(14)	0	1	21815	1
Bin	(14)	1	0	23416	1
Bin	(13)	0	1	25181	1
Bin	(13)	1	0	26782	1
Bin	(12)	0	1	32210	1
Bin	(12)	1	0	33811	1
Bin	(11)	0	1	32316	1
Bin	(11)	1	0	33917	1
Bin	(10)	0	1	34174	1
Bin	(10)	1	0	35775	1
Bin	(9)	0	1	36095	1
Bin	(9)	1	0	37694	1
Bin	(8)	0	1	33742	1
Bin	(8)	1	0	35342	1
Bin	(7)	0	1	58072	1
Bin	(7)	1	0	59673	1
Bin	(6)	0	1	56476	1
Bin	(6)	1	0	58068	1
Bin	(5)	0	1	65188	1
Bin	(5)	1	0	66780	1
Bin	(4)	0	1	60882	1
Bin	(4)	1	0	62481	1
Bin	(3)	0	1	75407	1
Bin	(3)	1	0	77008	1
Bin	(2)	0	1	60839	1
Bin	(2)	1	0	62439	1
Bin	(1)	0	1	37608	1
Bin	(1)	1	0	39208	1
Bin	(0)	0	1	49521	1
Bin	(0)	1	0	51121	1

Signal:

TEST_REGISTERS_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1346	1
Bin	(31)	1	0	2947	1
Bin	(30)	0	1	1292	1
Bin	(30)	1	0	2893	1
Bin	(29)	0	1	1332	1
Bin	(29)	1	0	2933	1
Bin	(28)	0	1	1452	1
Bin	(28)	1	0	3053	1
Bin	(27)	0	1	1463	1
Bin	(27)	1	0	3064	1
Bin	(26)	0	1	1445	1
Bin	(26)	1	0	3046	1
Bin	(25)	0	1	1476	1
Bin	(25)	1	0	3077	1
Bin	(24)	0	1	1518	1
Bin	(24)	1	0	3119	1
Bin	(23)	0	1	1407	1
Bin	(23)	1	0	3008	1
Bin	(22)	0	1	1359	1
Bin	(22)	1	0	2960	1
Bin	(21)	0	1	1389	1
Bin	(21)	1	0	2990	1
Bin	(20)	0	1	1466	1
Bin	(20)	1	0	3067	1
Bin	(19)	0	1	1491	1
Bin	(19)	1	0	3092	1
Bin	(18)	0	1	1478	1
Bin	(18)	1	0	3079	1
Bin	(17)	0	1	1444	1
Bin	(17)	1	0	3045	1
Bin	(16)	0	1	1491	1
Bin	(16)	1	0	3092	1
Bin	(15)	0	1	1417	1
Bin	(15)	1	0	3018	1
Bin	(14)	0	1	1345	1
Bin	(14)	1	0	2946	1
Bin	(13)	0	1	1426	1
Bin	(13)	1	0	3027	1
Bin	(12)	0	1	1501	1
Bin	(12)	1	0	3102	1
Bin	(11)	0	1	1503	1
Bin	(11)	1	0	3104	1
Bin	(10)	0	1	1454	1
Bin	(10)	1	0	3055	1
Bin	(9)	0	1	1514	1
Bin	(9)	1	0	3115	1
Bin	(8)	0	1	1538	1
Bin	(8)	1	0	3139	1
Bin	(7)	0	1	1443	1
Bin	(7)	1	0	3044	1
Bin	(6)	0	1	1389	1
Bin	(6)	1	0	2990	1
Bin	(5)	0	1	1417	1
Bin	(5)	1	0	3018	1
Bin	(4)	0	1	1479	1
Bin	(4)	1	0	3080	1
Bin	(3)	0	1	1492	1
Bin	(3)	1	0	3093	1
Bin	(2)	0	1	1494	1
Bin	(2)	1	0	3095	1
Bin	(1)	0	1	1531	1
Bin	(1)	1	0	3132	1
Bin	(0)	0	1	1539	1
Bin	(0)	1	0	3140	1

Signal:

REG_LOCK_1_ACTIVE

	From	To	Count	Threshold
Bin	0	1	2627	1
Bin	1	0	1027	1

Signal:

REG_LOCK_2_ACTIVE

	From	To	Count	Threshold
Bin	0	1	6483	1
Bin	1	0	8072	1

Signal:

SOFT_RES_D_N

	From	To	Count	Threshold
Bin	0	1	32879	1
Bin	1	0	868	1

Signal:

SOFT_RES_Q_N

	From	To	Count	Threshold
Bin	0	1	9645	1
Bin	1	0	8044	1

Signal:

RES_CORE_D_N

	From	To	Count	Threshold
Bin	0	1	8084	1
Bin	1	0	8072	1

Signal:

CONTROL_REGS_CLK_EN

	From	To	Count	Threshold
Bin	0	1	19215496	1
Bin	1	0	19217097	1

Signal:

TEST_REGS_CLK_EN

	From	To	Count	Threshold
Bin	0	1	313176	1
Bin	1	0	314777	1

Signal:

CLK_CONTROL_REGS

	From	To	Count	Threshold
Bin	0	1	31364611	1
Bin	1	0	31366211	1

Signal:

CLK_TEST_REGS

	From	To	Count	Threshold
Bin	0	1	14461333	1
Bin	1	0	14462934	1

Signal:

SCS_AND_SWR

	From	To	Count	Threshold
Bin	0	1	801022	1
Bin	1	0	802623	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

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