NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
FAULT_CONFINEMENT_FSM_INST	100.0 % (46/46)	100.0 % (38/38)	100.0 % (100/100)	100.0 % (33/33)	100.0 % (6/6)	N.A.	100.0 % (223/223)
ERR_COUNTERS_INST	100.0 % (89/89)	100.0 % (76/76)	100.0 % (536/536)	100.0 % (116/116)	N.A.	N.A.	100.0 % (817/817)
FAULT_CONFINEMENT_RULES_INST	100.0 % (18/18)	100.0 % (16/16)	100.0 % (34/34)	100.0 % (66/66)	N.A.	N.A.	100.0 % (134/134)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST	N.A.	N.A.	100.0 % (246/246)	N.A.	N.A.	N.A.	100.0 % (246/246)

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SCAN_ENABLE

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

MR_MODE_ROM

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1651	1

Port:

MR_EWL_EW_LIMIT(7)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1678	1

Port:

MR_EWL_EW_LIMIT(6)

	From	To	Count	Threshold
Bin	0	1	1686	1
Bin	1	0	86	1

Port:

MR_EWL_EW_LIMIT(5)

	From	To	Count	Threshold
Bin	0	1	1670	1
Bin	1	0	70	1

Port:

MR_EWL_EW_LIMIT(4)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1682	1

Port:

MR_EWL_EW_LIMIT(3)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1679	1

Port:

MR_EWL_EW_LIMIT(2)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1673	1

Port:

MR_EWL_EW_LIMIT(1)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1683	1

Port:

MR_EWL_EW_LIMIT(0)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1679	1

Port:

MR_ERP_ERP_LIMIT(7)

	From	To	Count	Threshold
Bin	0	1	1736	1
Bin	1	0	136	1

Port:

MR_ERP_ERP_LIMIT(6)

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1620	1

Port:

MR_ERP_ERP_LIMIT(5)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	1622	1

Port:

MR_ERP_ERP_LIMIT(4)

	From	To	Count	Threshold
Bin	0	1	27	1
Bin	1	0	1627	1

Port:

MR_ERP_ERP_LIMIT(3)

	From	To	Count	Threshold
Bin	0	1	26	1
Bin	1	0	1626	1

Port:

MR_ERP_ERP_LIMIT(2)

	From	To	Count	Threshold
Bin	0	1	27	1
Bin	1	0	1627	1

Port:

MR_ERP_ERP_LIMIT(1)

	From	To	Count	Threshold
Bin	0	1	29	1
Bin	1	0	1629	1

Port:

MR_ERP_ERP_LIMIT(0)

	From	To	Count	Threshold
Bin	0	1	21	1
Bin	1	0	1621	1

Port:

MR_CTR_PRES_CTPV(8)

	From	To	Count	Threshold
Bin	0	1	264	1
Bin	1	0	1864	1

Port:

MR_CTR_PRES_CTPV(7)

	From	To	Count	Threshold
Bin	0	1	2166	1
Bin	1	0	3766	1

Port:

MR_CTR_PRES_CTPV(6)

	From	To	Count	Threshold
Bin	0	1	683	1
Bin	1	0	2283	1

Port:

MR_CTR_PRES_CTPV(5)

	From	To	Count	Threshold
Bin	0	1	2181	1
Bin	1	0	3781	1

Port:

MR_CTR_PRES_CTPV(4)

	From	To	Count	Threshold
Bin	0	1	2332	1
Bin	1	0	3932	1

Port:

MR_CTR_PRES_CTPV(3)

	From	To	Count	Threshold
Bin	0	1	919	1
Bin	1	0	2519	1

Port:

MR_CTR_PRES_CTPV(2)

	From	To	Count	Threshold
Bin	0	1	2414	1
Bin	1	0	4014	1

Port:

MR_CTR_PRES_CTPV(1)

	From	To	Count	Threshold
Bin	0	1	1008	1
Bin	1	0	2608	1

Port:

MR_CTR_PRES_CTPV(0)

	From	To	Count	Threshold
Bin	0	1	768	1
Bin	1	0	2368	1

Port:

MR_CTR_PRES_PTX

	From	To	Count	Threshold
Bin	0	1	18698	1
Bin	1	0	42871	1

Port:

MR_CTR_PRES_PRX

	From	To	Count	Threshold
Bin	0	1	19085	1
Bin	1	0	42871	1

Port:

MR_CTR_PRES_ENORM

	From	To	Count	Threshold
Bin	0	1	5942	1
Bin	1	0	42871	1

Port:

MR_CTR_PRES_EFD

	From	To	Count	Threshold
Bin	0	1	5942	1
Bin	1	0	42871	1

Port:

MR_STATUS_EWL

	From	To	Count	Threshold
Bin	0	1	792	1
Bin	1	0	2391	1

Port:

FCS_CHANGED

	From	To	Count	Threshold
Bin	0	1	15989	1
Bin	1	0	17589	1

Port:

ERR_WARNING_LIMIT_PULSE

	From	To	Count	Threshold
Bin	0	1	3183	1
Bin	1	0	4783	1

Port:

IS_TRANSMITTER

	From	To	Count	Threshold
Bin	0	1	19892	1
Bin	1	0	21492	1

Port:

IS_RECEIVER

	From	To	Count	Threshold
Bin	0	1	30888	1
Bin	1	0	32482	1

Port:

SP_CONTROL(1)

	From	To	Count	Threshold
Bin	0	1	4206	1
Bin	1	0	5806	1

Port:

SP_CONTROL(0)

	From	To	Count	Threshold
Bin	0	1	25548	1
Bin	1	0	27148	1

Port:

SET_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	6636	1
Bin	1	0	8236	1

Port:

ERR_DETECTED

	From	To	Count	Threshold
Bin	0	1	123242	1
Bin	1	0	124842	1

Port:

ERR_CTRS_UNCHANGED

	From	To	Count	Threshold
Bin	0	1	791	1
Bin	1	0	2391	1

Port:

PRIMARY_ERR

	From	To	Count	Threshold
Bin	0	1	22658	1
Bin	1	0	24258	1

Port:

ACT_ERR_OVR_FLAG

	From	To	Count	Threshold
Bin	0	1	19607	1
Bin	1	0	21205	1

Port:

ERR_DELIM_LATE

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	1990	1

Port:

TRAN_VALID

	From	To	Count	Threshold
Bin	0	1	11098	1
Bin	1	0	12698	1

Port:

DECREMENT_REC

	From	To	Count	Threshold
Bin	0	1	14982	1
Bin	1	0	16582	1

Port:

BIT_ERR_AFTER_ACK_ERR

	From	To	Count	Threshold
Bin	0	1	8	1
Bin	1	0	1608	1

Port:

IS_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	8424	1
Bin	1	0	8415	1

Port:

IS_ERR_PASSIVE

	From	To	Count	Threshold
Bin	0	1	768	1
Bin	1	0	2368	1

Port:

IS_BUS_OFF

	From	To	Count	Threshold
Bin	0	1	8227	1
Bin	1	0	8236	1

Port:

TX_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	1849	1

Port:

TX_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	2121	1

Port:

TX_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	2088	1

Port:

TX_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	811	1
Bin	1	0	2411	1

Port:

TX_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	1931	1
Bin	1	0	3531	1

Port:

TX_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	12094	1
Bin	1	0	13694	1

Port:

TX_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	2980	1
Bin	1	0	4580	1

Port:

TX_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	3318	1
Bin	1	0	4918	1

Port:

TX_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	3517	1
Bin	1	0	5117	1

Port:

RX_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	1736	1

Port:

RX_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	1960	1

Port:

RX_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	1864	1

Port:

RX_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	1931	1

Port:

RX_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	2119	1

Port:

RX_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	2285	1

Port:

RX_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	627	1
Bin	1	0	2227	1

Port:

RX_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	1208	1
Bin	1	0	2808	1

Port:

RX_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	11221	1
Bin	1	0	12815	1

Port:

NORM_ERR_CTR(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1662	1

Port:

NORM_ERR_CTR(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1668	1

Port:

NORM_ERR_CTR(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1663	1

Port:

NORM_ERR_CTR(12)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1657	1

Port:

NORM_ERR_CTR(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1655	1

Port:

NORM_ERR_CTR(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1661	1

Port:

NORM_ERR_CTR(9)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1665	1

Port:

NORM_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1670	1

Port:

NORM_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1676	1

Port:

NORM_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1698	1

Port:

NORM_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	1759	1

Port:

NORM_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	1878	1

Port:

NORM_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	600	1
Bin	1	0	2194	1

Port:

NORM_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	1361	1
Bin	1	0	2956	1

Port:

NORM_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	3048	1
Bin	1	0	4645	1

Port:

NORM_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	11189	1
Bin	1	0	12783	1

Port:

DATA_ERR_CTR(15)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1670	1

Port:

DATA_ERR_CTR(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1660	1

Port:

DATA_ERR_CTR(13)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1661	1

Port:

DATA_ERR_CTR(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1662	1

Port:

DATA_ERR_CTR(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1657	1

Port:

DATA_ERR_CTR(10)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	1656	1

Port:

DATA_ERR_CTR(9)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1670	1

Port:

DATA_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1683	1

Port:

DATA_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1701	1

Port:

DATA_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	1735	1

Port:

DATA_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	1802	1

Port:

DATA_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	359	1
Bin	1	0	1956	1

Port:

DATA_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	679	1
Bin	1	0	2274	1

Port:

DATA_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	1295	1
Bin	1	0	2892	1

Port:

DATA_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	2524	1
Bin	1	0	4120	1

Port:

DATA_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	5478	1
Bin	1	0	7073	1

Signal:

TX_ERR_CTR_I(8)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	1849	1

Signal:

TX_ERR_CTR_I(7)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	2121	1

Signal:

TX_ERR_CTR_I(6)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	2088	1

Signal:

TX_ERR_CTR_I(5)

	From	To	Count	Threshold
Bin	0	1	811	1
Bin	1	0	2411	1

Signal:

TX_ERR_CTR_I(4)

	From	To	Count	Threshold
Bin	0	1	1931	1
Bin	1	0	3531	1

Signal:

TX_ERR_CTR_I(3)

	From	To	Count	Threshold
Bin	0	1	12094	1
Bin	1	0	13694	1

Signal:

TX_ERR_CTR_I(2)

	From	To	Count	Threshold
Bin	0	1	2980	1
Bin	1	0	4580	1

Signal:

TX_ERR_CTR_I(1)

	From	To	Count	Threshold
Bin	0	1	3318	1
Bin	1	0	4918	1

Signal:

TX_ERR_CTR_I(0)

	From	To	Count	Threshold
Bin	0	1	3517	1
Bin	1	0	5117	1

Signal:

RX_ERR_CTR_I(8)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	1736	1

Signal:

RX_ERR_CTR_I(7)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	1960	1

Signal:

RX_ERR_CTR_I(6)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	1864	1

Signal:

RX_ERR_CTR_I(5)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	1931	1

Signal:

RX_ERR_CTR_I(4)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	2119	1

Signal:

RX_ERR_CTR_I(3)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	2285	1

Signal:

RX_ERR_CTR_I(2)

	From	To	Count	Threshold
Bin	0	1	627	1
Bin	1	0	2227	1

Signal:

RX_ERR_CTR_I(1)

	From	To	Count	Threshold
Bin	0	1	1208	1
Bin	1	0	2808	1

Signal:

RX_ERR_CTR_I(0)

	From	To	Count	Threshold
Bin	0	1	11221	1
Bin	1	0	12815	1

Signal:

INC_ONE

	From	To	Count	Threshold
Bin	0	1	44878	1
Bin	1	0	46478	1

Signal:

INC_EIGHT

	From	To	Count	Threshold
Bin	0	1	79370	1
Bin	1	0	80970	1

Signal:

DEC_ONE

	From	To	Count	Threshold
Bin	0	1	26080	1
Bin	1	0	27680	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

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