NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
FAULT_CONFINEMENT_FSM_INST	100.0 % (47/47)	100.0 % (38/38)	100.0 % (100/100)	100.0 % (33/33)	100.0 % (6/6)	N.A.	100.0 % (224/224)
ERR_COUNTERS_INST	100.0 % (89/89)	100.0 % (76/76)	100.0 % (536/536)	100.0 % (116/116)	N.A.	N.A.	100.0 % (817/817)
FAULT_CONFINEMENT_RULES_INST	100.0 % (18/18)	100.0 % (16/16)	100.0 % (34/34)	98.4 % (65/66)	N.A.	N.A.	99.2 % (133/134)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

FAULT_CONFINEMENT_FSM_INST

100.0 % (47/47)

100.0 % (38/38)

100.0 % (100/100)

100.0 % (33/33)

100.0 % (6/6)

N.A.

100.0 % (224/224)

ERR_COUNTERS_INST

100.0 % (89/89)

100.0 % (76/76)

100.0 % (536/536)

100.0 % (116/116)

N.A.

100.0 % (817/817)

FAULT_CONFINEMENT_RULES_INST

100.0 % (18/18)

100.0 % (16/16)

100.0 % (34/34)

98.4 % (65/66)

N.A.

99.2 % (133/134)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST	100.0 % (2/2)	N.A.	100.0 % (246/246)	N.A.	N.A.	N.A.	100.0 % (248/248)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST

100.0 % (2/2)

N.A.

100.0 % (246/246)

N.A.

100.0 % (248/248)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 291:

291: tx_err_ctr <= tx_err_ctr_i;
Count: 33426
Threshold: 1

Signal assignment statement on line 292:

292: rx_err_ctr <= rx_err_ctr_i;
Count: 27286
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_EWL_EW_LIMIT

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_ERP_ERP_LIMIT

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_CTR_PRES_CTPV

	Element	From	To	Threshold	Excluded due to
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_CTR_PRES_PTX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_PRX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_ENORM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_EFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_TRANSMITTER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_RECEIVER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SET_ERR_ACTIVE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DETECTED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_CTRS_UNCHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PRIMARY_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ACT_ERR_OVR_FLAG

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DELIM_LATE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DECREMENT_REC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BIT_ERR_AFTER_ACK_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_STATUS_EWL

	From	To	Count	Threshold
Bin	0	1	778	1
Bin	1	0	2378	1

Port:

FCS_CHANGED

	From	To	Count	Threshold
Bin	0	1	15983	1
Bin	1	0	17584	1

Port:

ERR_WARNING_LIMIT_PULSE

	From	To	Count	Threshold
Bin	0	1	3156	1
Bin	1	0	4757	1

Port:

IS_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	8426	1
Bin	1	0	8415	1

Port:

IS_ERR_PASSIVE

	From	To	Count	Threshold
Bin	0	1	761	1
Bin	1	0	2362	1

Port:

IS_BUS_OFF

	From	To	Count	Threshold
Bin	0	1	8227	1
Bin	1	0	8238	1

Port:

TX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	246	1
Bin	(8)	1	0	1847	1
Bin	(7)	0	1	506	1
Bin	(7)	1	0	2107	1
Bin	(6)	0	1	504	1
Bin	(6)	1	0	2105	1
Bin	(5)	0	1	787	1
Bin	(5)	1	0	2388	1
Bin	(4)	0	1	1957	1
Bin	(4)	1	0	3557	1
Bin	(3)	0	1	12521	1
Bin	(3)	1	0	14122	1
Bin	(2)	0	1	2978	1
Bin	(2)	1	0	4579	1
Bin	(1)	0	1	3314	1
Bin	(1)	1	0	4915	1
Bin	(0)	0	1	3548	1
Bin	(0)	1	0	5149	1

Port:

RX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	126	1
Bin	(8)	1	0	1727	1
Bin	(7)	0	1	344	1
Bin	(7)	1	0	1945	1
Bin	(6)	0	1	262	1
Bin	(6)	1	0	1860	1
Bin	(5)	0	1	343	1
Bin	(5)	1	0	1943	1
Bin	(4)	0	1	501	1
Bin	(4)	1	0	2101	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2280	1
Bin	(2)	0	1	639	1
Bin	(2)	1	0	2240	1
Bin	(1)	0	1	1198	1
Bin	(1)	1	0	2799	1
Bin	(0)	0	1	11242	1
Bin	(0)	1	0	12836	1

Port:

NORM_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	67	1
Bin	(15)	1	0	1665	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	1663	1
Bin	(13)	0	1	66	1
Bin	(13)	1	0	1662	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	71	1
Bin	(11)	1	0	1670	1
Bin	(10)	0	1	67	1
Bin	(10)	1	0	1665	1
Bin	(9)	0	1	54	1
Bin	(9)	1	0	1654	1
Bin	(8)	0	1	71	1
Bin	(8)	1	0	1668	1
Bin	(7)	0	1	83	1
Bin	(7)	1	0	1682	1
Bin	(6)	0	1	97	1
Bin	(6)	1	0	1695	1
Bin	(5)	0	1	150	1
Bin	(5)	1	0	1747	1
Bin	(4)	0	1	271	1
Bin	(4)	1	0	1869	1
Bin	(3)	0	1	605	1
Bin	(3)	1	0	2200	1
Bin	(2)	0	1	1369	1
Bin	(2)	1	0	2967	1
Bin	(1)	0	1	3083	1
Bin	(1)	1	0	4677	1
Bin	(0)	0	1	11506	1
Bin	(0)	1	0	13100	1

Port:

DATA_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	59	1
Bin	(15)	1	0	1657	1
Bin	(14)	0	1	68	1
Bin	(14)	1	0	1666	1
Bin	(13)	0	1	70	1
Bin	(13)	1	0	1669	1
Bin	(12)	0	1	66	1
Bin	(12)	1	0	1665	1
Bin	(11)	0	1	63	1
Bin	(11)	1	0	1663	1
Bin	(10)	0	1	68	1
Bin	(10)	1	0	1666	1
Bin	(9)	0	1	77	1
Bin	(9)	1	0	1674	1
Bin	(8)	0	1	90	1
Bin	(8)	1	0	1688	1
Bin	(7)	0	1	99	1
Bin	(7)	1	0	1698	1
Bin	(6)	0	1	126	1
Bin	(6)	1	0	1723	1
Bin	(5)	0	1	212	1
Bin	(5)	1	0	1809	1
Bin	(4)	0	1	363	1
Bin	(4)	1	0	1962	1
Bin	(3)	0	1	679	1
Bin	(3)	1	0	2278	1
Bin	(2)	0	1	1288	1
Bin	(2)	1	0	2888	1
Bin	(1)	0	1	2512	1
Bin	(1)	1	0	4112	1
Bin	(0)	0	1	5598	1
Bin	(0)	1	0	7196	1

Signal:

TX_ERR_CTR_I

	Element	From	To	Count	Threshold
Bin	(8)	0	1	246	1
Bin	(8)	1	0	1847	1
Bin	(7)	0	1	506	1
Bin	(7)	1	0	2107	1
Bin	(6)	0	1	504	1
Bin	(6)	1	0	2105	1
Bin	(5)	0	1	787	1
Bin	(5)	1	0	2388	1
Bin	(4)	0	1	1957	1
Bin	(4)	1	0	3557	1
Bin	(3)	0	1	12521	1
Bin	(3)	1	0	14122	1
Bin	(2)	0	1	2978	1
Bin	(2)	1	0	4579	1
Bin	(1)	0	1	3314	1
Bin	(1)	1	0	4915	1
Bin	(0)	0	1	3548	1
Bin	(0)	1	0	5149	1

Signal:

RX_ERR_CTR_I

	Element	From	To	Count	Threshold
Bin	(8)	0	1	126	1
Bin	(8)	1	0	1727	1
Bin	(7)	0	1	344	1
Bin	(7)	1	0	1945	1
Bin	(6)	0	1	262	1
Bin	(6)	1	0	1860	1
Bin	(5)	0	1	343	1
Bin	(5)	1	0	1943	1
Bin	(4)	0	1	501	1
Bin	(4)	1	0	2101	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2280	1
Bin	(2)	0	1	639	1
Bin	(2)	1	0	2240	1
Bin	(1)	0	1	1198	1
Bin	(1)	1	0	2799	1
Bin	(0)	0	1	11242	1
Bin	(0)	1	0	12836	1

Signal:

INC_ONE

	From	To	Count	Threshold
Bin	0	1	44810	1
Bin	1	0	46411	1

Signal:

INC_EIGHT

	From	To	Count	Threshold
Bin	0	1	80681	1
Bin	1	0	82282	1

Signal:

DEC_ONE

	From	To	Count	Threshold
Bin	0	1	26093	1
Bin	1	0	27694	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 291:

Signal assignment statement on line 292:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: