NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/bit_filter.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.BIT_FILTER_B_INST.GEN_FILT_POS	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.BIT_FILTER_B_INST.GEN_FILT_POS

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

N.A.

100.0 % (10/10)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 126 to 128:

126:        valid <= '1' when (masked_input = masked_value) and (enable = '1') 
127:                     else 
128:                 '0';

Count: 2742
Threshold: 1

Signal assignment statement on line 126:

126: valid <= '1' when (masked_input = masked_value) and (enable = '1')
Count: 557
Threshold: 1

Signal assignment statement on line 128:

128: '0';
Count: 2185
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 126:

126: valid <= '1' when (masked_input = masked_value) and (enable = '1')

	Evaluated to	Count	Threshold
Bin	True	557	1
Bin	False	2185	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 126:

 (masked_input = masked_value) and (enable = '1') 
  <-----------LHS----------->       <---RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	515	1
Bin	True	False	777	1
Bin	True	True	557	1

"=" expression on line 126:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	1670	1
Bin	True	1072	1