File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/bit_filter.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Bit Filter for CAN identifiers.
71: --
72: -- Purpose:
73: -- Filters out CAN identifier based on bit mask.
74: --------------------------------------------------------------------------------
75:
76: Library ieee;
77: use ieee.std_logic_1164.all;
78: use ieee.numeric_std.ALL;
79:
80: Library ctu_can_fd_rtl;
81: use ctu_can_fd_rtl.can_constants_pkg.all;
82: use ctu_can_fd_rtl.can_types_pkg.all;
83:
84: use ctu_can_fd_rtl.CAN_FD_register_map.all;
85: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
86:
87: entity bit_filter is
88: generic(
89: -- Filter width
90: G_WIDTH : natural;
91:
92: -- Filter presence
93: G_IS_PRESENT : boolean
94: );
95: port(
96: -- Filter mask
97: filter_mask : in std_logic_vector(G_WIDTH - 1 downto 0);
98:
99: -- Filter value
100: filter_value : in std_logic_vector(G_WIDTH - 1 downto 0);
101:
102: -- Filter input
103: filter_input : in std_logic_vector(G_WIDTH - 1 downto 0);
104:
105: -- Filter enable (output is stuck at zero when disabled)
106: enable : in std_logic;
107:
108: -- '1' when Filter input passes the filter
109: valid : out std_logic
110: );
111: end entity;
112:
113: architecture rtl of bit_filter is
114:
115: signal masked_input : std_logic_vector(G_WIDTH - 1 downto 0);
116: signal masked_value : std_logic_vector(G_WIDTH - 1 downto 0);
117:
118: begin
119:
120: masked_input <= filter_input and filter_mask;
121: masked_value <= filter_value and filter_mask;
122:
123: -- Filter A input frame type filtering
124: gen_filt_pos : if (G_IS_PRESENT = true) generate
125: valid <= '1' when (masked_input = masked_value) and (enable = '1')
126: else
127: '0';
128: end generate;
129:
130: gen_filt_neg : if (G_IS_PRESENT = false) generate
131: valid <= '0';
132: end generate;
133:
134: end architecture;