NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.RX_SHIFT_RES_REG_INST.MUX2_RES_TST_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/mux2.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.RX_SHIFT_RES_REG_INST.MUX2_RES_TST_INST	100.0 % (3/3)	100.0 % (2/2)	100.0 % (8/8)	N.A.	N.A.	N.A.	100.0 % (13/13)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement:

106:    with sel select z <= 
107:        a when '0', 
108:        b when others;

Count: 146087
Threshold: 1

Signal assignment statement:

107: a when '0',
Count: 144482
Threshold: 1

Signal assignment statement:

108: b when others;
Count: 1605
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice:

107: a when '0',

	Choice of	Count	Threshold
Bin	`'0'`	144482	1

"case" / "with" / "select" choice:

108: b when others;

	Choice of	Count	Threshold
Bin	`others`	1605	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

A

	From	To	Count	Threshold
Bin	0	1	63366	1
Bin	1	0	63357	1

Port:

B

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SEL

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

Z

	From	To	Count	Threshold
Bin	0	1	63366	1
Bin	1	0	63357	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.RX_SHIFT_RES_REG_INST.MUX2_RES_TST_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/mux2.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: