NVC code coverage report

NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(5).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BYTE_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
RAM_RST_FALSE_GEN	100.0 % (4/4)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (10/10)
SYNC_READ_GEN	100.0 % (2/2)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(5).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST	100.0 % (1/1)	N.A.	100.0 % (1578/1578)	N.A.	N.A.	N.A.	100.0 % (1579/1579)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

191: int_read_data <= ram_memory(to_integer(unsigned(addr_B)));
Count: 32921
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	327767	1
Bin	1	0	327932	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	723	1
Bin	1	0	723	1

Port:

ADDR_A(4)

	From	To	Count	Threshold
Bin	0	1	101815	1
Bin	1	0	4952869	1

Port:

ADDR_A(3)

	From	To	Count	Threshold
Bin	0	1	128240	1
Bin	1	0	4926438	1

Port:

ADDR_A(2)

	From	To	Count	Threshold
Bin	0	1	109940	1
Bin	1	0	4944870	1

Port:

ADDR_A(1)

	From	To	Count	Threshold
Bin	0	1	4814597	1
Bin	1	0	240509	1

Port:

ADDR_A(0)

	From	To	Count	Threshold
Bin	0	1	3622610	1
Bin	1	0	1433101	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	11588	1
Bin	1	0	11783	1

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	16688	1
Bin	1	0	317963	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	18734	1
Bin	1	0	315909	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	16349	1
Bin	1	0	318304	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	24925	1
Bin	1	0	309722	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	19047	1
Bin	1	0	315606	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	21375	1
Bin	1	0	313276	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	26300	1
Bin	1	0	308365	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	21218	1
Bin	1	0	313443	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	20290	1
Bin	1	0	314363	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	23788	1
Bin	1	0	310869	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	22528	1
Bin	1	0	312113	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	20877	1
Bin	1	0	313780	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	34377	1
Bin	1	0	300284	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	42018	1
Bin	1	0	292654	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	39250	1
Bin	1	0	295410	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	83001	1
Bin	1	0	251665	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	18388	1
Bin	1	0	316271	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	21792	1
Bin	1	0	312859	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	19082	1
Bin	1	0	315581	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	22223	1
Bin	1	0	312436	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	40263	1
Bin	1	0	294400	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	41585	1
Bin	1	0	293068	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	49592	1
Bin	1	0	285067	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	50752	1
Bin	1	0	283903	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	44511	1
Bin	1	0	290144	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	42465	1
Bin	1	0	292194	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	44880	1
Bin	1	0	289787	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	48991	1
Bin	1	0	285650	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	52089	1
Bin	1	0	282574	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	54953	1
Bin	1	0	279712	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	94881	1
Bin	1	0	239773	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	81944	1
Bin	1	0	252736	1

Port:

BE(3)

	From	To	Count	Threshold
Bin	0	1	5053365	1
Bin	1	0	7925	1

Port:

BE(2)

	From	To	Count	Threshold
Bin	0	1	5053445	1
Bin	1	0	7845	1

Port:

BE(1)

	From	To	Count	Threshold
Bin	0	1	5039204	1
Bin	1	0	22086	1

Port:

BE(0)

	From	To	Count	Threshold
Bin	0	1	5039488	1
Bin	1	0	21802	1

Port:

ADDR_B(4)

	From	To	Count	Threshold
Bin	0	1	3249	1
Bin	1	0	3414	1

Port:

ADDR_B(3)

	From	To	Count	Threshold
Bin	0	1	166	1
Bin	1	0	331	1

Port:

ADDR_B(2)

	From	To	Count	Threshold
Bin	0	1	5045	1
Bin	1	0	5210	1

Port:

ADDR_B(1)

	From	To	Count	Threshold
Bin	0	1	4011	1
Bin	1	0	4011	1

Port:

ADDR_B(0)

	From	To	Count	Threshold
Bin	0	1	11138	1
Bin	1	0	11303	1

Port:

DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	351	1
Bin	1	0	506	1

Port:

DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	384	1
Bin	1	0	539	1

Port:

DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	304	1
Bin	1	0	459	1

Port:

DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	740	1
Bin	1	0	889	1

Port:

DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	766	1
Bin	1	0	915	1

Port:

DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	581	1
Bin	1	0	733	1

Port:

DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	845	1
Bin	1	0	997	1

Port:

DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	892	1
Bin	1	0	1042	1

Port:

DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	787	1
Bin	1	0	936	1

Port:

DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	667	1
Bin	1	0	818	1

Port:

DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	798	1
Bin	1	0	950	1

Port:

DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	606	1
Bin	1	0	755	1

Port:

DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	933	1
Bin	1	0	1082	1

Port:

DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	774	1
Bin	1	0	923	1

Port:

DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	675	1

Port:

DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	429	1
Bin	1	0	581	1

Port:

DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	717	1
Bin	1	0	869	1

Port:

DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	561	1
Bin	1	0	714	1

Port:

DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	652	1
Bin	1	0	805	1

Port:

DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	507	1
Bin	1	0	660	1

Port:

DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	503	1
Bin	1	0	654	1

Port:

DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	468	1
Bin	1	0	619	1

Port:

DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	972	1
Bin	1	0	1120	1

Port:

DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	599	1
Bin	1	0	750	1

Port:

DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	948	1
Bin	1	0	1090	1

Port:

DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	923	1
Bin	1	0	1073	1

Port:

DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	844	1
Bin	1	0	994	1

Port:

DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	493	1
Bin	1	0	644	1

Port:

DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	709	1
Bin	1	0	859	1

Port:

DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	878	1
Bin	1	0	1026	1

Port:

DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	938	1
Bin	1	0	1088	1

Port:

DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	775	1
Bin	1	0	921	1

Signal:

RAM_MEMORY(0)(31)

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	4000	1

Signal:

RAM_MEMORY(0)(30)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4020	1

Signal:

RAM_MEMORY(0)(29)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4019	1

Signal:

RAM_MEMORY(0)(28)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4040	1

Signal:

RAM_MEMORY(0)(27)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4000	1

Signal:

RAM_MEMORY(0)(26)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4020	1

Signal:

RAM_MEMORY(0)(25)

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	4000	1

Signal:

RAM_MEMORY(0)(24)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4040	1

Signal:

RAM_MEMORY(0)(23)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	4015	1

Signal:

RAM_MEMORY(0)(22)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	4019	1

Signal:

RAM_MEMORY(0)(21)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4014	1

Signal:

RAM_MEMORY(0)(20)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4035	1

Signal:

RAM_MEMORY(0)(19)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	3994	1

Signal:

RAM_MEMORY(0)(18)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4035	1

Signal:

RAM_MEMORY(0)(17)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3995	1

Signal:

RAM_MEMORY(0)(16)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4015	1

Signal:

RAM_MEMORY(0)(15)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3559	1

Signal:

RAM_MEMORY(0)(14)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	3558	1

Signal:

RAM_MEMORY(0)(13)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3578	1

Signal:

RAM_MEMORY(0)(12)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	3585	1

Signal:

RAM_MEMORY(0)(11)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3579	1

Signal:

RAM_MEMORY(0)(10)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3579	1

Signal:

RAM_MEMORY(0)(9)

	From	To	Count	Threshold
Bin	0	1	222	1
Bin	1	0	3815	1

Signal:

RAM_MEMORY(0)(8)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	3578	1

Signal:

RAM_MEMORY(0)(7)

	From	To	Count	Threshold
Bin	0	1	306	1
Bin	1	0	3471	1

Signal:

RAM_MEMORY(0)(6)

	From	To	Count	Threshold
Bin	0	1	226	1
Bin	1	0	3428	1

Signal:

RAM_MEMORY(0)(5)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	3376	1

Signal:

RAM_MEMORY(0)(4)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3303	1

Signal:

RAM_MEMORY(0)(3)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	3406	1

Signal:

RAM_MEMORY(0)(2)

	From	To	Count	Threshold
Bin	0	1	228	1
Bin	1	0	3446	1

Signal:

RAM_MEMORY(0)(1)

	From	To	Count	Threshold
Bin	0	1	211	1
Bin	1	0	3428	1

Signal:

RAM_MEMORY(0)(0)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	3421	1

Signal:

RAM_MEMORY(1)(31)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3191	1

Signal:

RAM_MEMORY(1)(30)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3191	1

Signal:

RAM_MEMORY(1)(29)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3191	1

Signal:

RAM_MEMORY(1)(28)

	From	To	Count	Threshold
Bin	0	1	262	1
Bin	1	0	3334	1

Signal:

RAM_MEMORY(1)(27)

	From	To	Count	Threshold
Bin	0	1	273	1
Bin	1	0	3355	1

Signal:

RAM_MEMORY(1)(26)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	3368	1

Signal:

RAM_MEMORY(1)(25)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	3348	1

Signal:

RAM_MEMORY(1)(24)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	3366	1

Signal:

RAM_MEMORY(1)(23)

	From	To	Count	Threshold
Bin	0	1	251	1
Bin	1	0	3342	1

Signal:

RAM_MEMORY(1)(22)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	3335	1

Signal:

RAM_MEMORY(1)(21)

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	3336	1

Signal:

RAM_MEMORY(1)(20)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	3350	1

Signal:

RAM_MEMORY(1)(19)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	3353	1

Signal:

RAM_MEMORY(1)(18)

	From	To	Count	Threshold
Bin	0	1	272	1
Bin	1	0	3361	1

Signal:

RAM_MEMORY(1)(17)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	3266	1

Signal:

RAM_MEMORY(1)(16)

	From	To	Count	Threshold
Bin	0	1	171	1
Bin	1	0	3277	1

Signal:

RAM_MEMORY(1)(15)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	3497	1

Signal:

RAM_MEMORY(1)(14)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	3584	1

Signal:

RAM_MEMORY(1)(13)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	3456	1

Signal:

RAM_MEMORY(1)(12)

	From	To	Count	Threshold
Bin	0	1	143	1
Bin	1	0	3580	1

Signal:

RAM_MEMORY(1)(11)

	From	To	Count	Threshold
Bin	0	1	150	1
Bin	1	0	3472	1

Signal:

RAM_MEMORY(1)(10)

	From	To	Count	Threshold
Bin	0	1	127	1
Bin	1	0	3510	1

Signal:

RAM_MEMORY(1)(9)

	From	To	Count	Threshold
Bin	0	1	183	1
Bin	1	0	3600	1

Signal:

RAM_MEMORY(1)(8)

	From	To	Count	Threshold
Bin	0	1	149	1
Bin	1	0	3519	1

Signal:

RAM_MEMORY(1)(7)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	3535	1

Signal:

RAM_MEMORY(1)(6)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	3518	1

Signal:

RAM_MEMORY(1)(5)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	3521	1

Signal:

RAM_MEMORY(1)(4)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	3481	1

Signal:

RAM_MEMORY(1)(3)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	3555	1

Signal:

RAM_MEMORY(1)(2)

	From	To	Count	Threshold
Bin	0	1	172	1
Bin	1	0	3548	1

Signal:

RAM_MEMORY(1)(1)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	3484	1

Signal:

RAM_MEMORY(1)(0)

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	3535	1

Signal:

RAM_MEMORY(2)(31)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3699	1

Signal:

RAM_MEMORY(2)(30)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3691	1

Signal:

RAM_MEMORY(2)(29)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3691	1

Signal:

RAM_MEMORY(2)(28)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3681	1

Signal:

RAM_MEMORY(2)(27)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3699	1

Signal:

RAM_MEMORY(2)(26)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3691	1

Signal:

RAM_MEMORY(2)(25)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3681	1

Signal:

RAM_MEMORY(2)(24)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3709	1

Signal:

RAM_MEMORY(2)(23)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	3708	1

Signal:

RAM_MEMORY(2)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(21)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3680	1

Signal:

RAM_MEMORY(2)(20)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(19)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(17)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3690	1

Signal:

RAM_MEMORY(2)(16)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3690	1

Signal:

RAM_MEMORY(2)(15)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3662	1

Signal:

RAM_MEMORY(2)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3662	1

Signal:

RAM_MEMORY(2)(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3684	1

Signal:

RAM_MEMORY(2)(12)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3684	1

Signal:

RAM_MEMORY(2)(11)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3699	1

Signal:

RAM_MEMORY(2)(10)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3666	1

Signal:

RAM_MEMORY(2)(9)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3662	1

Signal:

RAM_MEMORY(2)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3680	1

Signal:

RAM_MEMORY(2)(7)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3628	1

Signal:

RAM_MEMORY(2)(6)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3628	1

Signal:

RAM_MEMORY(2)(5)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	3612	1

Signal:

RAM_MEMORY(2)(4)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3608	1

Signal:

RAM_MEMORY(2)(3)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	3619	1

Signal:

RAM_MEMORY(2)(2)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	3687	1

Signal:

RAM_MEMORY(2)(1)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	3630	1

Signal:

RAM_MEMORY(2)(0)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	3630	1

Signal:

RAM_MEMORY(3)(31)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3546	1

Signal:

RAM_MEMORY(3)(30)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3532	1

Signal:

RAM_MEMORY(3)(29)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3546	1

Signal:

RAM_MEMORY(3)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(27)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3546	1

Signal:

RAM_MEMORY(3)(26)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3532	1

Signal:

RAM_MEMORY(3)(25)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	3550	1

Signal:

RAM_MEMORY(3)(24)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(23)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3549	1

Signal:

RAM_MEMORY(3)(22)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3532	1

Signal:

RAM_MEMORY(3)(21)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3546	1

Signal:

RAM_MEMORY(3)(20)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(19)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	3550	1

Signal:

RAM_MEMORY(3)(18)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3529	1

Signal:

RAM_MEMORY(3)(17)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(16)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3546	1

Signal:

RAM_MEMORY(3)(15)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(14)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3546	1

Signal:

RAM_MEMORY(3)(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3549	1

Signal:

RAM_MEMORY(3)(12)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3532	1

Signal:

RAM_MEMORY(3)(11)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(10)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3529	1

Signal:

RAM_MEMORY(3)(9)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3549	1

Signal:

RAM_MEMORY(3)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(7)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3487	1

Signal:

RAM_MEMORY(3)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3487	1

Signal:

RAM_MEMORY(3)(5)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3474	1

Signal:

RAM_MEMORY(3)(4)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	3544	1

Signal:

RAM_MEMORY(3)(3)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	3492	1

Signal:

RAM_MEMORY(3)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3487	1

Signal:

RAM_MEMORY(3)(1)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3471	1

Signal:

RAM_MEMORY(3)(0)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3471	1

Signal:

RAM_MEMORY(4)(31)

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	3005	1

Signal:

RAM_MEMORY(4)(30)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	3008	1

Signal:

RAM_MEMORY(4)(29)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	2955	1

Signal:

RAM_MEMORY(4)(28)

	From	To	Count	Threshold
Bin	0	1	192	1
Bin	1	0	3002	1

Signal:

RAM_MEMORY(4)(27)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	3009	1

Signal:

RAM_MEMORY(4)(26)

	From	To	Count	Threshold
Bin	0	1	161	1
Bin	1	0	2983	1

Signal:

RAM_MEMORY(4)(25)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	3011	1

Signal:

RAM_MEMORY(4)(24)

	From	To	Count	Threshold
Bin	0	1	190	1
Bin	1	0	3040	1

Signal:

RAM_MEMORY(4)(23)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	2989	1

Signal:

RAM_MEMORY(4)(22)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	2995	1

Signal:

RAM_MEMORY(4)(21)

	From	To	Count	Threshold
Bin	0	1	209	1
Bin	1	0	2961	1

Signal:

RAM_MEMORY(4)(20)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	2982	1

Signal:

RAM_MEMORY(4)(19)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	3027	1

Signal:

RAM_MEMORY(4)(18)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	3032	1

Signal:

RAM_MEMORY(4)(17)

	From	To	Count	Threshold
Bin	0	1	207	1
Bin	1	0	2984	1

Signal:

RAM_MEMORY(4)(16)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2922	1

Signal:

RAM_MEMORY(4)(15)

	From	To	Count	Threshold
Bin	0	1	226	1
Bin	1	0	2980	1

Signal:

RAM_MEMORY(4)(14)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	3011	1

Signal:

RAM_MEMORY(4)(13)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	2975	1

Signal:

RAM_MEMORY(4)(12)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	3010	1

Signal:

RAM_MEMORY(4)(11)

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	2964	1

Signal:

RAM_MEMORY(4)(10)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	2975	1

Signal:

RAM_MEMORY(4)(9)

	From	To	Count	Threshold
Bin	0	1	203	1
Bin	1	0	3016	1

Signal:

RAM_MEMORY(4)(8)

	From	To	Count	Threshold
Bin	0	1	186	1
Bin	1	0	3001	1

Signal:

RAM_MEMORY(4)(7)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	2951	1

Signal:

RAM_MEMORY(4)(6)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	2958	1

Signal:

RAM_MEMORY(4)(5)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	2952	1

Signal:

RAM_MEMORY(4)(4)

	From	To	Count	Threshold
Bin	0	1	190	1
Bin	1	0	2942	1

Signal:

RAM_MEMORY(4)(3)

	From	To	Count	Threshold
Bin	0	1	203	1
Bin	1	0	2947	1

Signal:

RAM_MEMORY(4)(2)

	From	To	Count	Threshold
Bin	0	1	198	1
Bin	1	0	2960	1

Signal:

RAM_MEMORY(4)(1)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	2948	1

Signal:

RAM_MEMORY(4)(0)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	2939	1

Signal:

RAM_MEMORY(5)(31)

	From	To	Count	Threshold
Bin	0	1	173	1
Bin	1	0	2938	1

Signal:

RAM_MEMORY(5)(30)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	3021	1

Signal:

RAM_MEMORY(5)(29)

	From	To	Count	Threshold
Bin	0	1	186	1
Bin	1	0	3036	1

Signal:

RAM_MEMORY(5)(28)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2938	1

Signal:

RAM_MEMORY(5)(27)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	2969	1

Signal:

RAM_MEMORY(5)(26)

	From	To	Count	Threshold
Bin	0	1	124	1
Bin	1	0	2928	1

Signal:

RAM_MEMORY(5)(25)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	2980	1

Signal:

RAM_MEMORY(5)(24)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2917	1

Signal:

RAM_MEMORY(5)(23)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	2990	1

Signal:

RAM_MEMORY(5)(22)

	From	To	Count	Threshold
Bin	0	1	162	1
Bin	1	0	2943	1

Signal:

RAM_MEMORY(5)(21)

	From	To	Count	Threshold
Bin	0	1	165	1
Bin	1	0	2955	1

Signal:

RAM_MEMORY(5)(20)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2907	1

Signal:

RAM_MEMORY(5)(19)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	2913	1

Signal:

RAM_MEMORY(5)(18)

	From	To	Count	Threshold
Bin	0	1	134	1
Bin	1	0	2982	1

Signal:

RAM_MEMORY(5)(17)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	2925	1

Signal:

RAM_MEMORY(5)(16)

	From	To	Count	Threshold
Bin	0	1	141	1
Bin	1	0	2942	1

Signal:

RAM_MEMORY(5)(15)

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	2828	1

Signal:

RAM_MEMORY(5)(14)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	2785	1

Signal:

RAM_MEMORY(5)(13)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	2830	1

Signal:

RAM_MEMORY(5)(12)

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	2922	1

Signal:

RAM_MEMORY(5)(11)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2838	1

Signal:

RAM_MEMORY(5)(10)

	From	To	Count	Threshold
Bin	0	1	144	1
Bin	1	0	2841	1

Signal:

RAM_MEMORY(5)(9)

	From	To	Count	Threshold
Bin	0	1	172	1
Bin	1	0	2890	1

Signal:

RAM_MEMORY(5)(8)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	2906	1

Signal:

RAM_MEMORY(5)(7)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	2819	1

Signal:

RAM_MEMORY(5)(6)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	2827	1

Signal:

RAM_MEMORY(5)(5)

	From	To	Count	Threshold
Bin	0	1	183	1
Bin	1	0	2926	1

Signal:

RAM_MEMORY(5)(4)

	From	To	Count	Threshold
Bin	0	1	174	1
Bin	1	0	2834	1

Signal:

RAM_MEMORY(5)(3)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2887	1

Signal:

RAM_MEMORY(5)(2)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	2821	1

Signal:

RAM_MEMORY(5)(1)

	From	To	Count	Threshold
Bin	0	1	162	1
Bin	1	0	2845	1

Signal:

RAM_MEMORY(5)(0)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	2889	1

Signal:

RAM_MEMORY(6)(31)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2943	1

Signal:

RAM_MEMORY(6)(30)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	2947	1

Signal:

RAM_MEMORY(6)(29)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2943	1

Signal:

RAM_MEMORY(6)(28)

	From	To	Count	Threshold
Bin	0	1	149	1
Bin	1	0	2957	1

Signal:

RAM_MEMORY(6)(27)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2938	1

Signal:

RAM_MEMORY(6)(26)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2890	1

Signal:

RAM_MEMORY(6)(25)

	From	To	Count	Threshold
Bin	0	1	146	1
Bin	1	0	2910	1

Signal:

RAM_MEMORY(6)(24)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2899	1

Signal:

RAM_MEMORY(6)(23)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	2890	1

Signal:

RAM_MEMORY(6)(22)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2900	1

Signal:

RAM_MEMORY(6)(21)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	2899	1

Signal:

RAM_MEMORY(6)(20)

	From	To	Count	Threshold
Bin	0	1	155	1
Bin	1	0	2929	1

Signal:

RAM_MEMORY(6)(19)

	From	To	Count	Threshold
Bin	0	1	185	1
Bin	1	0	2904	1

Signal:

RAM_MEMORY(6)(18)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2890	1

Signal:

RAM_MEMORY(6)(17)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	2910	1

Signal:

RAM_MEMORY(6)(16)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2924	1

Signal:

RAM_MEMORY(6)(15)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2895	1

Signal:

RAM_MEMORY(6)(14)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2952	1

Signal:

RAM_MEMORY(6)(13)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2938	1

Signal:

RAM_MEMORY(6)(12)

	From	To	Count	Threshold
Bin	0	1	153	1
Bin	1	0	2957	1

Signal:

RAM_MEMORY(6)(11)

	From	To	Count	Threshold
Bin	0	1	149	1
Bin	1	0	2928	1

Signal:

RAM_MEMORY(6)(10)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2914	1

Signal:

RAM_MEMORY(6)(9)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2881	1

Signal:

RAM_MEMORY(6)(8)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2943	1

Signal:

RAM_MEMORY(6)(7)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	2924	1

Signal:

RAM_MEMORY(6)(6)

	From	To	Count	Threshold
Bin	0	1	155	1
Bin	1	0	2886	1

Signal:

RAM_MEMORY(6)(5)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	2938	1

Signal:

RAM_MEMORY(6)(4)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2910	1

Signal:

RAM_MEMORY(6)(3)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2915	1

Signal:

RAM_MEMORY(6)(2)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2938	1

Signal:

RAM_MEMORY(6)(1)

	From	To	Count	Threshold
Bin	0	1	156	1
Bin	1	0	2915	1

Signal:

RAM_MEMORY(6)(0)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	2929	1

Signal:

RAM_MEMORY(7)(31)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	2737	1

Signal:

RAM_MEMORY(7)(30)

	From	To	Count	Threshold
Bin	0	1	144	1
Bin	1	0	2746	1

Signal:

RAM_MEMORY(7)(29)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2755	1

Signal:

RAM_MEMORY(7)(28)

	From	To	Count	Threshold
Bin	0	1	118	1
Bin	1	0	2741	1

Signal:

RAM_MEMORY(7)(27)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	2793	1

Signal:

RAM_MEMORY(7)(26)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2797	1

Signal:

RAM_MEMORY(7)(25)

	From	To	Count	Threshold
Bin	0	1	146	1
Bin	1	0	2741	1

Signal:

RAM_MEMORY(7)(24)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2779	1

Signal:

RAM_MEMORY(7)(23)

	From	To	Count	Threshold
Bin	0	1	147	1
Bin	1	0	2770	1

Signal:

RAM_MEMORY(7)(22)

	From	To	Count	Threshold
Bin	0	1	155	1
Bin	1	0	2741	1

Signal:

RAM_MEMORY(7)(21)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	2741	1

Signal:

RAM_MEMORY(7)(20)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2728	1

Signal:

RAM_MEMORY(7)(19)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	2793	1

Signal:

RAM_MEMORY(7)(18)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2741	1

Signal:

RAM_MEMORY(7)(17)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2755	1

Signal:

RAM_MEMORY(7)(16)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2779	1

Signal:

RAM_MEMORY(7)(15)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	2746	1

Signal:

RAM_MEMORY(7)(14)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2810	1

Signal:

RAM_MEMORY(7)(13)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	2755	1

Signal:

RAM_MEMORY(7)(12)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2793	1

Signal:

RAM_MEMORY(7)(11)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2797	1

Signal:

RAM_MEMORY(7)(10)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	2724	1

Signal:

RAM_MEMORY(7)(9)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2724	1

Signal:

RAM_MEMORY(7)(8)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	2737	1

Signal:

RAM_MEMORY(7)(7)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2779	1

Signal:

RAM_MEMORY(7)(6)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2742	1

Signal:

RAM_MEMORY(7)(5)

	From	To	Count	Threshold
Bin	0	1	169	1
Bin	1	0	2783	1

Signal:

RAM_MEMORY(7)(4)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	2784	1

Signal:

RAM_MEMORY(7)(3)

	From	To	Count	Threshold
Bin	0	1	124	1
Bin	1	0	2755	1

Signal:

RAM_MEMORY(7)(2)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	2783	1

Signal:

RAM_MEMORY(7)(1)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	2741	1

Signal:

RAM_MEMORY(7)(0)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2728	1

Signal:

RAM_MEMORY(8)(31)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2605	1

Signal:

RAM_MEMORY(8)(30)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2593	1

Signal:

RAM_MEMORY(8)(29)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	2619	1

Signal:

RAM_MEMORY(8)(28)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2631	1

Signal:

RAM_MEMORY(8)(27)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2593	1

Signal:

RAM_MEMORY(8)(26)

	From	To	Count	Threshold
Bin	0	1	118	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(25)

	From	To	Count	Threshold
Bin	0	1	133	1
Bin	1	0	2649	1

Signal:

RAM_MEMORY(8)(24)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	2675	1

Signal:

RAM_MEMORY(8)(23)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(22)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2649	1

Signal:

RAM_MEMORY(8)(21)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	2593	1

Signal:

RAM_MEMORY(8)(20)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2660	1

Signal:

RAM_MEMORY(8)(19)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	2634	1

Signal:

RAM_MEMORY(8)(18)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	2649	1

Signal:

RAM_MEMORY(8)(17)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2631	1

Signal:

RAM_MEMORY(8)(16)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(15)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2634	1

Signal:

RAM_MEMORY(8)(14)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(13)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	2596	1

Signal:

RAM_MEMORY(8)(12)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	2672	1

Signal:

RAM_MEMORY(8)(11)

	From	To	Count	Threshold
Bin	0	1	171	1
Bin	1	0	2675	1

Signal:

RAM_MEMORY(8)(10)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2605	1

Signal:

RAM_MEMORY(8)(9)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	2649	1

Signal:

RAM_MEMORY(8)(8)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2634	1

Signal:

RAM_MEMORY(8)(7)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2605	1

Signal:

RAM_MEMORY(8)(6)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2605	1

Signal:

RAM_MEMORY(8)(5)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	2593	1

Signal:

RAM_MEMORY(8)(4)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	2622	1

Signal:

RAM_MEMORY(8)(3)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	2622	1

Signal:

RAM_MEMORY(8)(2)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(1)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2646	1

Signal:

RAM_MEMORY(8)(0)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	2649	1

Signal:

RAM_MEMORY(9)(31)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2488	1

Signal:

RAM_MEMORY(9)(30)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2457	1

Signal:

RAM_MEMORY(9)(29)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2497	1

Signal:

RAM_MEMORY(9)(28)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2488	1

Signal:

RAM_MEMORY(9)(27)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2486	1

Signal:

RAM_MEMORY(9)(26)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2486	1

Signal:

RAM_MEMORY(9)(25)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	2457	1

Signal:

RAM_MEMORY(9)(24)

	From	To	Count	Threshold
Bin	0	1	153	1
Bin	1	0	2499	1

Signal:

RAM_MEMORY(9)(23)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2448	1

Signal:

RAM_MEMORY(9)(22)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2499	1

Signal:

RAM_MEMORY(9)(21)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2497	1

Signal:

RAM_MEMORY(9)(20)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2446	1

Signal:

RAM_MEMORY(9)(19)

	From	To	Count	Threshold
Bin	0	1	149	1
Bin	1	0	2499	1

Signal:

RAM_MEMORY(9)(18)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2524	1

Signal:

RAM_MEMORY(9)(17)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	2459	1

Signal:

RAM_MEMORY(9)(16)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2471	1

Signal:

RAM_MEMORY(9)(15)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2486	1

Signal:

RAM_MEMORY(9)(14)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2457	1

Signal:

RAM_MEMORY(9)(13)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	2457	1

Signal:

RAM_MEMORY(9)(12)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2486	1

Signal:

RAM_MEMORY(9)(11)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2448	1

Signal:

RAM_MEMORY(9)(10)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	2488	1

Signal:

RAM_MEMORY(9)(9)

	From	To	Count	Threshold
Bin	0	1	167	1
Bin	1	0	2499	1

Signal:

RAM_MEMORY(9)(8)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2448	1

Signal:

RAM_MEMORY(9)(7)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2497	1

Signal:

RAM_MEMORY(9)(6)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	2486	1

Signal:

RAM_MEMORY(9)(5)

	From	To	Count	Threshold
Bin	0	1	146	1
Bin	1	0	2488	1

Signal:

RAM_MEMORY(9)(4)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2448	1

Signal:

RAM_MEMORY(9)(3)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	2459	1

Signal:

RAM_MEMORY(9)(2)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2457	1

Signal:

RAM_MEMORY(9)(1)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2457	1

Signal:

RAM_MEMORY(9)(0)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2486	1

Signal:

RAM_MEMORY(10)(31)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(30)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2367	1

Signal:

RAM_MEMORY(10)(29)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(28)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	2328	1

Signal:

RAM_MEMORY(10)(27)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2367	1

Signal:

RAM_MEMORY(10)(26)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2367	1

Signal:

RAM_MEMORY(10)(25)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	2328	1

Signal:

RAM_MEMORY(10)(24)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2377	1

Signal:

RAM_MEMORY(10)(23)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2367	1

Signal:

RAM_MEMORY(10)(22)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	2391	1

Signal:

RAM_MEMORY(10)(21)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2377	1

Signal:

RAM_MEMORY(10)(20)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2362	1

Signal:

RAM_MEMORY(10)(19)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2328	1

Signal:

RAM_MEMORY(10)(18)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	2401	1

Signal:

RAM_MEMORY(10)(17)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(16)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(15)

	From	To	Count	Threshold
Bin	0	1	126	1
Bin	1	0	2401	1

Signal:

RAM_MEMORY(10)(14)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	2367	1

Signal:

RAM_MEMORY(10)(13)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2367	1

Signal:

RAM_MEMORY(10)(12)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(11)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(10)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2391	1

Signal:

RAM_MEMORY(10)(9)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	2377	1

Signal:

RAM_MEMORY(10)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(7)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(6)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(5)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	2377	1

Signal:

RAM_MEMORY(10)(4)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2362	1

Signal:

RAM_MEMORY(10)(3)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	2401	1

Signal:

RAM_MEMORY(10)(2)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2338	1

Signal:

RAM_MEMORY(10)(1)

	From	To	Count	Threshold
Bin	0	1	126	1
Bin	1	0	2377	1

Signal:

RAM_MEMORY(10)(0)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2328	1

Signal:

RAM_MEMORY(11)(31)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2188	1

Signal:

RAM_MEMORY(11)(30)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2188	1

Signal:

RAM_MEMORY(11)(29)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	2179	1

Signal:

RAM_MEMORY(11)(28)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2226	1

Signal:

RAM_MEMORY(11)(27)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2226	1

Signal:

RAM_MEMORY(11)(26)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2217	1

Signal:

RAM_MEMORY(11)(25)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2179	1

Signal:

RAM_MEMORY(11)(24)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	2179	1

Signal:

RAM_MEMORY(11)(23)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2188	1

Signal:

RAM_MEMORY(11)(22)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2240	1

Signal:

RAM_MEMORY(11)(21)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2179	1

Signal:

RAM_MEMORY(11)(20)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2226	1

Signal:

RAM_MEMORY(11)(19)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	2217	1

Signal:

RAM_MEMORY(11)(18)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2211	1

Signal:

RAM_MEMORY(11)(17)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2231	1

Signal:

RAM_MEMORY(11)(16)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2211	1

Signal:

RAM_MEMORY(11)(15)

	From	To	Count	Threshold
Bin	0	1	124	1
Bin	1	0	2226	1

Signal:

RAM_MEMORY(11)(14)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	2179	1

Signal:

RAM_MEMORY(11)(13)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2179	1

Signal:

RAM_MEMORY(11)(12)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	2202	1

Signal:

RAM_MEMORY(11)(11)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2226	1

Signal:

RAM_MEMORY(11)(10)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	2240	1

Signal:

RAM_MEMORY(11)(9)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2226	1

Signal:

RAM_MEMORY(11)(8)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2249	1

Signal:

RAM_MEMORY(11)(7)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2217	1

Signal:

RAM_MEMORY(11)(6)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2226	1

Signal:

RAM_MEMORY(11)(5)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2179	1

Signal:

RAM_MEMORY(11)(4)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	2217	1

Signal:

RAM_MEMORY(11)(3)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2211	1

Signal:

RAM_MEMORY(11)(2)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2226	1

Signal:

RAM_MEMORY(11)(1)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2211	1

Signal:

RAM_MEMORY(11)(0)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2188	1

Signal:

RAM_MEMORY(12)(31)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(12)(30)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2130	1

Signal:

RAM_MEMORY(12)(29)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(28)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2130	1

Signal:

RAM_MEMORY(12)(27)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(26)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(25)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	2122	1

Signal:

RAM_MEMORY(12)(24)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(23)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(22)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2130	1

Signal:

RAM_MEMORY(12)(21)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(12)(20)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2130	1

Signal:

RAM_MEMORY(12)(19)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(18)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(17)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	2122	1

Signal:

RAM_MEMORY(12)(16)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(15)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	2130	1

Signal:

RAM_MEMORY(12)(14)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	2122	1

Signal:

RAM_MEMORY(12)(13)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2130	1

Signal:

RAM_MEMORY(12)(12)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2130	1

Signal:

RAM_MEMORY(12)(11)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	2122	1

Signal:

RAM_MEMORY(12)(10)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	2122	1

Signal:

RAM_MEMORY(12)(9)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(12)(8)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(12)(7)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(12)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(5)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2093	1

Signal:

RAM_MEMORY(12)(4)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2130	1

Signal:

RAM_MEMORY(12)(3)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(12)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(12)(1)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(12)(0)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2085	1

Signal:

RAM_MEMORY(13)(31)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1941	1

Signal:

RAM_MEMORY(13)(30)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1941	1

Signal:

RAM_MEMORY(13)(29)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(28)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1977	1

Signal:

RAM_MEMORY(13)(27)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(26)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1977	1

Signal:

RAM_MEMORY(13)(25)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	1977	1

Signal:

RAM_MEMORY(13)(24)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(23)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1941	1

Signal:

RAM_MEMORY(13)(22)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1977	1

Signal:

RAM_MEMORY(13)(21)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(20)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1970	1

Signal:

RAM_MEMORY(13)(19)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	1941	1

Signal:

RAM_MEMORY(13)(18)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1970	1

Signal:

RAM_MEMORY(13)(17)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1970	1

Signal:

RAM_MEMORY(13)(16)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1977	1

Signal:

RAM_MEMORY(13)(15)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1941	1

Signal:

RAM_MEMORY(13)(13)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1977	1

Signal:

RAM_MEMORY(13)(12)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(11)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1977	1

Signal:

RAM_MEMORY(13)(10)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1977	1

Signal:

RAM_MEMORY(13)(9)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1941	1

Signal:

RAM_MEMORY(13)(8)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1970	1

Signal:

RAM_MEMORY(13)(7)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(6)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(5)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1970	1

Signal:

RAM_MEMORY(13)(4)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1941	1

Signal:

RAM_MEMORY(13)(3)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1970	1

Signal:

RAM_MEMORY(13)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(1)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1934	1

Signal:

RAM_MEMORY(13)(0)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1970	1

Signal:

RAM_MEMORY(14)(31)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1824	1

Signal:

RAM_MEMORY(14)(30)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(29)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(28)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(27)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(26)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1824	1

Signal:

RAM_MEMORY(14)(25)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(24)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1783	1

Signal:

RAM_MEMORY(14)(23)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(21)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(20)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(19)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1824	1

Signal:

RAM_MEMORY(14)(18)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1824	1

Signal:

RAM_MEMORY(14)(17)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(16)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(14)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1824	1

Signal:

RAM_MEMORY(14)(13)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1824	1

Signal:

RAM_MEMORY(14)(12)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1783	1

Signal:

RAM_MEMORY(14)(11)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(10)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(9)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1824	1

Signal:

RAM_MEMORY(14)(8)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1818	1

Signal:

RAM_MEMORY(14)(7)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(6)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1783	1

Signal:

RAM_MEMORY(14)(5)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(4)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1783	1

Signal:

RAM_MEMORY(14)(3)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1783	1

Signal:

RAM_MEMORY(14)(1)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1789	1

Signal:

RAM_MEMORY(14)(0)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1824	1

Signal:

RAM_MEMORY(15)(31)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(30)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(29)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(15)(28)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1666	1

Signal:

RAM_MEMORY(15)(27)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(15)(26)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(25)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(15)(24)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(23)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(22)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1666	1

Signal:

RAM_MEMORY(15)(21)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(20)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(15)(19)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(18)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(15)(17)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1666	1

Signal:

RAM_MEMORY(15)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(15)(15)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1637	1

Signal:

RAM_MEMORY(15)(13)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1637	1

Signal:

RAM_MEMORY(15)(11)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1637	1

Signal:

RAM_MEMORY(15)(10)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1637	1

Signal:

RAM_MEMORY(15)(9)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(15)(8)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(7)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1666	1

Signal:

RAM_MEMORY(15)(6)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(5)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1666	1

Signal:

RAM_MEMORY(15)(4)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1666	1

Signal:

RAM_MEMORY(15)(3)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(15)(2)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1671	1

Signal:

RAM_MEMORY(15)(1)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1666	1

Signal:

RAM_MEMORY(15)(0)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1632	1

Signal:

RAM_MEMORY(16)(31)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(30)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(29)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1521	1

Signal:

RAM_MEMORY(16)(28)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(27)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(26)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1488	1

Signal:

RAM_MEMORY(16)(25)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(24)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1521	1

Signal:

RAM_MEMORY(16)(23)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(22)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(21)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1521	1

Signal:

RAM_MEMORY(16)(20)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(19)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1521	1

Signal:

RAM_MEMORY(16)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1488	1

Signal:

RAM_MEMORY(16)(17)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1488	1

Signal:

RAM_MEMORY(16)(16)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1521	1

Signal:

RAM_MEMORY(16)(15)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1521	1

Signal:

RAM_MEMORY(16)(14)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1521	1

Signal:

RAM_MEMORY(16)(13)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(12)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(11)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(10)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(9)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(8)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1521	1

Signal:

RAM_MEMORY(16)(7)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(6)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1517	1

Signal:

RAM_MEMORY(16)(5)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(3)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(1)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1484	1

Signal:

RAM_MEMORY(16)(0)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1488	1

Signal:

RAM_MEMORY(17)(31)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(17)(29)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1367	1

Signal:

RAM_MEMORY(17)(28)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(27)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(26)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1367	1

Signal:

RAM_MEMORY(17)(25)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(24)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1367	1

Signal:

RAM_MEMORY(17)(23)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(17)(21)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1367	1

Signal:

RAM_MEMORY(17)(20)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1367	1

Signal:

RAM_MEMORY(17)(19)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(18)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(17)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1367	1

Signal:

RAM_MEMORY(17)(16)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(17)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(17)(13)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(17)(11)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(10)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(9)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1367	1

Signal:

RAM_MEMORY(17)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(7)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(17)(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(5)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(4)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(17)(3)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(17)(1)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1332	1

Signal:

RAM_MEMORY(17)(0)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1335	1

Signal:

RAM_MEMORY(18)(31)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1211	1

Signal:

RAM_MEMORY(18)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(29)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1211	1

Signal:

RAM_MEMORY(18)(28)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1180	1

Signal:

RAM_MEMORY(18)(27)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(26)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1211	1

Signal:

RAM_MEMORY(18)(25)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1213	1

Signal:

RAM_MEMORY(18)(24)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1213	1

Signal:

RAM_MEMORY(18)(23)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(21)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1180	1

Signal:

RAM_MEMORY(18)(20)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(19)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1213	1

Signal:

RAM_MEMORY(18)(18)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1213	1

Signal:

RAM_MEMORY(18)(17)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1180	1

Signal:

RAM_MEMORY(18)(15)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1213	1

Signal:

RAM_MEMORY(18)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(13)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(12)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1213	1

Signal:

RAM_MEMORY(18)(11)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1180	1

Signal:

RAM_MEMORY(18)(10)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1180	1

Signal:

RAM_MEMORY(18)(9)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1211	1

Signal:

RAM_MEMORY(18)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1180	1

Signal:

RAM_MEMORY(18)(7)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1180	1

Signal:

RAM_MEMORY(18)(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1180	1

Signal:

RAM_MEMORY(18)(5)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1211	1

Signal:

RAM_MEMORY(18)(4)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1182	1

Signal:

RAM_MEMORY(18)(3)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1211	1

Signal:

RAM_MEMORY(18)(2)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1211	1

Signal:

RAM_MEMORY(18)(1)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1211	1

Signal:

RAM_MEMORY(18)(0)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1213	1

Signal:

RAM_MEMORY(19)(31)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(30)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(29)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(28)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(27)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(26)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(25)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(24)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1058	1

Signal:

RAM_MEMORY(19)(23)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(22)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1058	1

Signal:

RAM_MEMORY(19)(21)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(20)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(19)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(18)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(17)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(15)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(13)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1058	1

Signal:

RAM_MEMORY(19)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(11)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(9)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(8)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(7)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(6)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(5)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1029	1

Signal:

RAM_MEMORY(19)(4)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1058	1

Signal:

RAM_MEMORY(19)(3)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1028	1

Signal:

RAM_MEMORY(19)(1)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(0)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1058	1

Signal:

RAM_MEMORY(20)(31)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	965	1

Signal:

RAM_MEMORY(20)(30)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(29)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(28)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(27)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(26)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	945	1

Signal:

RAM_MEMORY(20)(25)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	965	1

Signal:

RAM_MEMORY(20)(24)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(23)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	965	1

Signal:

RAM_MEMORY(20)(22)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(21)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	945	1

Signal:

RAM_MEMORY(20)(20)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(19)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(18)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(17)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	965	1

Signal:

RAM_MEMORY(20)(16)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	924	1

Signal:

RAM_MEMORY(20)(15)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	785	1

Signal:

RAM_MEMORY(20)(14)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	744	1

Signal:

RAM_MEMORY(20)(13)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	744	1

Signal:

RAM_MEMORY(20)(12)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	745	1

Signal:

RAM_MEMORY(20)(11)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	800	1

Signal:

RAM_MEMORY(20)(10)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	774	1

Signal:

RAM_MEMORY(20)(9)

	From	To	Count	Threshold
Bin	0	1	142	1
Bin	1	0	875	1

Signal:

RAM_MEMORY(20)(8)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	780	1

Signal:

RAM_MEMORY(20)(7)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	784	1

Signal:

RAM_MEMORY(20)(6)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	743	1

Signal:

RAM_MEMORY(20)(5)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	764	1

Signal:

RAM_MEMORY(20)(4)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	764	1

Signal:

RAM_MEMORY(20)(3)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	743	1

Signal:

RAM_MEMORY(20)(2)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	782	1

Signal:

RAM_MEMORY(20)(1)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	785	1

Signal:

RAM_MEMORY(20)(0)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	780	1

Signal:

INT_READ_DATA(31)

	From	To	Count	Threshold
Bin	0	1	354	1
Bin	1	0	509	1

Signal:

INT_READ_DATA(30)

	From	To	Count	Threshold
Bin	0	1	386	1
Bin	1	0	541	1

Signal:

INT_READ_DATA(29)

	From	To	Count	Threshold
Bin	0	1	307	1
Bin	1	0	462	1

Signal:

INT_READ_DATA(28)

	From	To	Count	Threshold
Bin	0	1	1020	1
Bin	1	0	1175	1

Signal:

INT_READ_DATA(27)

	From	To	Count	Threshold
Bin	0	1	1053	1
Bin	1	0	1208	1

Signal:

INT_READ_DATA(26)

	From	To	Count	Threshold
Bin	0	1	845	1
Bin	1	0	1000	1

Signal:

INT_READ_DATA(25)

	From	To	Count	Threshold
Bin	0	1	1221	1
Bin	1	0	1376	1

Signal:

INT_READ_DATA(24)

	From	To	Count	Threshold
Bin	0	1	1252	1
Bin	1	0	1407	1

Signal:

INT_READ_DATA(23)

	From	To	Count	Threshold
Bin	0	1	1114	1
Bin	1	0	1268	1

Signal:

INT_READ_DATA(22)

	From	To	Count	Threshold
Bin	0	1	1043	1
Bin	1	0	1198	1

Signal:

INT_READ_DATA(21)

	From	To	Count	Threshold
Bin	0	1	1207	1
Bin	1	0	1362	1

Signal:

INT_READ_DATA(20)

	From	To	Count	Threshold
Bin	0	1	840	1
Bin	1	0	995	1

Signal:

INT_READ_DATA(19)

	From	To	Count	Threshold
Bin	0	1	1312	1
Bin	1	0	1467	1

Signal:

INT_READ_DATA(18)

	From	To	Count	Threshold
Bin	0	1	1190	1
Bin	1	0	1345	1

Signal:

INT_READ_DATA(17)

	From	To	Count	Threshold
Bin	0	1	669	1
Bin	1	0	824	1

Signal:

INT_READ_DATA(16)

	From	To	Count	Threshold
Bin	0	1	511	1
Bin	1	0	666	1

Signal:

INT_READ_DATA(15)

	From	To	Count	Threshold
Bin	0	1	907	1
Bin	1	0	1062	1

Signal:

INT_READ_DATA(14)

	From	To	Count	Threshold
Bin	0	1	671	1
Bin	1	0	826	1

Signal:

INT_READ_DATA(13)

	From	To	Count	Threshold
Bin	0	1	852	1
Bin	1	0	1007	1

Signal:

INT_READ_DATA(12)

	From	To	Count	Threshold
Bin	0	1	643	1
Bin	1	0	798	1

Signal:

INT_READ_DATA(11)

	From	To	Count	Threshold
Bin	0	1	645	1
Bin	1	0	800	1

Signal:

INT_READ_DATA(10)

	From	To	Count	Threshold
Bin	0	1	559	1
Bin	1	0	714	1

Signal:

INT_READ_DATA(9)

	From	To	Count	Threshold
Bin	0	1	1256	1
Bin	1	0	1411	1

Signal:

INT_READ_DATA(8)

	From	To	Count	Threshold
Bin	0	1	705	1
Bin	1	0	860	1

Signal:

INT_READ_DATA(7)

	From	To	Count	Threshold
Bin	0	1	1214	1
Bin	1	0	1369	1

Signal:

INT_READ_DATA(6)

	From	To	Count	Threshold
Bin	0	1	993	1
Bin	1	0	1148	1

Signal:

INT_READ_DATA(5)

	From	To	Count	Threshold
Bin	0	1	1018	1
Bin	1	0	1173	1

Signal:

INT_READ_DATA(4)

	From	To	Count	Threshold
Bin	0	1	598	1
Bin	1	0	753	1

Signal:

INT_READ_DATA(3)

	From	To	Count	Threshold
Bin	0	1	901	1
Bin	1	0	1056	1

Signal:

INT_READ_DATA(2)

	From	To	Count	Threshold
Bin	0	1	1081	1
Bin	1	0	1236	1

Signal:

INT_READ_DATA(1)

	From	To	Count	Threshold
Bin	0	1	1163	1
Bin	1	0	1318	1

Signal:

INT_READ_DATA(0)

	From	To	Count	Threshold
Bin	0	1	1042	1
Bin	1	0	1197	1

Signal:

BYTE_WE(3)

	From	To	Count	Threshold
Bin	0	1	11588	1
Bin	1	0	11753	1

Signal:

BYTE_WE(2)

	From	To	Count	Threshold
Bin	0	1	11588	1
Bin	1	0	11753	1

Signal:

BYTE_WE(1)

	From	To	Count	Threshold
Bin	0	1	11588	1
Bin	1	0	11753	1

Signal:

BYTE_WE(0)

	From	To	Count	Threshold
Bin	0	1	11588	1
Bin	1	0	11753	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: