NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)
BIT_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)
BIT_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)
BIT_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)
BIT_GEN(4)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)
BIT_GEN(5)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)
BIT_GEN(6)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)
BIT_GEN(7)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

BIT_GEN(0)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

BIT_GEN(1)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

BIT_GEN(2)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

BIT_GEN(3)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

BIT_GEN(4)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

BIT_GEN(5)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

BIT_GEN(6)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

BIT_GEN(7)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (2/2)

N.A.

100.0 % (7/7)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.INT_MASK_SET_INT_MASK_SET_SLICE_1_REG_COMP	100.0 % (2/2)	N.A.	100.0 % (58/58)	100.0 % (3/3)	N.A.	N.A.	100.0 % (63/63)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.INT_MASK_SET_INT_MASK_SET_SLICE_1_REG_COMP

100.0 % (2/2)

N.A.

100.0 % (58/58)

100.0 % (3/3)

N.A.

100.0 % (63/63)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 140:

140: wr_en <= write and cs;
Count: 299277
Threshold: 1

Signal assignment statement on line 156:

156: reg_value <= reg_value_r;
Count: 4232
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

REG_VALUE

	Element	From	To	Count	Threshold
Bin	(7)	0	1	10	1
Bin	(7)	1	0	2076	1
Bin	(6)	0	1	10	1
Bin	(6)	1	0	2076	1
Bin	(5)	0	1	10	1
Bin	(5)	1	0	2076	1
Bin	(4)	0	1	10	1
Bin	(4)	1	0	2076	1
Bin	(3)	0	1	10	1
Bin	(3)	1	0	2076	1
Bin	(2)	0	1	10	1
Bin	(2)	1	0	2076	1
Bin	(1)	0	1	10	1
Bin	(1)	1	0	2076	1
Bin	(0)	0	1	10	1
Bin	(0)	1	0	2076	1

Signal:

REG_VALUE_R

	Element	From	To	Count	Threshold
Bin	(7)	0	1	10	1
Bin	(7)	1	0	2146	1
Bin	(6)	0	1	10	1
Bin	(6)	1	0	2146	1
Bin	(5)	0	1	10	1
Bin	(5)	1	0	2146	1
Bin	(4)	0	1	10	1
Bin	(4)	1	0	2146	1
Bin	(3)	0	1	10	1
Bin	(3)	1	0	2146	1
Bin	(2)	0	1	10	1
Bin	(2)	1	0	2146	1
Bin	(1)	0	1	10	1
Bin	(1)	1	0	2146	1
Bin	(0)	0	1	10	1
Bin	(0)	1	0	2146	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	475	1
Bin	1	0	2076	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 140:

 write and cs 
 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	565	1
Bin	'1'	'0'	146672	1
Bin	'1'	'1'	475	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.INT_MASK_SET_INT_MASK_SET_SLICE_1_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 140:

Signal assignment statement on line 156:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 140:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: