NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
INT_MODULE_GEN(0)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(1)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(2)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(3)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(4)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(5)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(6)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(7)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(8)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(9)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(10)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
INT_MODULE_GEN(11)	100.0 % (20/20)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (100/100)
DFF_INT_OUTPUT_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

INT_MODULE_GEN(0)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(1)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(2)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(3)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(4)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(5)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(6)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(7)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(8)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(9)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(10)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

INT_MODULE_GEN(11)

100.0 % (20/20)

100.0 % (24/24)

100.0 % (30/30)

100.0 % (26/26)

N.A.

100.0 % (100/100)

DFF_INT_OUTPUT_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST	100.0 % (43/43)	100.0 % (2/2)	100.0 % (334/334)	N.A.	N.A.	N.A.	100.0 % (379/379)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST

100.0 % (43/43)

100.0 % (2/2)

100.0 % (334/334)

N.A.

100.0 % (379/379)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Loop statement on lines 212 to 214:

212:        for i in input'range loop 
213:            tmp := tmp or input(i); 
214:        end loop;

Count: 44636
Threshold: 1

Variable assignment statement on line 213:

213: tmp := tmp or input(i);
Count: 150624
Threshold: 1

Sequential statement on line 215:

215: return tmp;
Count: 44636
Threshold: 1

If statement on lines 223 to 225:

223:    int_i  <= '0' when ((int_status_i and mr_int_ena_set_int_ena_set_o_i) = C_ZERO_MASK) 
224:                  else 
225:              '1';

Count: 19168
Threshold: 1

Signal assignment statement on line 223:

223: int_i <= '0' when ((int_status_i and mr_int_ena_set_int_ena_set_o_i) = C_ZERO_MASK)
Count: 17287
Threshold: 1

Signal assignment statement on line 225:

225: '1';
Count: 1881
Threshold: 1

Signal assignment statement on line 231:

231: int_input_active(RXI_IND) <= rec_valid;
Count: 33558
Threshold: 1

Signal assignment statement on line 232:

232: int_input_active(TXI_IND) <= tran_valid;
Count: 25426
Threshold: 1

Signal assignment statement on line 233:

233: int_input_active(EWLI_IND) <= err_warning_limit_pulse;
Count: 9514
Threshold: 1

Signal assignment statement on line 234:

234: int_input_active(DOI_IND) <= rx_data_overrun;
Count: 3264
Threshold: 1

Signal assignment statement on line 235:

235: int_input_active(FCSI_IND) <= fcs_changed;
Count: 35168
Threshold: 1

Signal assignment statement on line 236:

236: int_input_active(ALI_IND) <= arbitration_lost;
Count: 5544
Threshold: 1

Signal assignment statement on line 237:

237: int_input_active(BEI_IND) <= err_detected;
Count: 252142
Threshold: 1

Signal assignment statement on line 238:

238: int_input_active(OFI_IND) <= is_overload;
Count: 4260
Threshold: 1

Signal assignment statement on line 239:

239: int_input_active(RXFI_IND) <= rx_full;
Count: 3242
Threshold: 1

Signal assignment statement on line 240:

240: int_input_active(BSI_IND) <= br_shifted;
Count: 98498
Threshold: 1

Signal assignment statement on line 241:

241: int_input_active(RBNEI_IND) <= not rx_empty;
Count: 19601
Threshold: 1

Signal assignment statement on line 242:

242: int_input_active(TXBHCI_IND) <= or_reduce(txtb_hw_cmd_int);
Count: 44636
Threshold: 1

Signal assignment statement on line 245:

245: int_status_clr_i(RXI_IND) <= mr_int_stat_rxi_i;
Count: 3536
Threshold: 1

Signal assignment statement on line 246:

246: int_status_clr_i(TXI_IND) <= mr_int_stat_txi_i;
Count: 3538
Threshold: 1

Signal assignment statement on line 247:

247: int_status_clr_i(EWLI_IND) <= mr_int_stat_ewli_i;
Count: 3526
Threshold: 1

Signal assignment statement on line 248:

248: int_status_clr_i(DOI_IND) <= mr_int_stat_doi_i;
Count: 3512
Threshold: 1

Signal assignment statement on line 249:

249: int_status_clr_i(FCSI_IND) <= mr_int_stat_fcsi_i;
Count: 3576
Threshold: 1

Signal assignment statement on line 250:

250: int_status_clr_i(ALI_IND) <= mr_int_stat_ali_i;
Count: 3501
Threshold: 1

Signal assignment statement on line 251:

251: int_status_clr_i(BEI_IND) <= mr_int_stat_bei_i;
Count: 3511
Threshold: 1

Signal assignment statement on line 252:

252: int_status_clr_i(OFI_IND) <= mr_int_stat_ofi_i;
Count: 3501
Threshold: 1

Signal assignment statement on line 253:

253: int_status_clr_i(RXFI_IND) <= mr_int_stat_rxfi_i;
Count: 3511
Threshold: 1

Signal assignment statement on line 254:

254: int_status_clr_i(BSI_IND) <= mr_int_stat_bsi_i;
Count: 3530
Threshold: 1

Signal assignment statement on line 255:

255: int_status_clr_i(RBNEI_IND) <= mr_int_stat_rbnei_i;
Count: 3546
Threshold: 1

Signal assignment statement on line 256:

256: int_status_clr_i(TXBHCI_IND) <= mr_int_stat_txbhci_i;
Count: 3548
Threshold: 1

Signal assignment statement on line 259:

259: mr_int_stat_rxi_o <= int_status_i(RXI_IND);
Count: 4816
Threshold: 1

Signal assignment statement on line 260:

260: mr_int_stat_txi_o <= int_status_i(TXI_IND);
Count: 5628
Threshold: 1

Signal assignment statement on line 261:

261: mr_int_stat_ewli_o <= int_status_i(EWLI_IND);
Count: 4375
Threshold: 1

Signal assignment statement on line 262:

262: mr_int_stat_doi_o <= int_status_i(DOI_IND);
Count: 3244
Threshold: 1

Signal assignment statement on line 263:

263: mr_int_stat_fcsi_o <= int_status_i(FCSI_IND);
Count: 9798
Threshold: 1

Signal assignment statement on line 264:

264: mr_int_stat_ali_o <= int_status_i(ALI_IND);
Count: 3398
Threshold: 1

Signal assignment statement on line 265:

265: mr_int_stat_bei_o <= int_status_i(BEI_IND);
Count: 6028
Threshold: 1

Signal assignment statement on line 266:

266: mr_int_stat_ofi_o <= int_status_i(OFI_IND);
Count: 3506
Threshold: 1

Signal assignment statement on line 267:

267: mr_int_stat_rxfi_o <= int_status_i(RXFI_IND);
Count: 3242
Threshold: 1

Signal assignment statement on line 268:

268: mr_int_stat_bsi_o <= int_status_i(BSI_IND);
Count: 5794
Threshold: 1

Signal assignment statement on line 269:

269: mr_int_stat_rbnei_o <= int_status_i(RBNEI_IND);
Count: 5072
Threshold: 1

Signal assignment statement on line 270:

270: mr_int_stat_txbhci_o <= int_status_i(TXBHCI_IND);
Count: 6557
Threshold: 1

Signal assignment statement on line 315:

315: mr_int_ena_set_int_ena_set_o <= mr_int_ena_set_int_ena_set_o_i;
Count: 3774
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 223:

223: int_i <= '0' when ((int_status_i and mr_int_ena_set_int_ena_set_o_i) = C_ZERO_MASK)

	Evaluated to	Count	Threshold
Bin	True	17287	1
Bin	False	1881	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DETECTED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

FCS_CHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_WARNING_LIMIT_PULSE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ARBITRATION_LOST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BR_SHIFTED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_DATA_OVERRUN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_FULL

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_EMPTY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_HW_CMD_INT

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

IS_OVERLOAD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_ENA_SET_INT_ENA_SET

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_INT_ENA_CLR_INT_ENA_CLR

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_INT_MASK_SET_INT_MASK_SET

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_INT_MASK_CLR_INT_MASK_CLR

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_INT_STAT_RXI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_TXI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_EWLI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_DOI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_FCSI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_ALI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_BEI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_OFI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_RXFI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_BSI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_RBNEI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_TXBHCI_I

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_INT_STAT_RXI_O

	From	To	Count	Threshold
Bin	0	1	808	1
Bin	1	0	2407	1

Port:

MR_INT_STAT_TXI_O

	From	To	Count	Threshold
Bin	0	1	1215	1
Bin	1	0	2812	1

Port:

MR_INT_STAT_EWLI_O

	From	To	Count	Threshold
Bin	0	1	587	1
Bin	1	0	2187	1

Port:

MR_INT_STAT_DOI_O

	From	To	Count	Threshold
Bin	0	1	21	1
Bin	1	0	1622	1

Port:

MR_INT_STAT_FCSI_O

	From	To	Count	Threshold
Bin	0	1	3304	1
Bin	1	0	4893	1

Port:

MR_INT_STAT_ALI_O

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	1698	1

Port:

MR_INT_STAT_BEI_O

	From	To	Count	Threshold
Bin	0	1	1417	1
Bin	1	0	3010	1

Port:

MR_INT_STAT_OFI_O

	From	To	Count	Threshold
Bin	0	1	152	1
Bin	1	0	1753	1

Port:

MR_INT_STAT_RXFI_O

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1621	1

Port:

MR_INT_STAT_BSI_O

	From	To	Count	Threshold
Bin	0	1	1299	1
Bin	1	0	2894	1

Port:

MR_INT_STAT_RBNEI_O

	From	To	Count	Threshold
Bin	0	1	936	1
Bin	1	0	2535	1

Port:

MR_INT_STAT_TXBHCI_O

	From	To	Count	Threshold
Bin	0	1	1680	1
Bin	1	0	3276	1

Port:

MR_INT_ENA_SET_INT_ENA_SET_O

	Element	From	To	Count	Threshold
Bin	(11)	0	1	66	1
Bin	(11)	1	0	1667	1
Bin	(10)	0	1	30	1
Bin	(10)	1	0	1631	1
Bin	(9)	0	1	50	1
Bin	(9)	1	0	1651	1
Bin	(8)	0	1	15	1
Bin	(8)	1	0	1616	1
Bin	(7)	0	1	15	1
Bin	(7)	1	0	1616	1
Bin	(6)	0	1	15	1
Bin	(6)	1	0	1616	1
Bin	(5)	0	1	15	1
Bin	(5)	1	0	1616	1
Bin	(4)	0	1	15	1
Bin	(4)	1	0	1616	1
Bin	(3)	0	1	15	1
Bin	(3)	1	0	1616	1
Bin	(2)	0	1	20	1
Bin	(2)	1	0	1621	1
Bin	(1)	0	1	15	1
Bin	(1)	1	0	1616	1
Bin	(0)	0	1	15	1
Bin	(0)	1	0	1616	1

Port:

MR_INT_MASK_SET_INT_MASK_SET_O

	Element	From	To	Count	Threshold
Bin	(11)	0	1	22	1
Bin	(11)	1	0	1813	1
Bin	(10)	0	1	20	1
Bin	(10)	1	0	1815	1
Bin	(9)	0	1	20	1
Bin	(9)	1	0	1815	1
Bin	(8)	0	1	5	1
Bin	(8)	1	0	1830	1
Bin	(7)	0	1	5	1
Bin	(7)	1	0	1830	1
Bin	(6)	0	1	5	1
Bin	(6)	1	0	1830	1
Bin	(5)	0	1	5	1
Bin	(5)	1	0	1830	1
Bin	(4)	0	1	5	1
Bin	(4)	1	0	1830	1
Bin	(3)	0	1	5	1
Bin	(3)	1	0	1830	1
Bin	(2)	0	1	5	1
Bin	(2)	1	0	1830	1
Bin	(1)	0	1	10	1
Bin	(1)	1	0	1825	1
Bin	(0)	0	1	10	1
Bin	(0)	1	0	1825	1

Port:

INT

	From	To	Count	Threshold
Bin	0	1	1840	1
Bin	1	0	1840	1

Signal:

INT_INPUT_ACTIVE

	Element	From	To	Count	Threshold
Bin	(11)	0	1	32085	1
Bin	(11)	1	0	470259	1
Bin	(10)	0	1	71371	1
Bin	(10)	1	0	429372	1
Bin	(9)	0	1	61202	1
Bin	(9)	1	0	439541	1
Bin	(8)	0	1	250	1
Bin	(8)	1	0	502094	1
Bin	(7)	0	1	736	1
Bin	(7)	1	0	500007	1
Bin	(6)	0	1	138400	1
Bin	(6)	1	0	360742	1
Bin	(5)	0	1	1449	1
Bin	(5)	1	0	496092	1
Bin	(4)	0	1	16100	1
Bin	(4)	1	0	486244	1
Bin	(3)	0	1	335	1
Bin	(3)	1	0	489201	1
Bin	(2)	0	1	6818	1
Bin	(2)	1	0	495526	1
Bin	(1)	0	1	22224	1
Bin	(1)	1	0	472115	1
Bin	(0)	0	1	15182	1
Bin	(0)	1	0	480758	1

Signal:

INT_STATUS_I

	Element	From	To	Count	Threshold
Bin	(11)	0	1	2925	1
Bin	(11)	1	0	12469	1
Bin	(10)	0	1	1737	1
Bin	(10)	1	0	13657	1
Bin	(9)	0	1	2480	1
Bin	(9)	1	0	12914	1
Bin	(8)	0	1	50	1
Bin	(8)	1	0	15344	1
Bin	(7)	0	1	284	1
Bin	(7)	1	0	15110	1
Bin	(6)	0	1	3069	1
Bin	(6)	1	0	12325	1
Bin	(5)	0	1	359	1
Bin	(5)	1	0	15035	1
Bin	(4)	0	1	10194	1
Bin	(4)	1	0	5200	1
Bin	(3)	0	1	36	1
Bin	(3)	1	0	15358	1
Bin	(2)	0	1	1146	1
Bin	(2)	1	0	14248	1
Bin	(1)	0	1	2022	1
Bin	(1)	1	0	13372	1
Bin	(0)	0	1	2351	1
Bin	(0)	1	0	13043	1

Signal:

INT_STATUS_CLR_I

	Element	From	To	Count	Threshold
Bin	(11)	0	1	52	1
Bin	(11)	1	0	1838	1
Bin	(10)	0	1	50	1
Bin	(10)	1	0	1840	1
Bin	(9)	0	1	34	1
Bin	(9)	1	0	1856	1
Bin	(8)	0	1	15	1
Bin	(8)	1	0	1875	1
Bin	(7)	0	1	5	1
Bin	(7)	1	0	1885	1
Bin	(6)	0	1	15	1
Bin	(6)	1	0	1875	1
Bin	(5)	0	1	5	1
Bin	(5)	1	0	1885	1
Bin	(4)	0	1	80	1
Bin	(4)	1	0	1810	1
Bin	(3)	0	1	16	1
Bin	(3)	1	0	1874	1
Bin	(2)	0	1	30	1
Bin	(2)	1	0	1860	1
Bin	(1)	0	1	42	1
Bin	(1)	1	0	1848	1
Bin	(0)	0	1	40	1
Bin	(0)	1	0	1850	1

Signal:

INT_I

	From	To	Count	Threshold
Bin	0	1	1840	1
Bin	1	0	1840	1

Signal:

MR_INT_ENA_SET_INT_ENA_SET_O_I

	Element	From	To	Count	Threshold
Bin	(11)	0	1	66	1
Bin	(11)	1	0	2107	1
Bin	(10)	0	1	30	1
Bin	(10)	1	0	2143	1
Bin	(9)	0	1	50	1
Bin	(9)	1	0	2123	1
Bin	(8)	0	1	15	1
Bin	(8)	1	0	2158	1
Bin	(7)	0	1	15	1
Bin	(7)	1	0	2158	1
Bin	(6)	0	1	15	1
Bin	(6)	1	0	2158	1
Bin	(5)	0	1	15	1
Bin	(5)	1	0	2158	1
Bin	(4)	0	1	15	1
Bin	(4)	1	0	2158	1
Bin	(3)	0	1	15	1
Bin	(3)	1	0	2158	1
Bin	(2)	0	1	20	1
Bin	(2)	1	0	2153	1
Bin	(1)	0	1	15	1
Bin	(1)	1	0	2158	1
Bin	(0)	0	1	15	1
Bin	(0)	1	0	2158	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

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