Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| INT_MODULE_GEN(0) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(1) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(2) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(3) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(4) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(5) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(6) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(7) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(8) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(9) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(10) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| INT_MODULE_GEN(11) |
100.0 % (18/18) |
100.0 % (24/24) |
100.0 % (30/30) |
100.0 % (26/26) |
N.A. |
N.A. |
100.0 % (98/98) |
| DFF_INT_OUTPUT_REG |
100.0 % (3/3) |
100.0 % (4/4) |
100.0 % (8/8) |
100.0 % (2/2) |
N.A. |
N.A. |
100.0 % (17/17) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
223: int_i <= '0' when ((int_status_i and mr_int_ena_set_int_ena_set_o_i) = C_ZERO_MASK)
224: else
225: '1'; Count: 19198
Threshold: 1
Signal assignment statement:
223: int_i <= '0' when ((int_status_i and mr_int_ena_set_int_ena_set_o_i) = C_ZERO_MASK) Count: 17313
Threshold: 1
Signal assignment statement:
225: '1'; Count: 1885
Threshold: 1
Signal assignment statement:
241: int_input_active(RBNEI_IND) <= not rx_empty; Count: 19498
Threshold: 1
Signal assignment statement:
242: int_input_active(TXBHCI_IND) <= or_reduce(txtb_hw_cmd_int); Count: 43728
Threshold: 1
Loop statement:
212: for i in input'range loop
213: tmp := tmp or input(i);
214: end loop; Count: 43728
Threshold: 1
Variable assignment statement:
213: tmp := tmp or input(i); Count: 147092
Threshold: 1
Sequential statement:
215: return tmp; Count: 43728
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
223: int_i <= '0' when ((int_status_i and mr_int_ena_set_int_ena_set_o_i) = C_ZERO_MASK) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 17313 | 1 |
| Bin | False | 1885 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9642 | 1 |
| Bin | 1 | 0 | 8042 | 1 |
Port:
ERR_DETECTED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123242 | 1 |
| Bin | 1 | 0 | 124842 | 1 |
Port:
FCS_CHANGED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15989 | 1 |
| Bin | 1 | 0 | 17589 | 1 |
Port:
ERR_WARNING_LIMIT_PULSE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3183 | 1 |
| Bin | 1 | 0 | 4783 | 1 |
Port:
ARBITRATION_LOST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1172 | 1 |
| Bin | 1 | 0 | 2772 | 1 |
Port:
TRAN_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Port:
BR_SHIFTED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47787 | 1 |
| Bin | 1 | 0 | 49387 | 1 |
Port:
RX_DATA_OVERRUN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31 | 1 |
| Bin | 1 | 0 | 1631 | 1 |
Port:
REC_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15179 | 1 |
| Bin | 1 | 0 | 16779 | 1 |
Port:
RX_FULL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
Port:
RX_EMPTY | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8948 | 1 |
| Bin | 1 | 0 | 8950 | 1 |
Port:
TXTB_HW_CMD_INT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 167 | 1 |
| Bin | 1 | 0 | 5172 | 1 |
Port:
TXTB_HW_CMD_INT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 164 | 1 |
| Bin | 1 | 0 | 5175 | 1 |
Port:
TXTB_HW_CMD_INT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 173 | 1 |
| Bin | 1 | 0 | 5166 | 1 |
Port:
TXTB_HW_CMD_INT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 168 | 1 |
| Bin | 1 | 0 | 5171 | 1 |
Port:
TXTB_HW_CMD_INT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 732 | 1 |
| Bin | 1 | 0 | 17418 | 1 |
Port:
TXTB_HW_CMD_INT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 753 | 1 |
| Bin | 1 | 0 | 17397 | 1 |
Port:
TXTB_HW_CMD_INT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6280 | 1 |
| Bin | 1 | 0 | 35848 | 1 |
Port:
TXTB_HW_CMD_INT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11943 | 1 |
| Bin | 1 | 0 | 30185 | 1 |
Port:
IS_OVERLOAD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 529 | 1 |
| Bin | 1 | 0 | 2129 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 2372 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 2408 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 2388 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2423 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2423 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2423 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2423 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2423 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2423 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2418 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2418 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2418 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 476 | 1 |
| Bin | 1 | 0 | 2208 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 512 | 1 |
| Bin | 1 | 0 | 2172 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 492 | 1 |
| Bin | 1 | 0 | 2192 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2162 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2162 | 1 |
Port:
MR_INT_ENA_CLR_INT_ENA_CLR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2162 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 2260 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 2286 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 2276 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2311 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2316 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2316 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2316 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2316 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2316 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2316 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2316 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2316 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 409 | 1 |
| Bin | 1 | 0 | 2141 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 435 | 1 |
| Bin | 1 | 0 | 2115 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 425 | 1 |
| Bin | 1 | 0 | 2125 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 460 | 1 |
| Bin | 1 | 0 | 2090 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Port:
MR_INT_MASK_CLR_INT_MASK_CLR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2085 | 1 |
Port:
MR_INT_STAT_RXI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_TXI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_EWLI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_DOI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_FCSI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_ALI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_BEI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_OFI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_RXFI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_BSI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_RBNEI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_TXBHCI_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Port:
MR_INT_STAT_RXI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 809 | 1 |
| Bin | 1 | 0 | 2407 | 1 |
Port:
MR_INT_STAT_TXI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1214 | 1 |
| Bin | 1 | 0 | 2810 | 1 |
Port:
MR_INT_STAT_EWLI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 597 | 1 |
| Bin | 1 | 0 | 2196 | 1 |
Port:
MR_INT_STAT_DOI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
Port:
MR_INT_STAT_FCSI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3303 | 1 |
| Bin | 1 | 0 | 4893 | 1 |
Port:
MR_INT_STAT_ALI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
Port:
MR_INT_STAT_BEI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1413 | 1 |
| Bin | 1 | 0 | 3007 | 1 |
Port:
MR_INT_STAT_OFI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 152 | 1 |
| Bin | 1 | 0 | 1752 | 1 |
Port:
MR_INT_STAT_RXFI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
Port:
MR_INT_STAT_BSI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1326 | 1 |
| Bin | 1 | 0 | 2921 | 1 |
Port:
MR_INT_STAT_RBNEI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 937 | 1 |
| Bin | 1 | 0 | 2535 | 1 |
Port:
MR_INT_STAT_TXBHCI_O | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1679 | 1 |
| Bin | 1 | 0 | 3275 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1666 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_INT_ENA_SET_INT_ENA_SET_O(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1812 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1814 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1814 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
Port:
MR_INT_MASK_SET_INT_MASK_SET_O(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
Port:
INT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1839 | 1 |
| Bin | 1 | 0 | 1839 | 1 |
Signal:
INT_INPUT_ACTIVE(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31616 | 1 |
| Bin | 1 | 0 | 467515 | 1 |
Signal:
INT_INPUT_ACTIVE(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 73077 | 1 |
| Bin | 1 | 0 | 424454 | 1 |
Signal:
INT_INPUT_ACTIVE(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61230 | 1 |
| Bin | 1 | 0 | 436301 | 1 |
Signal:
INT_INPUT_ACTIVE(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 246 | 1 |
| Bin | 1 | 0 | 498885 | 1 |
Signal:
INT_INPUT_ACTIVE(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 736 | 1 |
| Bin | 1 | 0 | 496795 | 1 |
Signal:
INT_INPUT_ACTIVE(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 137055 | 1 |
| Bin | 1 | 0 | 358876 | 1 |
Signal:
INT_INPUT_ACTIVE(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1448 | 1 |
| Bin | 1 | 0 | 492883 | 1 |
Signal:
INT_INPUT_ACTIVE(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16106 | 1 |
| Bin | 1 | 0 | 483025 | 1 |
Signal:
INT_INPUT_ACTIVE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 339 | 1 |
| Bin | 1 | 0 | 485992 | 1 |
Signal:
INT_INPUT_ACTIVE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6850 | 1 |
| Bin | 1 | 0 | 492281 | 1 |
Signal:
INT_INPUT_ACTIVE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22196 | 1 |
| Bin | 1 | 0 | 468935 | 1 |
Signal:
INT_INPUT_ACTIVE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15185 | 1 |
| Bin | 1 | 0 | 477546 | 1 |
Signal:
INT_STATUS_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2938 | 1 |
| Bin | 1 | 0 | 12488 | 1 |
Signal:
INT_STATUS_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1756 | 1 |
| Bin | 1 | 0 | 13670 | 1 |
Signal:
INT_STATUS_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2489 | 1 |
| Bin | 1 | 0 | 12937 | 1 |
Signal:
INT_STATUS_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 15376 | 1 |
Signal:
INT_STATUS_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 297 | 1 |
| Bin | 1 | 0 | 15129 | 1 |
Signal:
INT_STATUS_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3079 | 1 |
| Bin | 1 | 0 | 12347 | 1 |
Signal:
INT_STATUS_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 363 | 1 |
| Bin | 1 | 0 | 15063 | 1 |
Signal:
INT_STATUS_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10216 | 1 |
| Bin | 1 | 0 | 5210 | 1 |
Signal:
INT_STATUS_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36 | 1 |
| Bin | 1 | 0 | 15390 | 1 |
Signal:
INT_STATUS_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1163 | 1 |
| Bin | 1 | 0 | 14263 | 1 |
Signal:
INT_STATUS_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2038 | 1 |
| Bin | 1 | 0 | 13388 | 1 |
Signal:
INT_STATUS_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2375 | 1 |
| Bin | 1 | 0 | 13051 | 1 |
Signal:
INT_STATUS_CLR_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1837 | 1 |
Signal:
INT_STATUS_CLR_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1839 | 1 |
Signal:
INT_STATUS_CLR_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1847 | 1 |
Signal:
INT_STATUS_CLR_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1874 | 1 |
Signal:
INT_STATUS_CLR_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1884 | 1 |
Signal:
INT_STATUS_CLR_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1874 | 1 |
Signal:
INT_STATUS_CLR_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1884 | 1 |
Signal:
INT_STATUS_CLR_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1809 | 1 |
Signal:
INT_STATUS_CLR_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16 | 1 |
| Bin | 1 | 0 | 1873 | 1 |
Signal:
INT_STATUS_CLR_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1859 | 1 |
Signal:
INT_STATUS_CLR_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1847 | 1 |
Signal:
INT_STATUS_CLR_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1849 | 1 |
Signal:
INT_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1839 | 1 |
| Bin | 1 | 0 | 1839 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 2106 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 2122 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2152 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Signal:
MR_INT_ENA_SET_INT_ENA_SET_O_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2157 | 1 |
Covered expressions:
"or" expression
213: tmp := tmp or input(i);
LHS <-RHS--> | LHS | RHS | Count | Threshold |
|---|
| Bin | '0' | '0' | 108158 | 1 |
| Bin | '0' | '1' | 20286 | 1 |
| Bin | '1' | '0' | 13374 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: