NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.MT_2_TXT_BUFFS

File:  /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd


Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.MT_2_TXT_BUFFS 100.0 % (2/2) N.A. N.A. N.A. N.A. N.A. 100.0 % (2/2)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

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Covered statements:

Signal assignment statement on line 631:

631:        mr_tx_priority(2)       <= mr_ctrl_out_i.tx_priority_txt3p
Count: 1670
Threshold: 1

Signal assignment statement on line 632:

632:        mr_tx_command_txbi(2)   <= mr_ctrl_out_i.tx_command_txb3
Count: 1980
Threshold: 1

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