NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RETRANSMITT_COUNTER_INST	100.0 % (15/15)	100.0 % (14/14)	100.0 % (46/46)	100.0 % (25/25)	N.A.	N.A.	100.0 % (100/100)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RETRANSMITT_COUNTER_INST

100.0 % (15/15)

100.0 % (14/14)

100.0 % (46/46)

100.0 % (25/25)

N.A.

100.0 % (100/100)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 143 to 145:

143:    retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else 
144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else 
145:                   retr_ctr_q;

Count: 89711
Threshold: 1

Signal assignment statement on line 143:

143: retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else
Count: 20838
Threshold: 1

Signal assignment statement on line 144:

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else

Count: 30743
Threshold: 1

Signal assignment statement on line 145:

145: retr_ctr_q;
Count: 38130
Threshold: 1

If statement on lines 148 to 150:

148:    retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1') 
149:                       else 
150:                   '0';

Count: 86797
Threshold: 1

Signal assignment statement on line 148:

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')
Count: 50305
Threshold: 1

Signal assignment statement on line 150:

150: '0';
Count: 36492
Threshold: 1

If statement on lines 157 to 163:

157:        if (res_n = '0') then 
158:            retr_ctr_q <= (others => '0'); 
...
162:            end if; 
163:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 158:

158: retr_ctr_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 160 to 162:

160:            if (retr_ctr_ce = '1') then 
161:                retr_ctr_q <= retr_ctr_d; 
162:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 161:

161: retr_ctr_q <= retr_ctr_d;
Count: 31679
Threshold: 1

If statement on lines 167 to 169:

167:    retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q) 
168:                              else 
169:                          '0';

Count: 6266
Threshold: 1

Signal assignment statement on line 167:

167: retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q)
Count: 1853
Threshold: 1

Signal assignment statement on line 169:

169: '0';
Count: 4413
Threshold: 1

Signal assignment statement on line 172:

172: retr_ctr <= std_logic_vector(retr_ctr_q);
Count: 4515
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 143:

143: retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else

	Evaluated to	Count	Threshold
Bin	True	20838	1
Bin	False	68873	1

"if" / "when" / "else" condition on line 144:

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else

	Evaluated to	Count	Threshold
Bin	True	30743	1
Bin	False	38130	1

"if" / "when" / "else" condition on line 148:

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')

	Evaluated to	Count	Threshold
Bin	True	50305	1
Bin	False	36492	1

"if" / "when" / "else" condition on line 157:

157: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 159:

159: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 160:

160: if (retr_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	31679	1
Bin	False	543759999	1

"if" / "when" / "else" condition on line 167:

167: retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q)

	Evaluated to	Count	Threshold
Bin	True	1853	1
Bin	False	4413	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_CHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RETR_CTR_CLEAR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RETR_CTR_ADD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_RTRTH

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

RETR_LIMIT_REACHED

	From	To	Count	Threshold
Bin	0	1	1853	1
Bin	1	0	1854	1

Port:

RETR_CTR

	Element	From	To	Count	Threshold
Bin	(3)	0	1	54	1
Bin	(3)	1	0	1655	1
Bin	(2)	0	1	140	1
Bin	(2)	1	0	1741	1
Bin	(1)	0	1	257	1
Bin	(1)	1	0	1858	1
Bin	(0)	0	1	642	1
Bin	(0)	1	0	2242	1

Signal:

RETR_CTR_D

	Element	From	To	Count	Threshold
Bin	(3)	0	1	152	1
Bin	(3)	1	0	1753	1
Bin	(2)	0	1	378	1
Bin	(2)	1	0	1979	1
Bin	(1)	0	1	960	1
Bin	(1)	1	0	2561	1
Bin	(0)	0	1	11103	1
Bin	(0)	1	0	12703	1

Signal:

RETR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(3)	0	1	54	1
Bin	(3)	1	0	1655	1
Bin	(2)	0	1	140	1
Bin	(2)	1	0	1741	1
Bin	(1)	0	1	257	1
Bin	(1)	1	0	1858	1
Bin	(0)	0	1	642	1
Bin	(0)	1	0	2242	1

Signal:

RETR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	31689	1
Bin	1	0	33290	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 143:

retr_ctr_add = '1'

	Evaluated to	Count	Threshold
Bin	False	68873	1
Bin	True	20838	1

"or" expression on line 144:

 retr_ctr_clear = '1' or txtb_changed = '1' 
 <-------LHS-------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	38130	1
Bin	False	True	10064	1
Bin	True	False	20679	1

"=" expression on line 144:

retr_ctr_clear = '1'

	Evaluated to	Count	Threshold
Bin	False	48194	1
Bin	True	20679	1

"=" expression on line 144:

txtb_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	58809	1
Bin	True	10064	1

"or" expression on line 148:

 txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1' 
 <------------------LHS------------------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	36492	1
Bin	False	True	10291	1
Bin	True	False	30578	1

"or" expression on line 148:

 txtb_changed = '1' or retr_ctr_clear = '1' 
 <------LHS------->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	46783	1
Bin	False	True	29994	1
Bin	True	False	10020	1

"=" expression on line 148:

txtb_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	76777	1
Bin	True	10020	1

"=" expression on line 148:

retr_ctr_clear = '1'

	Evaluated to	Count	Threshold
Bin	False	56803	1
Bin	True	29994	1

"=" expression on line 148:

retr_ctr_add = '1'

	Evaluated to	Count	Threshold
Bin	False	67070	1
Bin	True	19727	1

"=" expression on line 157:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 160:

retr_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543759999	1
Bin	True	31679	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RETRANSMITT_COUNTER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 143 to 145:

Signal assignment statement on line 143:

Signal assignment statement on line 144:

Signal assignment statement on line 145:

If statement on lines 148 to 150:

Signal assignment statement on line 148:

Signal assignment statement on line 150:

If statement on lines 157 to 163:

Signal assignment statement on line 158:

If statement on lines 160 to 162:

Signal assignment statement on line 161:

If statement on lines 167 to 169:

Signal assignment statement on line 167:

Signal assignment statement on line 169:

Signal assignment statement on line 172:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 143:

"if" / "when" / "else" condition on line 144:

"if" / "when" / "else" condition on line 148:

"if" / "when" / "else" condition on line 157:

"if" / "when" / "else" condition on line 159:

"if" / "when" / "else" condition on line 160:

"if" / "when" / "else" condition on line 167:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 143:

"or" expression on line 144:

"=" expression on line 144:

"=" expression on line 144:

"or" expression on line 148:

"or" expression on line 148:

"=" expression on line 148:

"=" expression on line 148:

"=" expression on line 148:

"=" expression on line 157:

"=" expression on line 160:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: