NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RETRANSMITT_COUNTER_INST	100.0 % (15/15)	100.0 % (14/14)	100.0 % (46/46)	100.0 % (25/25)	N.A.	N.A.	100.0 % (100/100)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

143:    retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else 
144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else 
145:                   retr_ctr_q;

Count: 87897
Threshold: 1

Signal assignment statement:

143: retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else
Count: 19948
Threshold: 1

Signal assignment statement:

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else

Count: 30296
Threshold: 1

Signal assignment statement:

145: retr_ctr_q;
Count: 37653
Threshold: 1

If statement:

148:    retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1') 
149:                       else 
150:                   '0';

Count: 85008
Threshold: 1

Signal assignment statement:

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')
Count: 48992
Threshold: 1

Signal assignment statement:

150: '0';
Count: 36016
Threshold: 1

If statement:

157:        if (res_n = '0') then 
158:            retr_ctr_q <= (others => '0'); 
...
162:            end if; 
163:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

158: retr_ctr_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

160:            if (retr_ctr_ce = '1') then 
161:                retr_ctr_q <= retr_ctr_d; 
162:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

161: retr_ctr_q <= retr_ctr_d;
Count: 31206
Threshold: 1

If statement:

167:    retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q) 
168:                              else 
169:                          '0';

Count: 6239
Threshold: 1

Signal assignment statement:

167: retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q)
Count: 1853
Threshold: 1

Signal assignment statement:

169: '0';
Count: 4386
Threshold: 1

Signal assignment statement:

172: retr_ctr <= std_logic_vector(retr_ctr_q);
Count: 4489
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

143: retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else

	Evaluated to	Count	Threshold
Bin	True	19948	1
Bin	False	67949	1

"if" / "when" / "else" condition:

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else

	Evaluated to	Count	Threshold
Bin	True	30296	1
Bin	False	37653	1

"if" / "when" / "else" condition:

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')

	Evaluated to	Count	Threshold
Bin	True	48992	1
Bin	False	36016	1

"if" / "when" / "else" condition:

157: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

159: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

160: if (retr_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	31206	1
Bin	False	526343094	1

"if" / "when" / "else" condition:

167: retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q)

	Evaluated to	Count	Threshold
Bin	True	1853	1
Bin	False	4386	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

TXTB_CHANGED

	From	To	Count	Threshold
Bin	0	1	10007	1
Bin	1	0	11607	1

Port:

RETR_CTR_CLEAR

	From	To	Count	Threshold
Bin	0	1	20123	1
Bin	1	0	21723	1

Port:

RETR_CTR_ADD

	From	To	Count	Threshold
Bin	0	1	10101	1
Bin	1	0	11701	1

Port:

MR_SETTINGS_RTRTH(3)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	1622	1

Port:

MR_SETTINGS_RTRTH(2)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1654	1

Port:

MR_SETTINGS_RTRTH(1)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	1622	1

Port:

MR_SETTINGS_RTRTH(0)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1654	1

Port:

RETR_LIMIT_REACHED

	From	To	Count	Threshold
Bin	0	1	1853	1
Bin	1	0	1853	1

Port:

RETR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1652	1

Port:

RETR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	1732	1

Port:

RETR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	1855	1

Port:

RETR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	629	1
Bin	1	0	2229	1

Signal:

RETR_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	146	1
Bin	1	0	1746	1

Signal:

RETR_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	365	1
Bin	1	0	1965	1

Signal:

RETR_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	948	1
Bin	1	0	2548	1

Signal:

RETR_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	10639	1
Bin	1	0	12239	1

Signal:

RETR_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1652	1

Signal:

RETR_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	1732	1

Signal:

RETR_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	1855	1

Signal:

RETR_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	629	1
Bin	1	0	2229	1

Signal:

RETR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	31216	1
Bin	1	0	32816	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

143: retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else

	Evaluated to	Count	Threshold
Bin	False	67949	1
Bin	True	19948	1

"=" expression

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else

	Evaluated to	Count	Threshold
Bin	False	47703	1
Bin	True	20246	1

"=" expression

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else

	Evaluated to	Count	Threshold
Bin	False	57899	1
Bin	True	10050	1

"or" expression

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else 
                                             <-------LHS-------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	37653	1
Bin	False	True	10050	1
Bin	True	False	20246	1

"=" expression

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')

	Evaluated to	Count	Threshold
Bin	False	75001	1
Bin	True	10007	1

"=" expression

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')

	Evaluated to	Count	Threshold
Bin	False	55870	1
Bin	True	29138	1

"or" expression

148:    retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1') 
                                 <------LHS------->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	45863	1
Bin	False	True	29138	1
Bin	True	False	10007	1

"=" expression

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')

	Evaluated to	Count	Threshold
Bin	False	66146	1
Bin	True	18862	1

"or" expression

148:    retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1') 
                                 <------------------LHS------------------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	36016	1
Bin	False	True	9847	1
Bin	True	False	30130	1

"=" expression

157: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

160: if (retr_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526343094	1
Bin	True	31206	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RETRANSMITT_COUNTER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/retransmitt_counter.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"=" expression

"or" expression

"=" expression

"=" expression

"or" expression

"=" expression

"or" expression

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: