NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 27274
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 27274
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 872768
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 27274
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	1757	1
Bin	1	0	2377	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	1610	1
Bin	1	0	2230	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	1512	1
Bin	1	0	2132	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	4104	1
Bin	1	0	4702	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	3910	1
Bin	1	0	4510	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	3844	1
Bin	1	0	4448	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	3736	1
Bin	1	0	4341	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	3799	1
Bin	1	0	4395	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	4294	1
Bin	1	0	4894	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	4713	1
Bin	1	0	5308	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	4451	1
Bin	1	0	5053	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	4089	1
Bin	1	0	4685	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	4711	1
Bin	1	0	5306	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	4503	1
Bin	1	0	5102	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	2976	1
Bin	1	0	3589	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	2682	1
Bin	1	0	3296	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	2889	1
Bin	1	0	3500	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	2997	1
Bin	1	0	3607	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	3106	1
Bin	1	0	3721	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	3071	1
Bin	1	0	3680	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	2923	1
Bin	1	0	3537	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	2997	1
Bin	1	0	3610	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	4778	1
Bin	1	0	5375	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	3431	1
Bin	1	0	4042	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	5870	1
Bin	1	0	6453	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	4542	1
Bin	1	0	5134	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	4194	1
Bin	1	0	4797	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	2969	1
Bin	1	0	3579	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	3881	1
Bin	1	0	4483	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	4745	1
Bin	1	0	5338	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	4721	1
Bin	1	0	5307	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	4644	1
Bin	1	0	5233	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	6892	1
Bin	1	0	6323	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	197096	1
Bin	'0'	'1'	67896	1
Bin	'1'	'0'	509585	1
Bin	'1'	'1'	77071	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

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Loop statement:

Variable assignment statement:

Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: