NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST.TX_SHIFT_REG_INST	100.0 % (5/5)	100.0 % (8/8)	100.0 % (202/202)	100.0 % (6/6)	N.A.	N.A.	100.0 % (221/221)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

136:        if (res_n = G_RESET_POLARITY) then 
137:            shift_regs <= G_RESET_VALUE; 
...
144:            end if; 
145:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

137: shift_regs <= G_RESET_VALUE;
Count: 2418499
Threshold: 1

If statement:

140:            if (preload = '1') then 
141:                shift_regs <= preload_val; 
142:            elsif (enable = '1') then 
143:                shift_regs <= shift_regs(G_WIDTH - 2 downto 0) & '0'; 
144:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

141: shift_regs <= preload_val;
Count: 312460
Threshold: 1

Signal assignment statement:

143: shift_regs <= shift_regs(G_WIDTH - 2 downto 0) & '0';
Count: 2335772
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

136: if (res_n = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

139: elsif (rising_edge(clk)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

140: if (preload = '1') then

	Evaluated to	Count	Threshold
Bin	True	312460	1
Bin	False	526061840	1

"if" / "when" / "else" condition:

142: elsif (enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	2335772	1
Bin	False	523726068	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

PRELOAD

	From	To	Count	Threshold
Bin	0	1	410629	1
Bin	1	0	412229	1

Port:

PRELOAD_VAL(31)

	From	To	Count	Threshold
Bin	0	1	105846	1
Bin	1	0	107446	1

Port:

PRELOAD_VAL(30)

	From	To	Count	Threshold
Bin	0	1	104450	1
Bin	1	0	106050	1

Port:

PRELOAD_VAL(29)

	From	To	Count	Threshold
Bin	0	1	112824	1
Bin	1	0	114424	1

Port:

PRELOAD_VAL(28)

	From	To	Count	Threshold
Bin	0	1	119499	1
Bin	1	0	121099	1

Port:

PRELOAD_VAL(27)

	From	To	Count	Threshold
Bin	0	1	83707	1
Bin	1	0	85307	1

Port:

PRELOAD_VAL(26)

	From	To	Count	Threshold
Bin	0	1	84455	1
Bin	1	0	86055	1

Port:

PRELOAD_VAL(25)

	From	To	Count	Threshold
Bin	0	1	83539	1
Bin	1	0	85139	1

Port:

PRELOAD_VAL(24)

	From	To	Count	Threshold
Bin	0	1	85742	1
Bin	1	0	87342	1

Port:

PRELOAD_VAL(23)

	From	To	Count	Threshold
Bin	0	1	81197	1
Bin	1	0	82797	1

Port:

PRELOAD_VAL(22)

	From	To	Count	Threshold
Bin	0	1	84984	1
Bin	1	0	86584	1

Port:

PRELOAD_VAL(21)

	From	To	Count	Threshold
Bin	0	1	85474	1
Bin	1	0	87074	1

Port:

PRELOAD_VAL(20)

	From	To	Count	Threshold
Bin	0	1	61057	1
Bin	1	0	62657	1

Port:

PRELOAD_VAL(19)

	From	To	Count	Threshold
Bin	0	1	59586	1
Bin	1	0	61186	1

Port:

PRELOAD_VAL(18)

	From	To	Count	Threshold
Bin	0	1	60919	1
Bin	1	0	62519	1

Port:

PRELOAD_VAL(17)

	From	To	Count	Threshold
Bin	0	1	60469	1
Bin	1	0	62069	1

Port:

PRELOAD_VAL(16)

	From	To	Count	Threshold
Bin	0	1	48471	1
Bin	1	0	50071	1

Port:

PRELOAD_VAL(15)

	From	To	Count	Threshold
Bin	0	1	43823	1
Bin	1	0	45423	1

Port:

PRELOAD_VAL(14)

	From	To	Count	Threshold
Bin	0	1	35897	1
Bin	1	0	37497	1

Port:

PRELOAD_VAL(13)

	From	To	Count	Threshold
Bin	0	1	26174	1
Bin	1	0	27774	1

Port:

PRELOAD_VAL(12)

	From	To	Count	Threshold
Bin	0	1	29146	1
Bin	1	0	30746	1

Port:

PRELOAD_VAL(11)

	From	To	Count	Threshold
Bin	0	1	26227	1
Bin	1	0	27827	1

Port:

PRELOAD_VAL(10)

	From	To	Count	Threshold
Bin	0	1	26754	1
Bin	1	0	28354	1

Port:

PRELOAD_VAL(9)

	From	To	Count	Threshold
Bin	0	1	23717	1
Bin	1	0	25317	1

Port:

PRELOAD_VAL(8)

	From	To	Count	Threshold
Bin	0	1	26260	1
Bin	1	0	27860	1

Port:

PRELOAD_VAL(7)

	From	To	Count	Threshold
Bin	0	1	22776	1
Bin	1	0	24376	1

Port:

PRELOAD_VAL(6)

	From	To	Count	Threshold
Bin	0	1	25620	1
Bin	1	0	27220	1

Port:

PRELOAD_VAL(5)

	From	To	Count	Threshold
Bin	0	1	22739	1
Bin	1	0	24339	1

Port:

PRELOAD_VAL(4)

	From	To	Count	Threshold
Bin	0	1	25811	1
Bin	1	0	27411	1

Port:

PRELOAD_VAL(3)

	From	To	Count	Threshold
Bin	0	1	23048	1
Bin	1	0	24648	1

Port:

PRELOAD_VAL(2)

	From	To	Count	Threshold
Bin	0	1	26097	1
Bin	1	0	27697	1

Port:

PRELOAD_VAL(1)

	From	To	Count	Threshold
Bin	0	1	23198	1
Bin	1	0	24798	1

Port:

PRELOAD_VAL(0)

	From	To	Count	Threshold
Bin	0	1	25565	1
Bin	1	0	27165	1

Port:

ENABLE

	From	To	Count	Threshold
Bin	0	1	2648733	1
Bin	1	0	2650333	1

Port:

REG_STAT(31)

	From	To	Count	Threshold
Bin	0	1	524281	1
Bin	1	0	525880	1

Port:

REG_STAT(30)

	From	To	Count	Threshold
Bin	0	1	499822	1
Bin	1	0	501420	1

Port:

REG_STAT(29)

	From	To	Count	Threshold
Bin	0	1	475051	1
Bin	1	0	476650	1

Port:

REG_STAT(28)

	From	To	Count	Threshold
Bin	0	1	450945	1
Bin	1	0	452544	1

Port:

REG_STAT(27)

	From	To	Count	Threshold
Bin	0	1	411017	1
Bin	1	0	412614	1

Port:

REG_STAT(26)

	From	To	Count	Threshold
Bin	0	1	392133	1
Bin	1	0	393732	1

Port:

REG_STAT(25)

	From	To	Count	Threshold
Bin	0	1	369207	1
Bin	1	0	370805	1

Port:

REG_STAT(24)

	From	To	Count	Threshold
Bin	0	1	350532	1
Bin	1	0	352131	1

Port:

REG_STAT(23)

	From	To	Count	Threshold
Bin	0	1	326417	1
Bin	1	0	328015	1

Port:

REG_STAT(22)

	From	To	Count	Threshold
Bin	0	1	310449	1
Bin	1	0	312049	1

Port:

REG_STAT(21)

	From	To	Count	Threshold
Bin	0	1	287670	1
Bin	1	0	289269	1

Port:

REG_STAT(20)

	From	To	Count	Threshold
Bin	0	1	263419	1
Bin	1	0	265018	1

Port:

REG_STAT(19)

	From	To	Count	Threshold
Bin	0	1	246339	1
Bin	1	0	247937	1

Port:

REG_STAT(18)

	From	To	Count	Threshold
Bin	0	1	230735	1
Bin	1	0	232333	1

Port:

REG_STAT(17)

	From	To	Count	Threshold
Bin	0	1	217368	1
Bin	1	0	218967	1

Port:

REG_STAT(16)

	From	To	Count	Threshold
Bin	0	1	195632	1
Bin	1	0	197232	1

Port:

REG_STAT(15)

	From	To	Count	Threshold
Bin	0	1	180454	1
Bin	1	0	182052	1

Port:

REG_STAT(14)

	From	To	Count	Threshold
Bin	0	1	165133	1
Bin	1	0	166733	1

Port:

REG_STAT(13)

	From	To	Count	Threshold
Bin	0	1	150538	1
Bin	1	0	152138	1

Port:

REG_STAT(12)

	From	To	Count	Threshold
Bin	0	1	142103	1
Bin	1	0	143703	1

Port:

REG_STAT(11)

	From	To	Count	Threshold
Bin	0	1	131321	1
Bin	1	0	132921	1

Port:

REG_STAT(10)

	From	To	Count	Threshold
Bin	0	1	121995	1
Bin	1	0	123595	1

Port:

REG_STAT(9)

	From	To	Count	Threshold
Bin	0	1	110566	1
Bin	1	0	112166	1

Port:

REG_STAT(8)

	From	To	Count	Threshold
Bin	0	1	102189	1
Bin	1	0	103789	1

Port:

REG_STAT(7)

	From	To	Count	Threshold
Bin	0	1	91302	1
Bin	1	0	92902	1

Port:

REG_STAT(6)

	From	To	Count	Threshold
Bin	0	1	83082	1
Bin	1	0	84682	1

Port:

REG_STAT(5)

	From	To	Count	Threshold
Bin	0	1	72167	1
Bin	1	0	73767	1

Port:

REG_STAT(4)

	From	To	Count	Threshold
Bin	0	1	64409	1
Bin	1	0	66009	1

Port:

REG_STAT(3)

	From	To	Count	Threshold
Bin	0	1	53342	1
Bin	1	0	54942	1

Port:

REG_STAT(2)

	From	To	Count	Threshold
Bin	0	1	45476	1
Bin	1	0	47076	1

Port:

REG_STAT(1)

	From	To	Count	Threshold
Bin	0	1	34288	1
Bin	1	0	35888	1

Port:

REG_STAT(0)

	From	To	Count	Threshold
Bin	0	1	25547	1
Bin	1	0	27147	1

Port:

REG_OUTPUT

	From	To	Count	Threshold
Bin	0	1	524281	1
Bin	1	0	525880	1

Signal:

SHIFT_REGS(31)

	From	To	Count	Threshold
Bin	0	1	1135862	1
Bin	1	0	1147225	1

Signal:

SHIFT_REGS(30)

	From	To	Count	Threshold
Bin	0	1	499822	1
Bin	1	0	623276	1

Signal:

SHIFT_REGS(29)

	From	To	Count	Threshold
Bin	0	1	475052	1
Bin	1	0	476959	1

Signal:

SHIFT_REGS(28)

	From	To	Count	Threshold
Bin	0	1	450945	1
Bin	1	0	452842	1

Signal:

SHIFT_REGS(27)

	From	To	Count	Threshold
Bin	0	1	411017	1
Bin	1	0	412887	1

Signal:

SHIFT_REGS(26)

	From	To	Count	Threshold
Bin	0	1	392133	1
Bin	1	0	393991	1

Signal:

SHIFT_REGS(25)

	From	To	Count	Threshold
Bin	0	1	369207	1
Bin	1	0	371060	1

Signal:

SHIFT_REGS(24)

	From	To	Count	Threshold
Bin	0	1	350532	1
Bin	1	0	352366	1

Signal:

SHIFT_REGS(23)

	From	To	Count	Threshold
Bin	0	1	326417	1
Bin	1	0	328235	1

Signal:

SHIFT_REGS(22)

	From	To	Count	Threshold
Bin	0	1	310449	1
Bin	1	0	312249	1

Signal:

SHIFT_REGS(21)

	From	To	Count	Threshold
Bin	0	1	287670	1
Bin	1	0	289469	1

Signal:

SHIFT_REGS(20)

	From	To	Count	Threshold
Bin	0	1	263419	1
Bin	1	0	265211	1

Signal:

SHIFT_REGS(19)

	From	To	Count	Threshold
Bin	0	1	246339	1
Bin	1	0	248111	1

Signal:

SHIFT_REGS(18)

	From	To	Count	Threshold
Bin	0	1	230735	1
Bin	1	0	232498	1

Signal:

SHIFT_REGS(17)

	From	To	Count	Threshold
Bin	0	1	217368	1
Bin	1	0	219126	1

Signal:

SHIFT_REGS(16)

	From	To	Count	Threshold
Bin	0	1	195632	1
Bin	1	0	197375	1

Signal:

SHIFT_REGS(15)

	From	To	Count	Threshold
Bin	0	1	180454	1
Bin	1	0	182190	1

Signal:

SHIFT_REGS(14)

	From	To	Count	Threshold
Bin	0	1	165133	1
Bin	1	0	166862	1

Signal:

SHIFT_REGS(13)

	From	To	Count	Threshold
Bin	0	1	150538	1
Bin	1	0	152259	1

Signal:

SHIFT_REGS(12)

	From	To	Count	Threshold
Bin	0	1	142103	1
Bin	1	0	143820	1

Signal:

SHIFT_REGS(11)

	From	To	Count	Threshold
Bin	0	1	131321	1
Bin	1	0	133037	1

Signal:

SHIFT_REGS(10)

	From	To	Count	Threshold
Bin	0	1	121995	1
Bin	1	0	123703	1

Signal:

SHIFT_REGS(9)

	From	To	Count	Threshold
Bin	0	1	110566	1
Bin	1	0	112263	1

Signal:

SHIFT_REGS(8)

	From	To	Count	Threshold
Bin	0	1	102189	1
Bin	1	0	103876	1

Signal:

SHIFT_REGS(7)

	From	To	Count	Threshold
Bin	0	1	91302	1
Bin	1	0	92980	1

Signal:

SHIFT_REGS(6)

	From	To	Count	Threshold
Bin	0	1	83082	1
Bin	1	0	84755	1

Signal:

SHIFT_REGS(5)

	From	To	Count	Threshold
Bin	0	1	72167	1
Bin	1	0	73827	1

Signal:

SHIFT_REGS(4)

	From	To	Count	Threshold
Bin	0	1	64409	1
Bin	1	0	66063	1

Signal:

SHIFT_REGS(3)

	From	To	Count	Threshold
Bin	0	1	53342	1
Bin	1	0	54992	1

Signal:

SHIFT_REGS(2)

	From	To	Count	Threshold
Bin	0	1	45476	1
Bin	1	0	47122	1

Signal:

SHIFT_REGS(1)

	From	To	Count	Threshold
Bin	0	1	34288	1
Bin	1	0	35928	1

Signal:

SHIFT_REGS(0)

	From	To	Count	Threshold
Bin	0	1	25547	1
Bin	1	0	27178	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

136: if (res_n = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

140: if (preload = '1') then

	Evaluated to	Count	Threshold
Bin	False	526061840	1
Bin	True	312460	1

"=" expression

142: elsif (enable = '1') then

	Evaluated to	Count	Threshold
Bin	False	523726068	1
Bin	True	2335772	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST.TX_SHIFT_REG_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_preload.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

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