NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/tx_shift_reg.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST.TX_SHIFT_REG_INST	100.0 % (7/7)	100.0 % (8/8)	100.0 % (202/202)	100.0 % (6/6)	N.A.	N.A.	100.0 % (223/223)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST.TX_SHIFT_REG_INST

100.0 % (7/7)

100.0 % (8/8)

100.0 % (202/202)

100.0 % (6/6)

N.A.

100.0 % (223/223)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 129:

129: reg_output <= shift_regs(G_WIDTH - 1);
Count: 1050219
Threshold: 1

If statement on lines 136 to 145:

136:        if (res_n = G_RESET_POLARITY) then 
137:            shift_regs <= G_RESET_VALUE; 
...
144:            end if; 
145:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 137:

137: shift_regs <= G_RESET_VALUE;
Count: 2424883
Threshold: 1

If statement on lines 140 to 144:

140:            if (preload = '1') then 
141:                shift_regs <= preload_val; 
142:            elsif (enable = '1') then 
143:                shift_regs <= shift_regs(G_WIDTH - 2 downto 0) & '0'; 
144:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 141:

141: shift_regs <= preload_val;
Count: 315158
Threshold: 1

Signal assignment statement on line 143:

143: shift_regs <= shift_regs(G_WIDTH - 2 downto 0) & '0';
Count: 2333693
Threshold: 1

Signal assignment statement on line 151:

151: reg_stat <= shift_regs;
Count: 2280802
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 136:

136: if (res_n = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 139:

139: elsif (rising_edge(clk)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 140:

140: if (preload = '1') then

	Evaluated to	Count	Threshold
Bin	True	315158	1
Bin	False	543476520	1

"if" / "when" / "else" condition on line 142:

142: elsif (enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	2333693	1
Bin	False	541142827	1

Uncovered toggles:

Excluded toggles:

Port:

CLK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PRELOAD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PRELOAD_VAL

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

REG_STAT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	523509	1
Bin	(31)	1	0	525109	1
Bin	(30)	0	1	499625	1
Bin	(30)	1	0	501222	1
Bin	(29)	0	1	472920	1
Bin	(29)	1	0	474519	1
Bin	(28)	0	1	451779	1
Bin	(28)	1	0	453375	1
Bin	(27)	0	1	410614	1
Bin	(27)	1	0	412214	1
Bin	(26)	0	1	393223	1
Bin	(26)	1	0	394821	1
Bin	(25)	0	1	369118	1
Bin	(25)	1	0	370717	1
Bin	(24)	0	1	348891	1
Bin	(24)	1	0	350490	1
Bin	(23)	0	1	326842	1
Bin	(23)	1	0	328441	1
Bin	(22)	0	1	306968	1
Bin	(22)	1	0	308568	1
Bin	(21)	0	1	287362	1
Bin	(21)	1	0	288960	1
Bin	(20)	0	1	261488	1
Bin	(20)	1	0	263086	1
Bin	(19)	0	1	245221	1
Bin	(19)	1	0	246820	1
Bin	(18)	0	1	232109	1
Bin	(18)	1	0	233709	1
Bin	(17)	0	1	218358	1
Bin	(17)	1	0	219957	1
Bin	(16)	0	1	196318	1
Bin	(16)	1	0	197917	1
Bin	(15)	0	1	181346	1
Bin	(15)	1	0	182947	1
Bin	(14)	0	1	165204	1
Bin	(14)	1	0	166805	1
Bin	(13)	0	1	149839	1
Bin	(13)	1	0	151440	1
Bin	(12)	0	1	141276	1
Bin	(12)	1	0	142877	1
Bin	(11)	0	1	130670	1
Bin	(11)	1	0	132271	1
Bin	(10)	0	1	120650	1
Bin	(10)	1	0	122251	1
Bin	(9)	0	1	109656	1
Bin	(9)	1	0	111257	1
Bin	(8)	0	1	101449	1
Bin	(8)	1	0	103050	1
Bin	(7)	0	1	90701	1
Bin	(7)	1	0	92302	1
Bin	(6)	0	1	82501	1
Bin	(6)	1	0	84102	1
Bin	(5)	0	1	72291	1
Bin	(5)	1	0	73892	1
Bin	(4)	0	1	64185	1
Bin	(4)	1	0	65786	1
Bin	(3)	0	1	53426	1
Bin	(3)	1	0	55027	1
Bin	(2)	0	1	44967	1
Bin	(2)	1	0	46568	1
Bin	(1)	0	1	33841	1
Bin	(1)	1	0	35442	1
Bin	(0)	0	1	26216	1
Bin	(0)	1	0	27817	1

Port:

REG_OUTPUT

	From	To	Count	Threshold
Bin	0	1	523509	1
Bin	1	0	525109	1

Signal:

SHIFT_REGS

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1127212	1
Bin	(31)	1	0	1151989	1
Bin	(30)	0	1	499626	1
Bin	(30)	1	0	622877	1
Bin	(29)	0	1	472922	1
Bin	(29)	1	0	474823	1
Bin	(28)	0	1	451779	1
Bin	(28)	1	0	453658	1
Bin	(27)	0	1	410615	1
Bin	(27)	1	0	412478	1
Bin	(26)	0	1	393223	1
Bin	(26)	1	0	395071	1
Bin	(25)	0	1	369118	1
Bin	(25)	1	0	370959	1
Bin	(24)	0	1	348891	1
Bin	(24)	1	0	350717	1
Bin	(23)	0	1	326842	1
Bin	(23)	1	0	328661	1
Bin	(22)	0	1	306968	1
Bin	(22)	1	0	308776	1
Bin	(21)	0	1	287362	1
Bin	(21)	1	0	289168	1
Bin	(20)	0	1	261488	1
Bin	(20)	1	0	263280	1
Bin	(19)	0	1	245221	1
Bin	(19)	1	0	247006	1
Bin	(18)	0	1	232109	1
Bin	(18)	1	0	233882	1
Bin	(17)	0	1	218358	1
Bin	(17)	1	0	220129	1
Bin	(16)	0	1	196318	1
Bin	(16)	1	0	198073	1
Bin	(15)	0	1	181346	1
Bin	(15)	1	0	183095	1
Bin	(14)	0	1	165204	1
Bin	(14)	1	0	166941	1
Bin	(13)	0	1	149839	1
Bin	(13)	1	0	151576	1
Bin	(12)	0	1	141276	1
Bin	(12)	1	0	143003	1
Bin	(11)	0	1	130670	1
Bin	(11)	1	0	132395	1
Bin	(10)	0	1	120650	1
Bin	(10)	1	0	122367	1
Bin	(9)	0	1	109656	1
Bin	(9)	1	0	111373	1
Bin	(8)	0	1	101449	1
Bin	(8)	1	0	103154	1
Bin	(7)	0	1	90701	1
Bin	(7)	1	0	92402	1
Bin	(6)	0	1	82501	1
Bin	(6)	1	0	84194	1
Bin	(5)	0	1	72291	1
Bin	(5)	1	0	73980	1
Bin	(4)	0	1	64185	1
Bin	(4)	1	0	65868	1
Bin	(3)	0	1	53426	1
Bin	(3)	1	0	55103	1
Bin	(2)	0	1	44967	1
Bin	(2)	1	0	46636	1
Bin	(1)	0	1	33841	1
Bin	(1)	1	0	35500	1
Bin	(0)	0	1	26216	1
Bin	(0)	1	0	27865	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 136:

res_n = G_RESET_POLARITY

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 140:

preload = '1'

	Evaluated to	Count	Threshold
Bin	False	543476520	1
Bin	True	315158	1

"=" expression on line 142:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	541142827	1
Bin	True	2333693	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST.TX_SHIFT_REG_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/tx_shift_reg.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 129:

If statement on lines 136 to 145:

Signal assignment statement on line 137:

If statement on lines 140 to 144:

Signal assignment statement on line 141:

Signal assignment statement on line 143:

Signal assignment statement on line 151:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 136:

"if" / "when" / "else" condition on line 139:

"if" / "when" / "else" condition on line 140:

"if" / "when" / "else" condition on line 142:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 136:

"=" expression on line 140:

"=" expression on line 142:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: