NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TX_SHIFT_REG_INST	100.0 % (5/5)	100.0 % (8/8)	100.0 % (202/202)	100.0 % (6/6)	N.A.	N.A.	100.0 % (221/221)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST	100.0 % (47/47)	100.0 % (44/44)	100.0 % (578/578)	100.0 % (80/80)	N.A.	N.A.	100.0 % (749/749)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

234:    tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1') 
235:                    else 
236:                '0';

Count: 22201277
Threshold: 1

Signal assignment statement:

234: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')
Count: 2648733
Threshold: 1

Signal assignment statement:

236: '0';
Count: 19552544
Threshold: 1

If statement:

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or 
...
245:                       else 
246:                   '0';

Count: 877054
Threshold: 1

Signal assignment statement:

239: tx_sr_pload <= '1' when (tx_load_base_id = '1' or
Count: 463225
Threshold: 1

Signal assignment statement:

246: '0';
Count: 413829
Threshold: 1

If statement:

249:    tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else 
250:                crc_17 & "0000" when (crc_src = C_CRC17_SRC) else 
251:                        crc_21;

Count: 8783108
Threshold: 1

Signal assignment statement:

249: tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else
Count: 1546936
Threshold: 1

Signal assignment statement:

250: crc_17 & "0000" when (crc_src = C_CRC17_SRC) else
Count: 1140180
Threshold: 1

Signal assignment statement:

251: crc_21;
Count: 6095992
Threshold: 1

Sequential statement:

254:    with bst_ctr select bst_ctr_grey <= 
255:        "001" when "001", 
...
261:        "100" when "111", 
262:        "000" when others;

Count: 294521
Threshold: 1

Signal assignment statement:

255: "001" when "001",
Count: 47065
Threshold: 1

Signal assignment statement:

256: "011" when "010",
Count: 42382
Threshold: 1

Signal assignment statement:

257: "010" when "011",
Count: 37460
Threshold: 1

Signal assignment statement:

258: "110" when "100",
Count: 33334
Threshold: 1

Signal assignment statement:

259: "111" when "101",
Count: 29788
Threshold: 1

Signal assignment statement:

260: "101" when "110",
Count: 27843
Threshold: 1

Signal assignment statement:

261: "100" when "111",
Count: 26387
Threshold: 1

Signal assignment statement:

262: "000" when others;
Count: 50262
Threshold: 1

Signal assignment statement:

264: bst_parity <= bst_ctr_grey(0) xor bst_ctr_grey(1) xor bst_ctr_grey(2);
Count: 294521
Threshold: 1

Signal assignment statement:

266: stuff_count <= bst_ctr_grey & bst_parity;
Count: 577519
Threshold: 1

Signal assignment statement:

277: flip_mask <= (others => '0');
Count: 8753
Threshold: 1

If statement:

278:        if (mr_mode_tstm = '1') then 
279:            flip_mask(20 - to_integer(unsigned(tran_frame_test.tprm))) <= '1'; 
280:        end if;

Count: 8753
Threshold: 1

Signal assignment statement:

279: flip_mask(20 - to_integer(unsigned(tran_frame_test.tprm))) <= '1';
Count: 2827
Threshold: 1

If statement:

284:    tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1') 
285:                                             else 
286:                                      tx_crc;

Count: 6794471
Threshold: 1

Signal assignment statement:

284: tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1')
Count: 78586
Threshold: 1

Signal assignment statement:

286: tx_crc;
Count: 6715885
Threshold: 1

If statement:

289:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1') 
290:                                                                     else 
291:                                                         stuff_count;

Count: 584095
Threshold: 1

Signal assignment statement:

289:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1')

Count: 2118
Threshold: 1

Signal assignment statement:

291:                                                         stuff_count;

Count: 581977
Threshold: 1

If statement:

294:    tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and 
295:                                                               mr_mode_tstm = '1') 
296:                                                         else 
297:                                                tran_dlc;

Count: 21386
Threshold: 1

Signal assignment statement:

294: tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and
Count: 220
Threshold: 1

Signal assignment statement:

297: tran_dlc;
Count: 21166
Threshold: 1

If statement:

307:    tx_sr_pload_val <= 
308:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else 
...
313:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else 
314:                                        (others => '0');

Count: 8243528
Threshold: 1

Signal assignment statement:

308:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else

Count: 49717
Threshold: 1

Signal assignment statement:

309:                            tx_ext_id & "00000000000000" when (tx_load_ext_id = '1') else

Count: 37532
Threshold: 1

Signal assignment statement:

310: tran_dlc_swapped & "0000000000000000000000000000" when (tx_load_dlc = '1') else
Count: 121205
Threshold: 1

Signal assignment statement:

311:                                       tran_word_swapped when (tx_load_data_word = '1') else

Count: 157486
Threshold: 1

Signal assignment statement:

312: stuff_count_flipped & "0000000000000000000000000000" when (tx_load_stuff_count = '1') else
Count: 40197
Threshold: 1

Signal assignment statement:

313:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else

Count: 57101
Threshold: 1

Signal assignment statement:

314: (others => '0');
Count: 7780290
Threshold: 1

If statement:

339:    tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else 
340:                   RECESSIVE when (err_frm_req = '1') else 
341:                   DOMINANT when (tx_dominant = '1') else 
342:                   tx_sr_output when (tx_shift_ena = '1') else 
343:                   RECESSIVE;

Count: 1426539
Threshold: 1

Signal assignment statement:

339: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else
Count: 30326
Threshold: 1

Signal assignment statement:

340: RECESSIVE when (err_frm_req = '1') else
Count: 12269
Threshold: 1

Signal assignment statement:

341: DOMINANT when (tx_dominant = '1') else
Count: 123542
Threshold: 1

Signal assignment statement:

342: tx_sr_output when (tx_shift_ena = '1') else
Count: 1066804
Threshold: 1

Signal assignment statement:

343: RECESSIVE;
Count: 193598
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

234: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')

	Evaluated to	Count	Threshold
Bin	True	2648733	1
Bin	False	19552544	1

"if" / "when" / "else" condition:

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or 
241:                             tx_load_dlc = '1' or 
242:                             tx_load_data_word = '1' or 
243:                             tx_load_stuff_count = '1' or 
244:                             tx_load_crc = '1')

	Evaluated to	Count	Threshold
Bin	True	463225	1
Bin	False	413829	1

"if" / "when" / "else" condition:

249: tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else

	Evaluated to	Count	Threshold
Bin	True	1546936	1
Bin	False	7236172	1

"if" / "when" / "else" condition:

250: crc_17 & "0000" when (crc_src = C_CRC17_SRC) else

	Evaluated to	Count	Threshold
Bin	True	1140180	1
Bin	False	6095992	1

"case" / "with" / "select" choice:

255: "001" when "001",

	Choice of	Count	Threshold
Bin	`"001"`	47065	1

"case" / "with" / "select" choice:

256: "011" when "010",

	Choice of	Count	Threshold
Bin	`"010"`	42382	1

"case" / "with" / "select" choice:

257: "010" when "011",

	Choice of	Count	Threshold
Bin	`"011"`	37460	1

"case" / "with" / "select" choice:

258: "110" when "100",

	Choice of	Count	Threshold
Bin	`"100"`	33334	1

"case" / "with" / "select" choice:

259: "111" when "101",

	Choice of	Count	Threshold
Bin	`"101"`	29788	1

"case" / "with" / "select" choice:

260: "101" when "110",

	Choice of	Count	Threshold
Bin	`"110"`	27843	1

"case" / "with" / "select" choice:

261: "100" when "111",

	Choice of	Count	Threshold
Bin	`"111"`	26387	1

"case" / "with" / "select" choice:

262: "000" when others;

	Choice of	Count	Threshold
Bin	`others`	50262	1

"if" / "when" / "else" condition:

278: if (mr_mode_tstm = '1') then

	Evaluated to	Count	Threshold
Bin	True	2827	1
Bin	False	5926	1

"if" / "when" / "else" condition:

284: tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1')

	Evaluated to	Count	Threshold
Bin	True	78586	1
Bin	False	6715885	1

"if" / "when" / "else" condition:

289:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1')

	Evaluated to	Count	Threshold
Bin	True	2118	1
Bin	False	581977	1

"if" / "when" / "else" condition:

294:    tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and 
295:                                                               mr_mode_tstm = '1')

	Evaluated to	Count	Threshold
Bin	True	220	1
Bin	False	21166	1

"if" / "when" / "else" condition:

308:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else

	Evaluated to	Count	Threshold
Bin	True	49717	1
Bin	False	8193811	1

"if" / "when" / "else" condition:

309:                            tx_ext_id & "00000000000000" when (tx_load_ext_id = '1') else

	Evaluated to	Count	Threshold
Bin	True	37532	1
Bin	False	8156279	1

"if" / "when" / "else" condition:

310: tran_dlc_swapped & "0000000000000000000000000000" when (tx_load_dlc = '1') else

	Evaluated to	Count	Threshold
Bin	True	121205	1
Bin	False	8035074	1

"if" / "when" / "else" condition:

311:                                       tran_word_swapped when (tx_load_data_word = '1') else

	Evaluated to	Count	Threshold
Bin	True	157486	1
Bin	False	7877588	1

"if" / "when" / "else" condition:

312: stuff_count_flipped & "0000000000000000000000000000" when (tx_load_stuff_count = '1') else

	Evaluated to	Count	Threshold
Bin	True	40197	1
Bin	False	7837391	1

"if" / "when" / "else" condition:

313:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else

	Evaluated to	Count	Threshold
Bin	True	57101	1
Bin	False	7780290	1

"if" / "when" / "else" condition:

339: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else

	Evaluated to	Count	Threshold
Bin	True	30326	1
Bin	False	1396213	1

"if" / "when" / "else" condition:

340: RECESSIVE when (err_frm_req = '1') else

	Evaluated to	Count	Threshold
Bin	True	12269	1
Bin	False	1383944	1

"if" / "when" / "else" condition:

341: DOMINANT when (tx_dominant = '1') else

	Evaluated to	Count	Threshold
Bin	True	123542	1
Bin	False	1260402	1

"if" / "when" / "else" condition:

342: tx_sr_output when (tx_shift_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	1066804	1
Bin	False	193598	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

MR_MODE_TSTM

	From	To	Count	Threshold
Bin	0	1	1027	1
Bin	1	0	2626	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

TX_DATA_NBS

	From	To	Count	Threshold
Bin	0	1	644444	1
Bin	1	0	642846	1

Port:

TX_LOAD_BASE_ID

	From	To	Count	Threshold
Bin	0	1	49704	1
Bin	1	0	51304	1

Port:

TX_LOAD_EXT_ID

	From	To	Count	Threshold
Bin	0	1	37532	1
Bin	1	0	39132	1

Port:

TX_LOAD_DLC

	From	To	Count	Threshold
Bin	0	1	121205	1
Bin	1	0	122805	1

Port:

TX_LOAD_DATA_WORD

	From	To	Count	Threshold
Bin	0	1	157486	1
Bin	1	0	159086	1

Port:

TX_LOAD_STUFF_COUNT

	From	To	Count	Threshold
Bin	0	1	40197	1
Bin	1	0	41797	1

Port:

TX_LOAD_CRC

	From	To	Count	Threshold
Bin	0	1	57101	1
Bin	1	0	58701	1

Port:

TX_SHIFT_ENA

	From	To	Count	Threshold
Bin	0	1	55036	1
Bin	1	0	56636	1

Port:

TX_DOMINANT

	From	To	Count	Threshold
Bin	0	1	102910	1
Bin	1	0	104508	1

Port:

CRC_SRC(1)

	From	To	Count	Threshold
Bin	0	1	24595	1
Bin	1	0	26195	1

Port:

CRC_SRC(0)

	From	To	Count	Threshold
Bin	0	1	28233	1
Bin	1	0	29829	1

Port:

CRC_15(14)

	From	To	Count	Threshold
Bin	0	1	1452642	1
Bin	1	0	1454241	1

Port:

CRC_15(13)

	From	To	Count	Threshold
Bin	0	1	1404381	1
Bin	1	0	1405979	1

Port:

CRC_15(12)

	From	To	Count	Threshold
Bin	0	1	1416815	1
Bin	1	0	1418414	1

Port:

CRC_15(11)

	From	To	Count	Threshold
Bin	0	1	1431040	1
Bin	1	0	1432636	1

Port:

CRC_15(10)

	From	To	Count	Threshold
Bin	0	1	1444591	1
Bin	1	0	1446189	1

Port:

CRC_15(9)

	From	To	Count	Threshold
Bin	0	1	1438246	1
Bin	1	0	1439842	1

Port:

CRC_15(8)

	From	To	Count	Threshold
Bin	0	1	1452223	1
Bin	1	0	1453819	1

Port:

CRC_15(7)

	From	To	Count	Threshold
Bin	0	1	1489085	1
Bin	1	0	1490683	1

Port:

CRC_15(6)

	From	To	Count	Threshold
Bin	0	1	1428572	1
Bin	1	0	1430168	1

Port:

CRC_15(5)

	From	To	Count	Threshold
Bin	0	1	1442138	1
Bin	1	0	1443734	1

Port:

CRC_15(4)

	From	To	Count	Threshold
Bin	0	1	1454104	1
Bin	1	0	1455703	1

Port:

CRC_15(3)

	From	To	Count	Threshold
Bin	0	1	1453743	1
Bin	1	0	1455342	1

Port:

CRC_15(2)

	From	To	Count	Threshold
Bin	0	1	1440570	1
Bin	1	0	1442165	1

Port:

CRC_15(1)

	From	To	Count	Threshold
Bin	0	1	1456437	1
Bin	1	0	1458034	1

Port:

CRC_15(0)

	From	To	Count	Threshold
Bin	0	1	1470076	1
Bin	1	0	1471674	1

Port:

CRC_17(16)

	From	To	Count	Threshold
Bin	0	1	1734039	1
Bin	1	0	1735633	1

Port:

CRC_17(15)

	From	To	Count	Threshold
Bin	0	1	1744508	1
Bin	1	0	1746106	1

Port:

CRC_17(14)

	From	To	Count	Threshold
Bin	0	1	1759054	1
Bin	1	0	1760651	1

Port:

CRC_17(13)

	From	To	Count	Threshold
Bin	0	1	1757156	1
Bin	1	0	1758753	1

Port:

CRC_17(12)

	From	To	Count	Threshold
Bin	0	1	1695908	1
Bin	1	0	1697506	1

Port:

CRC_17(11)

	From	To	Count	Threshold
Bin	0	1	1710517	1
Bin	1	0	1712115	1

Port:

CRC_17(10)

	From	To	Count	Threshold
Bin	0	1	1657718	1
Bin	1	0	1659317	1

Port:

CRC_17(9)

	From	To	Count	Threshold
Bin	0	1	1671362	1
Bin	1	0	1672959	1

Port:

CRC_17(8)

	From	To	Count	Threshold
Bin	0	1	1685982	1
Bin	1	0	1687581	1

Port:

CRC_17(7)

	From	To	Count	Threshold
Bin	0	1	1699437	1
Bin	1	0	1701036	1

Port:

CRC_17(6)

	From	To	Count	Threshold
Bin	0	1	1713617	1
Bin	1	0	1715217	1

Port:

CRC_17(5)

	From	To	Count	Threshold
Bin	0	1	1713382	1
Bin	1	0	1714978	1

Port:

CRC_17(4)

	From	To	Count	Threshold
Bin	0	1	1725540	1
Bin	1	0	1727138	1

Port:

CRC_17(3)

	From	To	Count	Threshold
Bin	0	1	1744070	1
Bin	1	0	1745668	1

Port:

CRC_17(2)

	From	To	Count	Threshold
Bin	0	1	1713985	1
Bin	1	0	1715584	1

Port:

CRC_17(1)

	From	To	Count	Threshold
Bin	0	1	1729286	1
Bin	1	0	1730885	1

Port:

CRC_17(0)

	From	To	Count	Threshold
Bin	0	1	1757719	1
Bin	1	0	1759317	1

Port:

CRC_21(20)

	From	To	Count	Threshold
Bin	0	1	1738348	1
Bin	1	0	1739941	1

Port:

CRC_21(19)

	From	To	Count	Threshold
Bin	0	1	1694492	1
Bin	1	0	1696089	1

Port:

CRC_21(18)

	From	To	Count	Threshold
Bin	0	1	1709182	1
Bin	1	0	1710780	1

Port:

CRC_21(17)

	From	To	Count	Threshold
Bin	0	1	1723668	1
Bin	1	0	1725266	1

Port:

CRC_21(16)

	From	To	Count	Threshold
Bin	0	1	1736428	1
Bin	1	0	1738027	1

Port:

CRC_21(15)

	From	To	Count	Threshold
Bin	0	1	1749537	1
Bin	1	0	1751135	1

Port:

CRC_21(14)

	From	To	Count	Threshold
Bin	0	1	1762507	1
Bin	1	0	1764105	1

Port:

CRC_21(13)

	From	To	Count	Threshold
Bin	0	1	1777446	1
Bin	1	0	1779044	1

Port:

CRC_21(12)

	From	To	Count	Threshold
Bin	0	1	1718146	1
Bin	1	0	1719743	1

Port:

CRC_21(11)

	From	To	Count	Threshold
Bin	0	1	1733293	1
Bin	1	0	1734892	1

Port:

CRC_21(10)

	From	To	Count	Threshold
Bin	0	1	1723964	1
Bin	1	0	1725560	1

Port:

CRC_21(9)

	From	To	Count	Threshold
Bin	0	1	1737663	1
Bin	1	0	1739261	1

Port:

CRC_21(8)

	From	To	Count	Threshold
Bin	0	1	1753350	1
Bin	1	0	1754945	1

Port:

CRC_21(7)

	From	To	Count	Threshold
Bin	0	1	1768568	1
Bin	1	0	1770168	1

Port:

CRC_21(6)

	From	To	Count	Threshold
Bin	0	1	1710305	1
Bin	1	0	1711902	1

Port:

CRC_21(5)

	From	To	Count	Threshold
Bin	0	1	1724000	1
Bin	1	0	1725597	1

Port:

CRC_21(4)

	From	To	Count	Threshold
Bin	0	1	1737131	1
Bin	1	0	1738729	1

Port:

CRC_21(3)

	From	To	Count	Threshold
Bin	0	1	1753239	1
Bin	1	0	1754837	1

Port:

CRC_21(2)

	From	To	Count	Threshold
Bin	0	1	1752204	1
Bin	1	0	1753800	1

Port:

CRC_21(1)

	From	To	Count	Threshold
Bin	0	1	1764851	1
Bin	1	0	1766449	1

Port:

CRC_21(0)

	From	To	Count	Threshold
Bin	0	1	1777838	1
Bin	1	0	1779434	1

Port:

ERR_FRM_REQ

	From	To	Count	Threshold
Bin	0	1	30824	1
Bin	1	0	32424	1

Port:

IS_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	8424	1
Bin	1	0	8415	1

Port:

BST_CTR(2)

	From	To	Count	Threshold
Bin	0	1	33334	1
Bin	1	0	34934	1

Port:

BST_CTR(1)

	From	To	Count	Threshold
Bin	0	1	70225	1
Bin	1	0	71823	1

Port:

BST_CTR(0)

	From	To	Count	Threshold
Bin	0	1	140700	1
Bin	1	0	142298	1

Port:

TRAN_IDENTIFIER(28)

	From	To	Count	Threshold
Bin	0	1	3946	1
Bin	1	0	5484	1

Port:

TRAN_IDENTIFIER(27)

	From	To	Count	Threshold
Bin	0	1	3920	1
Bin	1	0	5542	1

Port:

TRAN_IDENTIFIER(26)

	From	To	Count	Threshold
Bin	0	1	3792	1
Bin	1	0	5324	1

Port:

TRAN_IDENTIFIER(25)

	From	To	Count	Threshold
Bin	0	1	4128	1
Bin	1	0	5746	1

Port:

TRAN_IDENTIFIER(24)

	From	To	Count	Threshold
Bin	0	1	3888	1
Bin	1	0	5425	1

Port:

TRAN_IDENTIFIER(23)

	From	To	Count	Threshold
Bin	0	1	4157	1
Bin	1	0	5770	1

Port:

TRAN_IDENTIFIER(22)

	From	To	Count	Threshold
Bin	0	1	3886	1
Bin	1	0	5504	1

Port:

TRAN_IDENTIFIER(21)

	From	To	Count	Threshold
Bin	0	1	4233	1
Bin	1	0	5783	1

Port:

TRAN_IDENTIFIER(20)

	From	To	Count	Threshold
Bin	0	1	3889	1
Bin	1	0	5506	1

Port:

TRAN_IDENTIFIER(19)

	From	To	Count	Threshold
Bin	0	1	4204	1
Bin	1	0	5749	1

Port:

TRAN_IDENTIFIER(18)

	From	To	Count	Threshold
Bin	0	1	3808	1
Bin	1	0	5429	1

Port:

TRAN_IDENTIFIER(17)

	From	To	Count	Threshold
Bin	0	1	1667	1
Bin	1	0	9368	1

Port:

TRAN_IDENTIFIER(16)

	From	To	Count	Threshold
Bin	0	1	1713	1
Bin	1	0	9584	1

Port:

TRAN_IDENTIFIER(15)

	From	To	Count	Threshold
Bin	0	1	1692	1
Bin	1	0	9464	1

Port:

TRAN_IDENTIFIER(14)

	From	To	Count	Threshold
Bin	0	1	1708	1
Bin	1	0	9676	1

Port:

TRAN_IDENTIFIER(13)

	From	To	Count	Threshold
Bin	0	1	1710	1
Bin	1	0	9487	1

Port:

TRAN_IDENTIFIER(12)

	From	To	Count	Threshold
Bin	0	1	1603	1
Bin	1	0	9370	1

Port:

TRAN_IDENTIFIER(11)

	From	To	Count	Threshold
Bin	0	1	1646	1
Bin	1	0	9410	1

Port:

TRAN_IDENTIFIER(10)

	From	To	Count	Threshold
Bin	0	1	1672	1
Bin	1	0	9469	1

Port:

TRAN_IDENTIFIER(9)

	From	To	Count	Threshold
Bin	0	1	1704	1
Bin	1	0	9526	1

Port:

TRAN_IDENTIFIER(8)

	From	To	Count	Threshold
Bin	0	1	1702	1
Bin	1	0	9536	1

Port:

TRAN_IDENTIFIER(7)

	From	To	Count	Threshold
Bin	0	1	1736	1
Bin	1	0	9656	1

Port:

TRAN_IDENTIFIER(6)

	From	To	Count	Threshold
Bin	0	1	1654	1
Bin	1	0	9406	1

Port:

TRAN_IDENTIFIER(5)

	From	To	Count	Threshold
Bin	0	1	1706	1
Bin	1	0	9513	1

Port:

TRAN_IDENTIFIER(4)

	From	To	Count	Threshold
Bin	0	1	1714	1
Bin	1	0	9618	1

Port:

TRAN_IDENTIFIER(3)

	From	To	Count	Threshold
Bin	0	1	1700	1
Bin	1	0	9481	1

Port:

TRAN_IDENTIFIER(2)

	From	To	Count	Threshold
Bin	0	1	1734	1
Bin	1	0	9571	1

Port:

TRAN_IDENTIFIER(1)

	From	To	Count	Threshold
Bin	0	1	1744	1
Bin	1	0	9585	1

Port:

TRAN_IDENTIFIER(0)

	From	To	Count	Threshold
Bin	0	1	1645	1
Bin	1	0	9381	1

Port:

TRAN_FRAME_TEST.FSTC

	From	To	Count	Threshold
Bin	0	1	270	1
Bin	1	0	1870	1

Port:

TRAN_FRAME_TEST.FCRC

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	1700	1

Port:

TRAN_FRAME_TEST.SDLC

	From	To	Count	Threshold
Bin	0	1	270	1
Bin	1	0	1870	1

Port:

TRAN_FRAME_TEST.TPRM(4)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	3284	1

Port:

TRAN_FRAME_TEST.TPRM(3)

	From	To	Count	Threshold
Bin	0	1	183	1
Bin	1	0	1828	1

Port:

TRAN_FRAME_TEST.TPRM(2)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	1880	1

Port:

TRAN_FRAME_TEST.TPRM(1)

	From	To	Count	Threshold
Bin	0	1	429	1
Bin	1	0	2074	1

Port:

TRAN_FRAME_TEST.TPRM(0)

	From	To	Count	Threshold
Bin	0	1	646	1
Bin	1	0	2291	1

Port:

TRAN_WORD_SWAPPED(31)

	From	To	Count	Threshold
Bin	0	1	35438	1
Bin	1	0	37038	1

Port:

TRAN_WORD_SWAPPED(30)

	From	To	Count	Threshold
Bin	0	1	26739	1
Bin	1	0	28339	1

Port:

TRAN_WORD_SWAPPED(29)

	From	To	Count	Threshold
Bin	0	1	19032	1
Bin	1	0	20632	1

Port:

TRAN_WORD_SWAPPED(28)

	From	To	Count	Threshold
Bin	0	1	16938	1
Bin	1	0	18538	1

Port:

TRAN_WORD_SWAPPED(27)

	From	To	Count	Threshold
Bin	0	1	26470	1
Bin	1	0	28070	1

Port:

TRAN_WORD_SWAPPED(26)

	From	To	Count	Threshold
Bin	0	1	26680	1
Bin	1	0	28280	1

Port:

TRAN_WORD_SWAPPED(25)

	From	To	Count	Threshold
Bin	0	1	27552	1
Bin	1	0	29152	1

Port:

TRAN_WORD_SWAPPED(24)

	From	To	Count	Threshold
Bin	0	1	35377	1
Bin	1	0	36977	1

Port:

TRAN_WORD_SWAPPED(23)

	From	To	Count	Threshold
Bin	0	1	14400	1
Bin	1	0	16000	1

Port:

TRAN_WORD_SWAPPED(22)

	From	To	Count	Threshold
Bin	0	1	15059	1
Bin	1	0	16659	1

Port:

TRAN_WORD_SWAPPED(21)

	From	To	Count	Threshold
Bin	0	1	14849	1
Bin	1	0	16449	1

Port:

TRAN_WORD_SWAPPED(20)

	From	To	Count	Threshold
Bin	0	1	15821	1
Bin	1	0	17421	1

Port:

TRAN_WORD_SWAPPED(19)

	From	To	Count	Threshold
Bin	0	1	14688	1
Bin	1	0	16288	1

Port:

TRAN_WORD_SWAPPED(18)

	From	To	Count	Threshold
Bin	0	1	15846	1
Bin	1	0	17446	1

Port:

TRAN_WORD_SWAPPED(17)

	From	To	Count	Threshold
Bin	0	1	25928	1
Bin	1	0	27528	1

Port:

TRAN_WORD_SWAPPED(16)

	From	To	Count	Threshold
Bin	0	1	16627	1
Bin	1	0	18227	1

Port:

TRAN_WORD_SWAPPED(15)

	From	To	Count	Threshold
Bin	0	1	22777	1
Bin	1	0	24377	1

Port:

TRAN_WORD_SWAPPED(14)

	From	To	Count	Threshold
Bin	0	1	25704	1
Bin	1	0	27304	1

Port:

TRAN_WORD_SWAPPED(13)

	From	To	Count	Threshold
Bin	0	1	22032	1
Bin	1	0	23632	1

Port:

TRAN_WORD_SWAPPED(12)

	From	To	Count	Threshold
Bin	0	1	25833	1
Bin	1	0	27433	1

Port:

TRAN_WORD_SWAPPED(11)

	From	To	Count	Threshold
Bin	0	1	22441	1
Bin	1	0	24041	1

Port:

TRAN_WORD_SWAPPED(10)

	From	To	Count	Threshold
Bin	0	1	26355	1
Bin	1	0	27955	1

Port:

TRAN_WORD_SWAPPED(9)

	From	To	Count	Threshold
Bin	0	1	14208	1
Bin	1	0	15808	1

Port:

TRAN_WORD_SWAPPED(8)

	From	To	Count	Threshold
Bin	0	1	15135	1
Bin	1	0	16735	1

Port:

TRAN_WORD_SWAPPED(7)

	From	To	Count	Threshold
Bin	0	1	8251	1
Bin	1	0	9851	1

Port:

TRAN_WORD_SWAPPED(6)

	From	To	Count	Threshold
Bin	0	1	8670	1
Bin	1	0	10270	1

Port:

TRAN_WORD_SWAPPED(5)

	From	To	Count	Threshold
Bin	0	1	8250	1
Bin	1	0	9850	1

Port:

TRAN_WORD_SWAPPED(4)

	From	To	Count	Threshold
Bin	0	1	26016	1
Bin	1	0	27616	1

Port:

TRAN_WORD_SWAPPED(3)

	From	To	Count	Threshold
Bin	0	1	20559	1
Bin	1	0	22159	1

Port:

TRAN_WORD_SWAPPED(2)

	From	To	Count	Threshold
Bin	0	1	26228	1
Bin	1	0	27828	1

Port:

TRAN_WORD_SWAPPED(1)

	From	To	Count	Threshold
Bin	0	1	21530	1
Bin	1	0	23130	1

Port:

TRAN_WORD_SWAPPED(0)

	From	To	Count	Threshold
Bin	0	1	25986	1
Bin	1	0	27586	1

Port:

TRAN_DLC(3)

	From	To	Count	Threshold
Bin	0	1	1530	1
Bin	1	0	3129	1

Port:

TRAN_DLC(2)

	From	To	Count	Threshold
Bin	0	1	1943	1
Bin	1	0	3543	1

Port:

TRAN_DLC(1)

	From	To	Count	Threshold
Bin	0	1	1905	1
Bin	1	0	3504	1

Port:

TRAN_DLC(0)

	From	To	Count	Threshold
Bin	0	1	3494	1
Bin	1	0	5094	1

Signal:

TX_SR_OUTPUT

	From	To	Count	Threshold
Bin	0	1	524281	1
Bin	1	0	525880	1

Signal:

TX_SR_CE

	From	To	Count	Threshold
Bin	0	1	2648733	1
Bin	1	0	2650333	1

Signal:

TX_SR_PLOAD

	From	To	Count	Threshold
Bin	0	1	410629	1
Bin	1	0	412229	1

Signal:

TX_SR_PLOAD_VAL(31)

	From	To	Count	Threshold
Bin	0	1	105846	1
Bin	1	0	107446	1

Signal:

TX_SR_PLOAD_VAL(30)

	From	To	Count	Threshold
Bin	0	1	104450	1
Bin	1	0	106050	1

Signal:

TX_SR_PLOAD_VAL(29)

	From	To	Count	Threshold
Bin	0	1	112824	1
Bin	1	0	114424	1

Signal:

TX_SR_PLOAD_VAL(28)

	From	To	Count	Threshold
Bin	0	1	119499	1
Bin	1	0	121099	1

Signal:

TX_SR_PLOAD_VAL(27)

	From	To	Count	Threshold
Bin	0	1	83707	1
Bin	1	0	85307	1

Signal:

TX_SR_PLOAD_VAL(26)

	From	To	Count	Threshold
Bin	0	1	84455	1
Bin	1	0	86055	1

Signal:

TX_SR_PLOAD_VAL(25)

	From	To	Count	Threshold
Bin	0	1	83539	1
Bin	1	0	85139	1

Signal:

TX_SR_PLOAD_VAL(24)

	From	To	Count	Threshold
Bin	0	1	85742	1
Bin	1	0	87342	1

Signal:

TX_SR_PLOAD_VAL(23)

	From	To	Count	Threshold
Bin	0	1	81197	1
Bin	1	0	82797	1

Signal:

TX_SR_PLOAD_VAL(22)

	From	To	Count	Threshold
Bin	0	1	84984	1
Bin	1	0	86584	1

Signal:

TX_SR_PLOAD_VAL(21)

	From	To	Count	Threshold
Bin	0	1	85474	1
Bin	1	0	87074	1

Signal:

TX_SR_PLOAD_VAL(20)

	From	To	Count	Threshold
Bin	0	1	61057	1
Bin	1	0	62657	1

Signal:

TX_SR_PLOAD_VAL(19)

	From	To	Count	Threshold
Bin	0	1	59586	1
Bin	1	0	61186	1

Signal:

TX_SR_PLOAD_VAL(18)

	From	To	Count	Threshold
Bin	0	1	60919	1
Bin	1	0	62519	1

Signal:

TX_SR_PLOAD_VAL(17)

	From	To	Count	Threshold
Bin	0	1	60469	1
Bin	1	0	62069	1

Signal:

TX_SR_PLOAD_VAL(16)

	From	To	Count	Threshold
Bin	0	1	48471	1
Bin	1	0	50071	1

Signal:

TX_SR_PLOAD_VAL(15)

	From	To	Count	Threshold
Bin	0	1	43823	1
Bin	1	0	45423	1

Signal:

TX_SR_PLOAD_VAL(14)

	From	To	Count	Threshold
Bin	0	1	35897	1
Bin	1	0	37497	1

Signal:

TX_SR_PLOAD_VAL(13)

	From	To	Count	Threshold
Bin	0	1	26174	1
Bin	1	0	27774	1

Signal:

TX_SR_PLOAD_VAL(12)

	From	To	Count	Threshold
Bin	0	1	29146	1
Bin	1	0	30746	1

Signal:

TX_SR_PLOAD_VAL(11)

	From	To	Count	Threshold
Bin	0	1	26227	1
Bin	1	0	27827	1

Signal:

TX_SR_PLOAD_VAL(10)

	From	To	Count	Threshold
Bin	0	1	26754	1
Bin	1	0	28354	1

Signal:

TX_SR_PLOAD_VAL(9)

	From	To	Count	Threshold
Bin	0	1	23717	1
Bin	1	0	25317	1

Signal:

TX_SR_PLOAD_VAL(8)

	From	To	Count	Threshold
Bin	0	1	26260	1
Bin	1	0	27860	1

Signal:

TX_SR_PLOAD_VAL(7)

	From	To	Count	Threshold
Bin	0	1	22776	1
Bin	1	0	24376	1

Signal:

TX_SR_PLOAD_VAL(6)

	From	To	Count	Threshold
Bin	0	1	25620	1
Bin	1	0	27220	1

Signal:

TX_SR_PLOAD_VAL(5)

	From	To	Count	Threshold
Bin	0	1	22739	1
Bin	1	0	24339	1

Signal:

TX_SR_PLOAD_VAL(4)

	From	To	Count	Threshold
Bin	0	1	25811	1
Bin	1	0	27411	1

Signal:

TX_SR_PLOAD_VAL(3)

	From	To	Count	Threshold
Bin	0	1	23048	1
Bin	1	0	24648	1

Signal:

TX_SR_PLOAD_VAL(2)

	From	To	Count	Threshold
Bin	0	1	26097	1
Bin	1	0	27697	1

Signal:

TX_SR_PLOAD_VAL(1)

	From	To	Count	Threshold
Bin	0	1	23198	1
Bin	1	0	24798	1

Signal:

TX_SR_PLOAD_VAL(0)

	From	To	Count	Threshold
Bin	0	1	25565	1
Bin	1	0	27165	1

Signal:

TX_BASE_ID(10)

	From	To	Count	Threshold
Bin	0	1	3860	1
Bin	1	0	5459	1

Signal:

TX_BASE_ID(9)

	From	To	Count	Threshold
Bin	0	1	3917	1
Bin	1	0	5517	1

Signal:

TX_BASE_ID(8)

	From	To	Count	Threshold
Bin	0	1	3701	1
Bin	1	0	5299	1

Signal:

TX_BASE_ID(7)

	From	To	Count	Threshold
Bin	0	1	4123	1
Bin	1	0	5721	1

Signal:

TX_BASE_ID(6)

	From	To	Count	Threshold
Bin	0	1	3799	1
Bin	1	0	5399	1

Signal:

TX_BASE_ID(5)

	From	To	Count	Threshold
Bin	0	1	4147	1
Bin	1	0	5746	1

Signal:

TX_BASE_ID(4)

	From	To	Count	Threshold
Bin	0	1	3880	1
Bin	1	0	5479	1

Signal:

TX_BASE_ID(3)

	From	To	Count	Threshold
Bin	0	1	4146	1
Bin	1	0	5746	1

Signal:

TX_BASE_ID(2)

	From	To	Count	Threshold
Bin	0	1	3885	1
Bin	1	0	5483	1

Signal:

TX_BASE_ID(1)

	From	To	Count	Threshold
Bin	0	1	4115	1
Bin	1	0	5713	1

Signal:

TX_BASE_ID(0)

	From	To	Count	Threshold
Bin	0	1	3807	1
Bin	1	0	5406	1

Signal:

TX_EXT_ID(17)

	From	To	Count	Threshold
Bin	0	1	1661	1
Bin	1	0	3261	1

Signal:

TX_EXT_ID(16)

	From	To	Count	Threshold
Bin	0	1	1707	1
Bin	1	0	3307	1

Signal:

TX_EXT_ID(15)

	From	To	Count	Threshold
Bin	0	1	1686	1
Bin	1	0	3286	1

Signal:

TX_EXT_ID(14)

	From	To	Count	Threshold
Bin	0	1	1706	1
Bin	1	0	3306	1

Signal:

TX_EXT_ID(13)

	From	To	Count	Threshold
Bin	0	1	1709	1
Bin	1	0	3309	1

Signal:

TX_EXT_ID(12)

	From	To	Count	Threshold
Bin	0	1	1602	1
Bin	1	0	3202	1

Signal:

TX_EXT_ID(11)

	From	To	Count	Threshold
Bin	0	1	1645	1
Bin	1	0	3245	1

Signal:

TX_EXT_ID(10)

	From	To	Count	Threshold
Bin	0	1	1667	1
Bin	1	0	3267	1

Signal:

TX_EXT_ID(9)

	From	To	Count	Threshold
Bin	0	1	1699	1
Bin	1	0	3299	1

Signal:

TX_EXT_ID(8)

	From	To	Count	Threshold
Bin	0	1	1698	1
Bin	1	0	3298	1

Signal:

TX_EXT_ID(7)

	From	To	Count	Threshold
Bin	0	1	1732	1
Bin	1	0	3332	1

Signal:

TX_EXT_ID(6)

	From	To	Count	Threshold
Bin	0	1	1653	1
Bin	1	0	3253	1

Signal:

TX_EXT_ID(5)

	From	To	Count	Threshold
Bin	0	1	1705	1
Bin	1	0	3305	1

Signal:

TX_EXT_ID(4)

	From	To	Count	Threshold
Bin	0	1	1713	1
Bin	1	0	3313	1

Signal:

TX_EXT_ID(3)

	From	To	Count	Threshold
Bin	0	1	1700	1
Bin	1	0	3300	1

Signal:

TX_EXT_ID(2)

	From	To	Count	Threshold
Bin	0	1	1729	1
Bin	1	0	3329	1

Signal:

TX_EXT_ID(1)

	From	To	Count	Threshold
Bin	0	1	1740	1
Bin	1	0	3340	1

Signal:

TX_EXT_ID(0)

	From	To	Count	Threshold
Bin	0	1	1639	1
Bin	1	0	3239	1

Signal:

TX_CRC(20)

	From	To	Count	Threshold
Bin	0	1	1759193	1
Bin	1	0	1760791	1

Signal:

TX_CRC(19)

	From	To	Count	Threshold
Bin	0	1	1681713	1
Bin	1	0	1683312	1

Signal:

TX_CRC(18)

	From	To	Count	Threshold
Bin	0	1	1691529	1
Bin	1	0	1693127	1

Signal:

TX_CRC(17)

	From	To	Count	Threshold
Bin	0	1	1707498	1
Bin	1	0	1709094	1

Signal:

TX_CRC(16)

	From	To	Count	Threshold
Bin	0	1	1702189	1
Bin	1	0	1703788	1

Signal:

TX_CRC(15)

	From	To	Count	Threshold
Bin	0	1	1698865	1
Bin	1	0	1700463	1

Signal:

TX_CRC(14)

	From	To	Count	Threshold
Bin	0	1	1703186	1
Bin	1	0	1704784	1

Signal:

TX_CRC(13)

	From	To	Count	Threshold
Bin	0	1	1725811	1
Bin	1	0	1727409	1

Signal:

TX_CRC(12)

	From	To	Count	Threshold
Bin	0	1	1641540	1
Bin	1	0	1643138	1

Signal:

TX_CRC(11)

	From	To	Count	Threshold
Bin	0	1	1665845	1
Bin	1	0	1667442	1

Signal:

TX_CRC(10)

	From	To	Count	Threshold
Bin	0	1	1712479	1
Bin	1	0	1714079	1

Signal:

TX_CRC(9)

	From	To	Count	Threshold
Bin	0	1	1701396	1
Bin	1	0	1702993	1

Signal:

TX_CRC(8)

	From	To	Count	Threshold
Bin	0	1	1696599	1
Bin	1	0	1698196	1

Signal:

TX_CRC(7)

	From	To	Count	Threshold
Bin	0	1	1724172	1
Bin	1	0	1725771	1

Signal:

TX_CRC(6)

	From	To	Count	Threshold
Bin	0	1	1680324	1
Bin	1	0	1681923	1

Signal:

TX_CRC(5)

	From	To	Count	Threshold
Bin	0	1	1423269	1
Bin	1	0	1424868	1

Signal:

TX_CRC(4)

	From	To	Count	Threshold
Bin	0	1	1434699	1
Bin	1	0	1436298	1

Signal:

TX_CRC(3)

	From	To	Count	Threshold
Bin	0	1	1228985	1
Bin	1	0	1230585	1

Signal:

TX_CRC(2)

	From	To	Count	Threshold
Bin	0	1	1231120	1
Bin	1	0	1232720	1

Signal:

TX_CRC(1)

	From	To	Count	Threshold
Bin	0	1	1234656	1
Bin	1	0	1236256	1

Signal:

TX_CRC(0)

	From	To	Count	Threshold
Bin	0	1	1239400	1
Bin	1	0	1241000	1

Signal:

TX_CRC_FLIPPED(20)

	From	To	Count	Threshold
Bin	0	1	1759243	1
Bin	1	0	1760841	1

Signal:

TX_CRC_FLIPPED(19)

	From	To	Count	Threshold
Bin	0	1	1681763	1
Bin	1	0	1683362	1

Signal:

TX_CRC_FLIPPED(18)

	From	To	Count	Threshold
Bin	0	1	1691579	1
Bin	1	0	1693177	1

Signal:

TX_CRC_FLIPPED(17)

	From	To	Count	Threshold
Bin	0	1	1707548	1
Bin	1	0	1709144	1

Signal:

TX_CRC_FLIPPED(16)

	From	To	Count	Threshold
Bin	0	1	1702239	1
Bin	1	0	1703838	1

Signal:

TX_CRC_FLIPPED(15)

	From	To	Count	Threshold
Bin	0	1	1698915	1
Bin	1	0	1700513	1

Signal:

TX_CRC_FLIPPED(14)

	From	To	Count	Threshold
Bin	0	1	1703236	1
Bin	1	0	1704834	1

Signal:

TX_CRC_FLIPPED(13)

	From	To	Count	Threshold
Bin	0	1	1725861	1
Bin	1	0	1727459	1

Signal:

TX_CRC_FLIPPED(12)

	From	To	Count	Threshold
Bin	0	1	1641590	1
Bin	1	0	1643188	1

Signal:

TX_CRC_FLIPPED(11)

	From	To	Count	Threshold
Bin	0	1	1665895	1
Bin	1	0	1667492	1

Signal:

TX_CRC_FLIPPED(10)

	From	To	Count	Threshold
Bin	0	1	1712529	1
Bin	1	0	1714129	1

Signal:

TX_CRC_FLIPPED(9)

	From	To	Count	Threshold
Bin	0	1	1701446	1
Bin	1	0	1703043	1

Signal:

TX_CRC_FLIPPED(8)

	From	To	Count	Threshold
Bin	0	1	1696649	1
Bin	1	0	1698246	1

Signal:

TX_CRC_FLIPPED(7)

	From	To	Count	Threshold
Bin	0	1	1724222	1
Bin	1	0	1725821	1

Signal:

TX_CRC_FLIPPED(6)

	From	To	Count	Threshold
Bin	0	1	1680374	1
Bin	1	0	1681973	1

Signal:

TX_CRC_FLIPPED(5)

	From	To	Count	Threshold
Bin	0	1	1423319	1
Bin	1	0	1424918	1

Signal:

TX_CRC_FLIPPED(4)

	From	To	Count	Threshold
Bin	0	1	1434749	1
Bin	1	0	1436348	1

Signal:

TX_CRC_FLIPPED(3)

	From	To	Count	Threshold
Bin	0	1	1228990	1
Bin	1	0	1230590	1

Signal:

TX_CRC_FLIPPED(2)

	From	To	Count	Threshold
Bin	0	1	1231125	1
Bin	1	0	1232725	1

Signal:

TX_CRC_FLIPPED(1)

	From	To	Count	Threshold
Bin	0	1	1234661	1
Bin	1	0	1236261	1

Signal:

TX_CRC_FLIPPED(0)

	From	To	Count	Threshold
Bin	0	1	1239405	1
Bin	1	0	1241005	1

Signal:

BST_CTR_GREY(2)

	From	To	Count	Threshold
Bin	0	1	117352	1
Bin	1	0	175569	1

Signal:

BST_CTR_GREY(1)

	From	To	Count	Threshold
Bin	0	1	142964	1
Bin	1	0	149957	1

Signal:

BST_CTR_GREY(0)

	From	To	Count	Threshold
Bin	0	1	147078	1
Bin	1	0	145843	1

Signal:

BST_PARITY

	From	To	Count	Threshold
Bin	0	1	140700	1
Bin	1	0	142298	1

Signal:

STUFF_COUNT(3)

	From	To	Count	Threshold
Bin	0	1	33334	1
Bin	1	0	34934	1

Signal:

STUFF_COUNT(2)

	From	To	Count	Threshold
Bin	0	1	42382	1
Bin	1	0	43980	1

Signal:

STUFF_COUNT(1)

	From	To	Count	Threshold
Bin	0	1	76853	1
Bin	1	0	78451	1

Signal:

STUFF_COUNT(0)

	From	To	Count	Threshold
Bin	0	1	140700	1
Bin	1	0	142298	1

Signal:

FLIP_MASK(20)

	From	To	Count	Threshold
Bin	0	1	1473	1
Bin	1	0	3842	1

Signal:

FLIP_MASK(19)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	5178	1

Signal:

FLIP_MASK(18)

	From	To	Count	Threshold
Bin	0	1	141	1
Bin	1	0	5174	1

Signal:

FLIP_MASK(17)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	5225	1

Signal:

FLIP_MASK(16)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	5243	1

Signal:

FLIP_MASK(15)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	5243	1

Signal:

FLIP_MASK(14)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	5254	1

Signal:

FLIP_MASK(13)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	5252	1

Signal:

FLIP_MASK(12)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	5255	1

Signal:

FLIP_MASK(11)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	5245	1

Signal:

FLIP_MASK(10)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	5246	1

Signal:

FLIP_MASK(9)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	5250	1

Signal:

FLIP_MASK(8)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	5250	1

Signal:

FLIP_MASK(7)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	5251	1

Signal:

FLIP_MASK(6)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	5254	1

Signal:

FLIP_MASK(5)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	5259	1

Signal:

FLIP_MASK(4)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	5265	1

Signal:

FLIP_MASK(3)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	5310	1

Signal:

FLIP_MASK(2)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	5310	1

Signal:

FLIP_MASK(1)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	5310	1

Signal:

FLIP_MASK(0)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	5310	1

Signal:

STUFF_COUNT_FLIPPED(3)

	From	To	Count	Threshold
Bin	0	1	33554	1
Bin	1	0	35154	1

Signal:

STUFF_COUNT_FLIPPED(2)

	From	To	Count	Threshold
Bin	0	1	42453	1
Bin	1	0	44051	1

Signal:

STUFF_COUNT_FLIPPED(1)

	From	To	Count	Threshold
Bin	0	1	76934	1
Bin	1	0	78532	1

Signal:

STUFF_COUNT_FLIPPED(0)

	From	To	Count	Threshold
Bin	0	1	140729	1
Bin	1	0	142327	1

Signal:

TRAN_DLC_SWAPPED(3)

	From	To	Count	Threshold
Bin	0	1	1637	1
Bin	1	0	3236	1

Signal:

TRAN_DLC_SWAPPED(2)

	From	To	Count	Threshold
Bin	0	1	2046	1
Bin	1	0	3646	1

Signal:

TRAN_DLC_SWAPPED(1)

	From	To	Count	Threshold
Bin	0	1	2016	1
Bin	1	0	3615	1

Signal:

TRAN_DLC_SWAPPED(0)

	From	To	Count	Threshold
Bin	0	1	3597	1
Bin	1	0	5197	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

234: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')

	Evaluated to	Count	Threshold
Bin	False	16848775	1
Bin	True	5352502	1

"=" expression

234: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')

	Evaluated to	Count	Threshold
Bin	False	11157274	1
Bin	True	11044003	1

"and" expression

234:    tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1') 
                              <------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	8395270	1
Bin	True	False	2703769	1
Bin	True	True	2648733	1

"=" expression

239: tx_sr_pload <= '1' when (tx_load_base_id = '1' or

	Evaluated to	Count	Threshold
Bin	False	827350	1
Bin	True	49704	1

"=" expression

240: tx_load_ext_id = '1' or

	Evaluated to	Count	Threshold
Bin	False	839522	1
Bin	True	37532	1

"or" expression

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or

	LHS	RHS	Count	Threshold
Bin	False	False	789818	1
Bin	False	True	37532	1
Bin	True	False	49704	1

"=" expression

241: tx_load_dlc = '1' or

	Evaluated to	Count	Threshold
Bin	False	755849	1
Bin	True	121205	1

"or" expression

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or 
241:                             tx_load_dlc = '1' or

	LHS	RHS	Count	Threshold
Bin	False	False	668613	1
Bin	False	True	121205	1
Bin	True	False	87236	1

"=" expression

242: tx_load_data_word = '1' or

	Evaluated to	Count	Threshold
Bin	False	719568	1
Bin	True	157486	1

"or" expression

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or 
241:                             tx_load_dlc = '1' or 
242:                             tx_load_data_word = '1' or

	LHS	RHS	Count	Threshold
Bin	False	False	511127	1
Bin	False	True	157486	1
Bin	True	False	208441	1

"=" expression

243: tx_load_stuff_count = '1' or

	Evaluated to	Count	Threshold
Bin	False	836857	1
Bin	True	40197	1

"or" expression

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or 
241:                             tx_load_dlc = '1' or 
242:                             tx_load_data_word = '1' or 
243:                             tx_load_stuff_count = '1' or

	LHS	RHS	Count	Threshold
Bin	False	False	470930	1
Bin	False	True	40197	1
Bin	True	False	365927	1

"=" expression

244: tx_load_crc = '1')

	Evaluated to	Count	Threshold
Bin	False	819953	1
Bin	True	57101	1

"or" expression

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or 
241:                             tx_load_dlc = '1' or 
242:                             tx_load_data_word = '1' or 
243:                             tx_load_stuff_count = '1' or 
244:                             tx_load_crc = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	413829	1
Bin	False	True	57101	1
Bin	True	False	406124	1

"xor" expression

264:    bst_parity <= bst_ctr_grey(0) xor bst_ctr_grey(1) xor bst_ctr_grey(2); 
                      <-----LHS----->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	75049	1
Bin	'0'	'1'	70794	1
Bin	'1'	'0'	74908	1
Bin	'1'	'1'	72170	1

"xor" expression

264:    bst_parity <= bst_ctr_grey(0) xor bst_ctr_grey(1) xor bst_ctr_grey(2); 
                      <---------------LHS--------------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	91044	1
Bin	'0'	'1'	56175	1
Bin	'1'	'0'	84525	1
Bin	'1'	'1'	61177	1

"=" expression

278: if (mr_mode_tstm = '1') then

	Evaluated to	Count	Threshold
Bin	False	5926	1
Bin	True	2827	1

"=" expression

284: tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1')

	Evaluated to	Count	Threshold
Bin	False	6715885	1
Bin	True	78586	1

"=" expression

289:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1')

	Evaluated to	Count	Threshold
Bin	False	581977	1
Bin	True	2118	1

"=" expression

294: tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and

	Evaluated to	Count	Threshold
Bin	False	21116	1
Bin	True	270	1

"=" expression

295:                                                               mr_mode_tstm = '1')

	Evaluated to	Count	Threshold
Bin	False	16769	1
Bin	True	4617	1

"and" expression

294:    tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and 
295:                                                               mr_mode_tstm = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	4397	1
Bin	True	False	50	1
Bin	True	True	220	1

"=" expression

308:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else

	Evaluated to	Count	Threshold
Bin	False	8193811	1
Bin	True	49717	1

"=" expression

309:                            tx_ext_id & "00000000000000" when (tx_load_ext_id = '1') else

	Evaluated to	Count	Threshold
Bin	False	8156279	1
Bin	True	37532	1

"=" expression

310: tran_dlc_swapped & "0000000000000000000000000000" when (tx_load_dlc = '1') else

	Evaluated to	Count	Threshold
Bin	False	8035074	1
Bin	True	121205	1

"=" expression

311:                                       tran_word_swapped when (tx_load_data_word = '1') else

	Evaluated to	Count	Threshold
Bin	False	7877588	1
Bin	True	157486	1

"=" expression

312: stuff_count_flipped & "0000000000000000000000000000" when (tx_load_stuff_count = '1') else

	Evaluated to	Count	Threshold
Bin	False	7837391	1
Bin	True	40197	1

"=" expression

313:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else

	Evaluated to	Count	Threshold
Bin	False	7780290	1
Bin	True	57101	1

"=" expression

339: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else

	Evaluated to	Count	Threshold
Bin	False	1383944	1
Bin	True	42595	1

"=" expression

339: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else

	Evaluated to	Count	Threshold
Bin	False	133215	1
Bin	True	1293324	1

"and" expression

339:    tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else 
                                      <------LHS------>     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	1262998	1
Bin	True	False	12269	1
Bin	True	True	30326	1

"=" expression

340: RECESSIVE when (err_frm_req = '1') else

	Evaluated to	Count	Threshold
Bin	False	1383944	1
Bin	True	12269	1

"=" expression

341: DOMINANT when (tx_dominant = '1') else

	Evaluated to	Count	Threshold
Bin	False	1260402	1
Bin	True	123542	1

"=" expression

342: tx_sr_output when (tx_shift_ena = '1') else

	Evaluated to	Count	Threshold
Bin	False	193598	1
Bin	True	1066804	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/tx_shift_reg.vhd

Sub-instances:

Current Instance:

Details:

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"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

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