NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TX_SHIFT_REG_INST	100.0 % (7/7)	100.0 % (8/8)	100.0 % (202/202)	100.0 % (6/6)	N.A.	N.A.	100.0 % (223/223)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST	100.0 % (49/49)	100.0 % (44/44)	100.0 % (578/578)	100.0 % (80/80)	N.A.	N.A.	100.0 % (751/751)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 234 to 236:

234:    tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1') 
235:                    else 
236:                '0';

Count: 22897767
Threshold: 1

Signal assignment statement on line 234:

234: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')
Count: 2645094
Threshold: 1

Signal assignment statement on line 236:

236: '0';
Count: 20252673
Threshold: 1

If statement on lines 239 to 246:

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or 
...
245:                       else 
246:                   '0';

Count: 885096
Threshold: 1

Signal assignment statement on line 239:

239: tx_sr_pload <= '1' when (tx_load_base_id = '1' or
Count: 467636
Threshold: 1

Signal assignment statement on line 246:

246: '0';
Count: 417460
Threshold: 1

If statement on lines 249 to 251:

249:    tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else 
250:                crc_17 & "0000" when (crc_src = C_CRC17_SRC) else 
251:                        crc_21;

Count: 8800039
Threshold: 1

Signal assignment statement on line 249:

249: tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else
Count: 1635350
Threshold: 1

Signal assignment statement on line 250:

250: crc_17 & "0000" when (crc_src = C_CRC17_SRC) else
Count: 1166446
Threshold: 1

Signal assignment statement on line 251:

251: crc_21;
Count: 5998243
Threshold: 1

Sequential statement on lines 254 to 262:

254:    with bst_ctr select bst_ctr_grey <= 
255:        "001" when "001", 
...
261:        "100" when "111", 
262:        "000" when others;

Count: 296187
Threshold: 1

Signal assignment statement on line 255:

255: "001" when "001",
Count: 47282
Threshold: 1

Signal assignment statement on line 256:

256: "011" when "010",
Count: 42922
Threshold: 1

Signal assignment statement on line 257:

257: "010" when "011",
Count: 37660
Threshold: 1

Signal assignment statement on line 258:

258: "110" when "100",
Count: 33452
Threshold: 1

Signal assignment statement on line 259:

259: "111" when "101",
Count: 30081
Threshold: 1

Signal assignment statement on line 260:

260: "101" when "110",
Count: 28018
Threshold: 1

Signal assignment statement on line 261:

261: "100" when "111",
Count: 26292
Threshold: 1

Signal assignment statement on line 262:

262: "000" when others;
Count: 50480
Threshold: 1

Signal assignment statement on line 264:

264: bst_parity <= bst_ctr_grey(0) xor bst_ctr_grey(1) xor bst_ctr_grey(2);
Count: 296187
Threshold: 1

Signal assignment statement on line 266:

266: stuff_count <= bst_ctr_grey & bst_parity;
Count: 580416
Threshold: 1

Signal assignment statement on line 269:

269: tx_base_id <= tran_identifier(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
Count: 17659
Threshold: 1

Signal assignment statement on line 270:

270: tx_ext_id <= tran_identifier(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
Count: 9835
Threshold: 1

Signal assignment statement on line 277:

277: flip_mask <= (others => '0');
Count: 8760
Threshold: 1

If statement on lines 278 to 280:

278:        if (mr_mode_tstm = '1') then 
279:            flip_mask(20 - to_integer(unsigned(tran_frame_test.tprm))) <= '1'; 
280:        end if;

Count: 8760
Threshold: 1

Signal assignment statement on line 279:

279: flip_mask(20 - to_integer(unsigned(tran_frame_test.tprm))) <= '1';
Count: 2831
Threshold: 1

If statement on lines 284 to 286:

284:    tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1') 
285:                                             else 
286:                                      tx_crc;

Count: 6819596
Threshold: 1

Signal assignment statement on line 284:

284: tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1')
Count: 87811
Threshold: 1

Signal assignment statement on line 286:

286: tx_crc;
Count: 6731785
Threshold: 1

If statement on lines 289 to 291:

289:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1') 
290:                                                                     else 
291:                                                         stuff_count;

Count: 587009
Threshold: 1

Signal assignment statement on line 289:

289:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1')

Count: 2131
Threshold: 1

Signal assignment statement on line 291:

291:                                                         stuff_count;

Count: 584878
Threshold: 1

If statement on lines 294 to 297:

294:    tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and 
295:                                                               mr_mode_tstm = '1') 
296:                                                         else 
297:                                                tran_dlc;

Count: 21573
Threshold: 1

Signal assignment statement on line 294:

294: tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and
Count: 220
Threshold: 1

Signal assignment statement on line 297:

297: tran_dlc;
Count: 21353
Threshold: 1

If statement on lines 307 to 314:

307:    tx_sr_pload_val <= 
308:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else 
...
313:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else 
314:                                        (others => '0');

Count: 8281325
Threshold: 1

Signal assignment statement on line 308:

308:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else

Count: 50636
Threshold: 1

Signal assignment statement on line 309:

309:                            tx_ext_id & "00000000000000" when (tx_load_ext_id = '1') else

Count: 39365
Threshold: 1

Signal assignment statement on line 310:

310: tran_dlc_swapped & "0000000000000000000000000000" when (tx_load_dlc = '1') else
Count: 122549
Threshold: 1

Signal assignment statement on line 311:

311:                                       tran_word_swapped when (tx_load_data_word = '1') else

Count: 156937
Threshold: 1

Signal assignment statement on line 312:

312: stuff_count_flipped & "0000000000000000000000000000" when (tx_load_stuff_count = '1') else
Count: 40510
Threshold: 1

Signal assignment statement on line 313:

313:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else

Count: 57652
Threshold: 1

Signal assignment statement on line 314:

314: (others => '0');
Count: 7813676
Threshold: 1

If statement on lines 339 to 343:

339:    tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else 
340:                   RECESSIVE when (err_frm_req = '1') else 
341:                   DOMINANT when (tx_dominant = '1') else 
342:                   tx_sr_output when (tx_shift_ena = '1') else 
343:                   RECESSIVE;

Count: 1428832
Threshold: 1

Signal assignment statement on line 339:

339: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else
Count: 30343
Threshold: 1

Signal assignment statement on line 340:

340: RECESSIVE when (err_frm_req = '1') else
Count: 13184
Threshold: 1

Signal assignment statement on line 341:

341: DOMINANT when (tx_dominant = '1') else
Count: 123833
Threshold: 1

Signal assignment statement on line 342:

342: tx_sr_output when (tx_shift_ena = '1') else
Count: 1067305
Threshold: 1

Signal assignment statement on line 343:

343: RECESSIVE;
Count: 194167
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 234:

234: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')

	Evaluated to	Count	Threshold
Bin	True	2645094	1
Bin	False	20252673	1

"if" / "when" / "else" condition on lines 239 to 244:

239:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
240:                             tx_load_ext_id = '1' or 
241:                             tx_load_dlc = '1' or 
242:                             tx_load_data_word = '1' or 
243:                             tx_load_stuff_count = '1' or 
244:                             tx_load_crc = '1')

	Evaluated to	Count	Threshold
Bin	True	467636	1
Bin	False	417460	1

"if" / "when" / "else" condition on line 249:

249: tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else

	Evaluated to	Count	Threshold
Bin	True	1635350	1
Bin	False	7164689	1

"if" / "when" / "else" condition on line 250:

250: crc_17 & "0000" when (crc_src = C_CRC17_SRC) else

	Evaluated to	Count	Threshold
Bin	True	1166446	1
Bin	False	5998243	1

"case" / "with" / "select" choice on line 255:

255: "001" when "001",

	Choice of	Count	Threshold
Bin	`"001"`	47282	1

"case" / "with" / "select" choice on line 256:

256: "011" when "010",

	Choice of	Count	Threshold
Bin	`"010"`	42922	1

"case" / "with" / "select" choice on line 257:

257: "010" when "011",

	Choice of	Count	Threshold
Bin	`"011"`	37660	1

"case" / "with" / "select" choice on line 258:

258: "110" when "100",

	Choice of	Count	Threshold
Bin	`"100"`	33452	1

"case" / "with" / "select" choice on line 259:

259: "111" when "101",

	Choice of	Count	Threshold
Bin	`"101"`	30081	1

"case" / "with" / "select" choice on line 260:

260: "101" when "110",

	Choice of	Count	Threshold
Bin	`"110"`	28018	1

"case" / "with" / "select" choice on line 261:

261: "100" when "111",

	Choice of	Count	Threshold
Bin	`"111"`	26292	1

"case" / "with" / "select" choice on line 262:

262: "000" when others;

	Choice of	Count	Threshold
Bin	`others`	50480	1

"if" / "when" / "else" condition on line 278:

278: if (mr_mode_tstm = '1') then

	Evaluated to	Count	Threshold
Bin	True	2831	1
Bin	False	5929	1

"if" / "when" / "else" condition on line 284:

284: tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1')

	Evaluated to	Count	Threshold
Bin	True	87811	1
Bin	False	6731785	1

"if" / "when" / "else" condition on line 289:

289:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1')

	Evaluated to	Count	Threshold
Bin	True	2131	1
Bin	False	584878	1

"if" / "when" / "else" condition on lines 294 to 295:

294:    tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and 
295:                                                               mr_mode_tstm = '1')

	Evaluated to	Count	Threshold
Bin	True	220	1
Bin	False	21353	1

"if" / "when" / "else" condition on line 308:

308:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else

	Evaluated to	Count	Threshold
Bin	True	50636	1
Bin	False	8230689	1

"if" / "when" / "else" condition on line 309:

309:                            tx_ext_id & "00000000000000" when (tx_load_ext_id = '1') else

	Evaluated to	Count	Threshold
Bin	True	39365	1
Bin	False	8191324	1

"if" / "when" / "else" condition on line 310:

310: tran_dlc_swapped & "0000000000000000000000000000" when (tx_load_dlc = '1') else

	Evaluated to	Count	Threshold
Bin	True	122549	1
Bin	False	8068775	1

"if" / "when" / "else" condition on line 311:

311:                                       tran_word_swapped when (tx_load_data_word = '1') else

	Evaluated to	Count	Threshold
Bin	True	156937	1
Bin	False	7911838	1

"if" / "when" / "else" condition on line 312:

312: stuff_count_flipped & "0000000000000000000000000000" when (tx_load_stuff_count = '1') else

	Evaluated to	Count	Threshold
Bin	True	40510	1
Bin	False	7871328	1

"if" / "when" / "else" condition on line 313:

313:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else

	Evaluated to	Count	Threshold
Bin	True	57652	1
Bin	False	7813676	1

"if" / "when" / "else" condition on line 339:

339: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else

	Evaluated to	Count	Threshold
Bin	True	30343	1
Bin	False	1398489	1

"if" / "when" / "else" condition on line 340:

340: RECESSIVE when (err_frm_req = '1') else

	Evaluated to	Count	Threshold
Bin	True	13184	1
Bin	False	1385305	1

"if" / "when" / "else" condition on line 341:

341: DOMINANT when (tx_dominant = '1') else

	Evaluated to	Count	Threshold
Bin	True	123833	1
Bin	False	1261472	1

"if" / "when" / "else" condition on line 342:

342: tx_sr_output when (tx_shift_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	1067305	1
Bin	False	194167	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TSTM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_BASE_ID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_EXT_ID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_DLC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_DATA_WORD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_STUFF_COUNT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_CRC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_SHIFT_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_DOMINANT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CRC_SRC

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CRC_15

	Element	From	To	Threshold	Excluded due to
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CRC_17

	Element	From	To	Threshold	Excluded due to
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CRC_21

	Element	From	To	Threshold	Excluded due to
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ERR_FRM_REQ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_ERR_ACTIVE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BST_CTR

	Element	From	To	Threshold	Excluded due to
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TRAN_IDENTIFIER

	Element	From	To	Threshold	Excluded due to
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TRAN_WORD_SWAPPED

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TRAN_DLC

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

TX_DATA_NBS

	From	To	Count	Threshold
Bin	0	1	645138	1
Bin	1	0	643541	1

Port:

TRAN_FRAME_TEST

	Element	From	To	Count	Threshold
Bin	FSTC	0	1	270	1
Bin	FSTC	1	0	1871	1
Bin	FCRC	0	1	100	1
Bin	FCRC	1	0	1701	1
Bin	SDLC	0	1	270	1
Bin	SDLC	1	0	1871	1
Bin	TPRM(4)	0	1	74	1
Bin	TPRM(4)	1	0	3283	1
Bin	TPRM(3)	0	1	169	1
Bin	TPRM(3)	1	0	1814	1
Bin	TPRM(2)	0	1	246	1
Bin	TPRM(2)	1	0	1891	1
Bin	TPRM(1)	0	1	458	1
Bin	TPRM(1)	1	0	2103	1
Bin	TPRM(0)	0	1	645	1
Bin	TPRM(0)	1	0	2290	1

Signal:

TX_SR_OUTPUT

	From	To	Count	Threshold
Bin	0	1	523509	1
Bin	1	0	525109	1

Signal:

TX_SR_CE

	From	To	Count	Threshold
Bin	0	1	2645094	1
Bin	1	0	2646695	1

Signal:

TX_SR_PLOAD

	From	To	Count	Threshold
Bin	0	1	414258	1
Bin	1	0	415859	1

Signal:

TX_SR_PLOAD_VAL

	Element	From	To	Count	Threshold
Bin	(31)	0	1	105176	1
Bin	(31)	1	0	106777	1
Bin	(30)	0	1	106155	1
Bin	(30)	1	0	107756	1
Bin	(29)	0	1	109905	1
Bin	(29)	1	0	111506	1
Bin	(28)	0	1	120887	1
Bin	(28)	1	0	122488	1
Bin	(27)	0	1	84043	1
Bin	(27)	1	0	85644	1
Bin	(26)	0	1	84578	1
Bin	(26)	1	0	86179	1
Bin	(25)	0	1	83290	1
Bin	(25)	1	0	84891	1
Bin	(24)	0	1	84434	1
Bin	(24)	1	0	86035	1
Bin	(23)	0	1	80774	1
Bin	(23)	1	0	82375	1
Bin	(22)	0	1	81531	1
Bin	(22)	1	0	83132	1
Bin	(21)	0	1	86603	1
Bin	(21)	1	0	88204	1
Bin	(20)	0	1	60370	1
Bin	(20)	1	0	61971	1
Bin	(19)	0	1	59036	1
Bin	(19)	1	0	60637	1
Bin	(18)	0	1	63794	1
Bin	(18)	1	0	65395	1
Bin	(17)	0	1	62080	1
Bin	(17)	1	0	63681	1
Bin	(16)	0	1	48923	1
Bin	(16)	1	0	50524	1
Bin	(15)	0	1	44489	1
Bin	(15)	1	0	46090	1
Bin	(14)	0	1	36660	1
Bin	(14)	1	0	38261	1
Bin	(13)	0	1	25485	1
Bin	(13)	1	0	27086	1
Bin	(12)	0	1	28600	1
Bin	(12)	1	0	30201	1
Bin	(11)	0	1	26233	1
Bin	(11)	1	0	27834	1
Bin	(10)	0	1	26221	1
Bin	(10)	1	0	27822	1
Bin	(9)	0	1	23194	1
Bin	(9)	1	0	24795	1
Bin	(8)	0	1	25752	1
Bin	(8)	1	0	27353	1
Bin	(7)	0	1	22560	1
Bin	(7)	1	0	24161	1
Bin	(6)	0	1	24932	1
Bin	(6)	1	0	26533	1
Bin	(5)	0	1	23135	1
Bin	(5)	1	0	24736	1
Bin	(4)	0	1	25968	1
Bin	(4)	1	0	27569	1
Bin	(3)	0	1	23253	1
Bin	(3)	1	0	24854	1
Bin	(2)	0	1	26160	1
Bin	(2)	1	0	27761	1
Bin	(1)	0	1	22564	1
Bin	(1)	1	0	24165	1
Bin	(0)	0	1	26229	1
Bin	(0)	1	0	27830	1

Signal:

TX_BASE_ID

	Element	From	To	Count	Threshold
Bin	(10)	0	1	3820	1
Bin	(10)	1	0	5419	1
Bin	(9)	0	1	3883	1
Bin	(9)	1	0	5483	1
Bin	(8)	0	1	3817	1
Bin	(8)	1	0	5415	1
Bin	(7)	0	1	4129	1
Bin	(7)	1	0	5729	1
Bin	(6)	0	1	3806	1
Bin	(6)	1	0	5406	1
Bin	(5)	0	1	4134	1
Bin	(5)	1	0	5734	1
Bin	(4)	0	1	3824	1
Bin	(4)	1	0	5423	1
Bin	(3)	0	1	4128	1
Bin	(3)	1	0	5728	1
Bin	(2)	0	1	3868	1
Bin	(2)	1	0	5469	1
Bin	(1)	0	1	4160	1
Bin	(1)	1	0	5758	1
Bin	(0)	0	1	3777	1
Bin	(0)	1	0	5375	1

Signal:

TX_EXT_ID

	Element	From	To	Count	Threshold
Bin	(17)	0	1	1685	1
Bin	(17)	1	0	3286	1
Bin	(16)	0	1	1680	1
Bin	(16)	1	0	3281	1
Bin	(15)	0	1	1732	1
Bin	(15)	1	0	3333	1
Bin	(14)	0	1	1640	1
Bin	(14)	1	0	3241	1
Bin	(13)	0	1	1691	1
Bin	(13)	1	0	3291	1
Bin	(12)	0	1	1656	1
Bin	(12)	1	0	3257	1
Bin	(11)	0	1	1721	1
Bin	(11)	1	0	3321	1
Bin	(10)	0	1	1648	1
Bin	(10)	1	0	3248	1
Bin	(9)	0	1	1686	1
Bin	(9)	1	0	3287	1
Bin	(8)	0	1	1667	1
Bin	(8)	1	0	3268	1
Bin	(7)	0	1	1718	1
Bin	(7)	1	0	3319	1
Bin	(6)	0	1	1637	1
Bin	(6)	1	0	3238	1
Bin	(5)	0	1	1683	1
Bin	(5)	1	0	3283	1
Bin	(4)	0	1	1710	1
Bin	(4)	1	0	3310	1
Bin	(3)	0	1	1706	1
Bin	(3)	1	0	3307	1
Bin	(2)	0	1	1686	1
Bin	(2)	1	0	3286	1
Bin	(1)	0	1	1703	1
Bin	(1)	1	0	3304	1
Bin	(0)	0	1	1654	1
Bin	(0)	1	0	3254	1

Signal:

TX_CRC

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1765328	1
Bin	(20)	1	0	1766926	1
Bin	(19)	0	1	1689535	1
Bin	(19)	1	0	1691134	1
Bin	(18)	0	1	1700633	1
Bin	(18)	1	0	1702233	1
Bin	(17)	0	1	1716269	1
Bin	(17)	1	0	1717864	1
Bin	(16)	0	1	1711912	1
Bin	(16)	1	0	1713511	1
Bin	(15)	0	1	1708188	1
Bin	(15)	1	0	1709785	1
Bin	(14)	0	1	1714432	1
Bin	(14)	1	0	1716029	1
Bin	(13)	0	1	1729864	1
Bin	(13)	1	0	1731464	1
Bin	(12)	0	1	1640964	1
Bin	(12)	1	0	1642561	1
Bin	(11)	0	1	1666769	1
Bin	(11)	1	0	1668365	1
Bin	(10)	0	1	1715806	1
Bin	(10)	1	0	1717404	1
Bin	(9)	0	1	1704879	1
Bin	(9)	1	0	1706477	1
Bin	(8)	0	1	1706446	1
Bin	(8)	1	0	1708043	1
Bin	(7)	0	1	1734364	1
Bin	(7)	1	0	1735962	1
Bin	(6)	0	1	1686619	1
Bin	(6)	1	0	1688216	1
Bin	(5)	0	1	1410758	1
Bin	(5)	1	0	1412356	1
Bin	(4)	0	1	1424679	1
Bin	(4)	1	0	1426277	1
Bin	(3)	0	1	1214806	1
Bin	(3)	1	0	1216407	1
Bin	(2)	0	1	1216385	1
Bin	(2)	1	0	1217986	1
Bin	(1)	0	1	1219960	1
Bin	(1)	1	0	1221561	1
Bin	(0)	0	1	1224532	1
Bin	(0)	1	0	1226133	1

Signal:

TX_CRC_FLIPPED

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1765378	1
Bin	(20)	1	0	1766976	1
Bin	(19)	0	1	1689585	1
Bin	(19)	1	0	1691184	1
Bin	(18)	0	1	1700683	1
Bin	(18)	1	0	1702283	1
Bin	(17)	0	1	1716319	1
Bin	(17)	1	0	1717914	1
Bin	(16)	0	1	1711962	1
Bin	(16)	1	0	1713561	1
Bin	(15)	0	1	1708238	1
Bin	(15)	1	0	1709835	1
Bin	(14)	0	1	1714482	1
Bin	(14)	1	0	1716079	1
Bin	(13)	0	1	1729914	1
Bin	(13)	1	0	1731514	1
Bin	(12)	0	1	1641014	1
Bin	(12)	1	0	1642611	1
Bin	(11)	0	1	1666819	1
Bin	(11)	1	0	1668415	1
Bin	(10)	0	1	1715856	1
Bin	(10)	1	0	1717454	1
Bin	(9)	0	1	1704929	1
Bin	(9)	1	0	1706527	1
Bin	(8)	0	1	1706496	1
Bin	(8)	1	0	1708093	1
Bin	(7)	0	1	1734414	1
Bin	(7)	1	0	1736012	1
Bin	(6)	0	1	1686669	1
Bin	(6)	1	0	1688266	1
Bin	(5)	0	1	1410808	1
Bin	(5)	1	0	1412406	1
Bin	(4)	0	1	1424729	1
Bin	(4)	1	0	1426327	1
Bin	(3)	0	1	1214812	1
Bin	(3)	1	0	1216413	1
Bin	(2)	0	1	1216391	1
Bin	(2)	1	0	1217992	1
Bin	(1)	0	1	1219966	1
Bin	(1)	1	0	1221567	1
Bin	(0)	0	1	1224538	1
Bin	(0)	1	0	1226139	1

Signal:

BST_CTR_GREY

	Element	From	To	Count	Threshold
Bin	(2)	0	1	117843	1
Bin	(2)	1	0	176743	1
Bin	(1)	0	1	144115	1
Bin	(1)	1	0	150471	1
Bin	(0)	0	1	148303	1
Bin	(0)	1	0	146283	1

Signal:

BST_PARITY

	From	To	Count	Threshold
Bin	0	1	141315	1
Bin	1	0	142914	1

Signal:

STUFF_COUNT

	Element	From	To	Count	Threshold
Bin	(3)	0	1	33452	1
Bin	(3)	1	0	35053	1
Bin	(2)	0	1	42922	1
Bin	(2)	1	0	44520	1
Bin	(1)	0	1	77363	1
Bin	(1)	1	0	78961	1
Bin	(0)	0	1	141315	1
Bin	(0)	1	0	142914	1

Signal:

FLIP_MASK

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1469	1
Bin	(20)	1	0	3843	1
Bin	(19)	0	1	128	1
Bin	(19)	1	0	5184	1
Bin	(18)	0	1	153	1
Bin	(18)	1	0	5159	1
Bin	(17)	0	1	96	1
Bin	(17)	1	0	5216	1
Bin	(16)	0	1	66	1
Bin	(16)	1	0	5246	1
Bin	(15)	0	1	72	1
Bin	(15)	1	0	5240	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	5247	1
Bin	(13)	0	1	65	1
Bin	(13)	1	0	5247	1
Bin	(12)	0	1	67	1
Bin	(12)	1	0	5245	1
Bin	(11)	0	1	66	1
Bin	(11)	1	0	5246	1
Bin	(10)	0	1	61	1
Bin	(10)	1	0	5251	1
Bin	(9)	0	1	59	1
Bin	(9)	1	0	5253	1
Bin	(8)	0	1	61	1
Bin	(8)	1	0	5251	1
Bin	(7)	0	1	60	1
Bin	(7)	1	0	5252	1
Bin	(6)	0	1	62	1
Bin	(6)	1	0	5250	1
Bin	(5)	0	1	61	1
Bin	(5)	1	0	5251	1
Bin	(4)	0	1	50	1
Bin	(4)	1	0	5262	1
Bin	(3)	0	1	6	1
Bin	(3)	1	0	5306	1
Bin	(2)	0	1	6	1
Bin	(2)	1	0	5306	1
Bin	(1)	0	1	6	1
Bin	(1)	1	0	5306	1
Bin	(0)	0	1	6	1
Bin	(0)	1	0	5306	1

Signal:

STUFF_COUNT_FLIPPED

	Element	From	To	Count	Threshold
Bin	(3)	0	1	33672	1
Bin	(3)	1	0	35273	1
Bin	(2)	0	1	42984	1
Bin	(2)	1	0	44582	1
Bin	(1)	0	1	77453	1
Bin	(1)	1	0	79051	1
Bin	(0)	0	1	141343	1
Bin	(0)	1	0	142942	1

Signal:

TRAN_DLC_SWAPPED

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1701	1
Bin	(3)	1	0	3301	1
Bin	(2)	0	1	2118	1
Bin	(2)	1	0	3717	1
Bin	(1)	0	1	2083	1
Bin	(1)	1	0	3682	1
Bin	(0)	0	1	3725	1
Bin	(0)	1	0	5326	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 234:

 tx_shift_ena = '1' and tx_trigger = '1' 
 <------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	8745983	1
Bin	True	False	2701300	1
Bin	True	True	2645094	1

"=" expression on line 234:

tx_shift_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	17551373	1
Bin	True	5346394	1

"=" expression on line 234:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11506690	1
Bin	True	11391077	1

"or" expression on lines 239 to 244:

 tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1' or tx_load_data_word = '1' or tx_load_stuff_count = '1' or tx_load_crc = '1' 
 <----------------------------------------------------------LHS----------------------------------------------------------->    <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	417460	1
Bin	False	True	57652	1
Bin	True	False	409984	1

"or" expression on lines 239 to 243:

 tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1' or tx_load_data_word = '1' or tx_load_stuff_count = '1' 
 <--------------------------------------------LHS-------------------------------------------->    <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	475112	1
Bin	False	True	40510	1
Bin	True	False	369474	1

"or" expression on lines 239 to 242:

 tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1' or tx_load_data_word = '1' 
 <------------------------------LHS------------------------------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	515622	1
Bin	False	True	156937	1
Bin	True	False	212537	1

"or" expression on lines 239 to 241:

 tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1' 
 <--------------------LHS-------------------->    <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	672559	1
Bin	False	True	122549	1
Bin	True	False	89988	1

"or" expression on lines 239 to 240:

 tx_load_base_id = '1' or tx_load_ext_id = '1' 
 <--------LHS-------->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	795108	1
Bin	False	True	39365	1
Bin	True	False	50623	1

"=" expression on line 239:

tx_load_base_id = '1'

	Evaluated to	Count	Threshold
Bin	False	834473	1
Bin	True	50623	1

"=" expression on line 240:

tx_load_ext_id = '1'

	Evaluated to	Count	Threshold
Bin	False	845731	1
Bin	True	39365	1

"=" expression on line 241:

tx_load_dlc = '1'

	Evaluated to	Count	Threshold
Bin	False	762547	1
Bin	True	122549	1

"=" expression on line 242:

tx_load_data_word = '1'

	Evaluated to	Count	Threshold
Bin	False	728159	1
Bin	True	156937	1

"=" expression on line 243:

tx_load_stuff_count = '1'

	Evaluated to	Count	Threshold
Bin	False	844586	1
Bin	True	40510	1

"=" expression on line 244:

tx_load_crc = '1'

	Evaluated to	Count	Threshold
Bin	False	827444	1
Bin	True	57652	1

"xor" expression on line 264:

 bst_ctr_grey(0) xor bst_ctr_grey(1) xor bst_ctr_grey(2) 
 <---------------LHS--------------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	91801	1
Bin	'0'	'1'	56373	1
Bin	'1'	'0'	84942	1
Bin	'1'	'1'	61470	1

"xor" expression on line 264:

 bst_ctr_grey(0) xor bst_ctr_grey(1) 
 <-----LHS----->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	75171	1
Bin	'0'	'1'	71112	1
Bin	'1'	'0'	75300	1
Bin	'1'	'1'	73003	1

"=" expression on line 278:

mr_mode_tstm = '1'

	Evaluated to	Count	Threshold
Bin	False	5929	1
Bin	True	2831	1

"=" expression on line 284:

tran_frame_test.fcrc = '1'

	Evaluated to	Count	Threshold
Bin	False	6731785	1
Bin	True	87811	1

"=" expression on line 289:

tran_frame_test.fstc = '1'

	Evaluated to	Count	Threshold
Bin	False	584878	1
Bin	True	2131	1

"and" expression on lines 294 to 295:

 tran_frame_test.sdlc = '1' and mr_mode_tstm = '1' 
 <----------LHS----------->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	4472	1
Bin	True	False	50	1
Bin	True	True	220	1

"=" expression on line 294:

tran_frame_test.sdlc = '1'

	Evaluated to	Count	Threshold
Bin	False	21303	1
Bin	True	270	1

"=" expression on line 295:

mr_mode_tstm = '1'

	Evaluated to	Count	Threshold
Bin	False	16881	1
Bin	True	4692	1

"=" expression on line 308:

tx_load_base_id = '1'

	Evaluated to	Count	Threshold
Bin	False	8230689	1
Bin	True	50636	1

"=" expression on line 309:

tx_load_ext_id = '1'

	Evaluated to	Count	Threshold
Bin	False	8191324	1
Bin	True	39365	1

"=" expression on line 310:

tx_load_dlc = '1'

	Evaluated to	Count	Threshold
Bin	False	8068775	1
Bin	True	122549	1

"=" expression on line 311:

tx_load_data_word = '1'

	Evaluated to	Count	Threshold
Bin	False	7911838	1
Bin	True	156937	1

"=" expression on line 312:

tx_load_stuff_count = '1'

	Evaluated to	Count	Threshold
Bin	False	7871328	1
Bin	True	40510	1

"=" expression on line 313:

tx_load_crc = '1'

	Evaluated to	Count	Threshold
Bin	False	7813676	1
Bin	True	57652	1

"and" expression on line 339:

 err_frm_req = '1' and is_err_active = '1' 
 <------LHS------>     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	1229140	1
Bin	True	False	13184	1
Bin	True	True	30343	1

"=" expression on line 339:

err_frm_req = '1'

	Evaluated to	Count	Threshold
Bin	False	1385305	1
Bin	True	43527	1

"=" expression on line 339:

is_err_active = '1'

	Evaluated to	Count	Threshold
Bin	False	169349	1
Bin	True	1259483	1

"=" expression on line 340:

err_frm_req = '1'

	Evaluated to	Count	Threshold
Bin	False	1385305	1
Bin	True	13184	1

"=" expression on line 341:

tx_dominant = '1'

	Evaluated to	Count	Threshold
Bin	False	1261472	1
Bin	True	123833	1

"=" expression on line 342:

tx_shift_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	194167	1
Bin	True	1067305	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.TX_SHIFT_REG_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Details:

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"if" / "when" / "else" condition on line 249:

"if" / "when" / "else" condition on line 250:

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"if" / "when" / "else" condition on line 278:

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"if" / "when" / "else" condition on line 289:

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"if" / "when" / "else" condition on line 308:

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"if" / "when" / "else" condition on line 311: