NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

BIT_GEN(0)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(1)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(2)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(3)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(4)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(5)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.BTR_FD_PROP_FD_REG_COMP	100.0 % (2/2)	N.A.	100.0 % (48/48)	100.0 % (6/6)	N.A.	N.A.	100.0 % (56/56)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.BTR_FD_PROP_FD_REG_COMP

100.0 % (2/2)

N.A.

100.0 % (48/48)

100.0 % (6/6)

N.A.

100.0 % (56/56)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 145:

145: wr_en <= write and cs and (not lock);
Count: 326126
Threshold: 1

Signal assignment statement on line 168:

168: reg_value <= reg_value_r;
Count: 10026
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOCK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

REG_VALUE

	Element	From	To	Count	Threshold
Bin	(5)	0	1	239	1
Bin	(5)	1	0	1837	1
Bin	(4)	0	1	292	1
Bin	(4)	1	0	1890	1
Bin	(3)	0	1	278	1
Bin	(3)	1	0	1876	1
Bin	(2)	0	1	1184	1
Bin	(2)	1	0	2773	1
Bin	(1)	0	1	4706	1
Bin	(1)	1	0	3114	1
Bin	(0)	0	1	3888	1
Bin	(0)	1	0	2287	1

Signal:

REG_VALUE_R

	Element	From	To	Count	Threshold
Bin	(5)	0	1	301	1
Bin	(5)	1	0	8124	1
Bin	(4)	0	1	362	1
Bin	(4)	1	0	8063	1
Bin	(3)	0	1	362	1
Bin	(3)	1	0	8063	1
Bin	(2)	0	1	1268	1
Bin	(2)	1	0	7157	1
Bin	(1)	0	1	5201	1
Bin	(1)	1	0	3224	1
Bin	(0)	0	1	6074	1
Bin	(0)	1	0	2351	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	6347	1
Bin	1	0	7948	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 145:

 write and cs and (not lock) 
 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	55685	1
Bin	'1'	'0'	5	1
Bin	'1'	'1'	6347	1

"and" expression on line 145:

 write and cs 
 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	6712	1
Bin	'1'	'0'	156456	1
Bin	'1'	'1'	6352	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.BTR_FD_PROP_FD_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 145:

Signal assignment statement on line 168:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 145:

"and" expression on line 145:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: