NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_DEST_TST_MTGT_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (36/36)	100.0 % (6/6)	N.A.	N.A.	100.0 % (43/43)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

145: wr_en <= write and cs and (not lock);
Count: 717103
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13267459	1
Bin	1	0	13269059	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	110009	1
Bin	1	0	979836	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	131558	1
Bin	1	0	958287	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	123951	1
Bin	1	0	965894	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	193513	1
Bin	1	0	896332	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	219247	1
Bin	1	0	220847	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	135078	1
Bin	1	0	136678	1

Port:

LOCK

	From	To	Count	Threshold
Bin	0	1	2626	1
Bin	1	0	1027	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	1835	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	374	1
Bin	1	0	1974	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	2114	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	979	1
Bin	1	0	2579	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	469	1
Bin	1	0	3351	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	1095	1
Bin	1	0	2725	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	1091	1
Bin	1	0	2729	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	1079	1
Bin	1	0	2741	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	90848	1
Bin	1	0	92448	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	135078	1
Bin	'1'	'0'	219247	1
Bin	'1'	'1'	135068	1

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	405429	1
Bin	'1'	'0'	44220	1
Bin	'1'	'1'	90848	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_DEST_TST_MTGT_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: