NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/ctu_can_fd_vip.vhd

Nested Instances Statement Branch Toggle Expression FSM state Functional Average
FUNC_COV_CAN_CORE_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (115/115) 100.0 % (117/117)
FUNC_COV_PRESCALER_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (25/25) 100.0 % (27/27)
FUNC_COV_PRESCALER_NBT_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (9/9) 100.0 % (11/11)
FUNC_COV_PRESCALER_DBT_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (9/9) 100.0 % (11/11)
FUNC_COV_BUS_SAMPLING_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (15/15) 100.0 % (17/17)
FUNC_COV_RX_BUFFER_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (23/23) 100.0 % (25/25)
FUNC_COV_TX_ARBITRATOR_INST N.A. N.A. 100.0 % (18/18) N.A. N.A. 100.0 % (26/26) 100.0 % (44/44)
G_EACH_BUF(0) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (16/16) 100.0 % (18/18)
G_EACH_BUF(1) N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (17/17) 100.0 % (19/19)
G_EACH_BUF(2) N.A. N.A. 100.0 % (2/2) N.A. N.A. N.A. 100.0 % (2/2)
G_EACH_BUF(3) N.A. N.A. 100.0 % (2/2) N.A. N.A. N.A. 100.0 % (2/2)
G_EACH_BUF(4) N.A. N.A. 100.0 % (2/2) N.A. N.A. N.A. 100.0 % (2/2)
G_EACH_BUF(5) N.A. N.A. 100.0 % (2/2) N.A. N.A. N.A. 100.0 % (2/2)
G_EACH_BUF(6) N.A. N.A. 100.0 % (2/2) N.A. N.A. N.A. 100.0 % (2/2)
G_EACH_BUF(7) N.A. N.A. 100.0 % (2/2) N.A. N.A. N.A. 100.0 % (2/2)

Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST 100.0 % (1/1) N.A. 100.0 % (4/4) N.A. N.A. N.A. 100.0 % (5/5)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 112:

112:    clk_delayed <= clk after 1 ps; 
Count: 1090002050
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

 CLK
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Signal:

 CLK_DELAYED
FromToCountThreshold
Bin015449994291
Bin105450010191

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: