NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/err_detector.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ERR_DETECTOR_INST.ERR_PIPELINE_TRUE_GEN	100.0 % (3/3)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (9/9)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ERR_DETECTOR_INST.ERR_PIPELINE_TRUE_GEN

100.0 % (3/3)

100.0 % (4/4)

N.A.

100.0 % (2/2)

N.A.

100.0 % (9/9)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 274 to 278:

274:            if (res_n = '0') then 
275:                err_frm_req <= '0'; 
276:            elsif (rising_edge(clk_sys)) then 
277:                err_frm_req <= err_frm_req_i; 
278:            end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 275:

275: err_frm_req <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 277:

277: err_frm_req <= err_frm_req_i;
Count: 543791678
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 274:

274: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 276:

276: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 274:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1