NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_FSM_INST	100.0 % (29/29)	100.0 % (26/26)	100.0 % (18/18)	100.0 % (18/18)	100.0 % (6/6)	N.A.	100.0 % (97/97)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

143: next_state <= current_state;
Count: 66269811
Threshold: 1

If statement:

145:        if (mr_settings_ena = CTU_CAN_DISABLED) then 
146:            next_state <= s_bt_reset; 
...
159:            end case; 
160:        end if;

Count: 66269811
Threshold: 1

Signal assignment statement:

146: next_state <= s_bt_reset;
Count: 12177
Threshold: 1

Sequential statement:

148:            case current_state is 
149:            when s_bt_tseg1 => 
...
158:                next_state <= s_bt_tseg1; 
159:            end case;

Count: 66257634
Threshold: 1

If statement:

150:                if (segm_end = '1') then 
151:                    next_state <= s_bt_tseg2; 
152:                end if;

Count: 33142302
Threshold: 1

Signal assignment statement:

151: next_state <= s_bt_tseg2;
Count: 22084111
Threshold: 1

If statement:

154:                if (segm_end = '1') then 
155:                    next_state <= s_bt_tseg1; 
156:                end if;

Count: 33104018
Threshold: 1

Signal assignment statement:

155: next_state <= s_bt_tseg1;
Count: 22068948
Threshold: 1

Signal assignment statement:

158: next_state <= s_bt_tseg1;
Count: 11314
Threshold: 1

Signal assignment statement:

169: is_tseg1 <= '0';
Count: 66269811
Threshold: 1

Signal assignment statement:

170: is_tseg2 <= '0';
Count: 66269811
Threshold: 1

Signal assignment statement:

171: rx_trig_req <= '0';
Count: 66269811
Threshold: 1

Signal assignment statement:

172: tx_trig_req <= '0';
Count: 66269811
Threshold: 1

Sequential statement:

174:        case current_state is 
175:        when s_bt_reset => 
...
191: 
192:        end case;

Count: 66269811
Threshold: 1

If statement:

176:            if (mr_settings_ena = CTU_CAN_ENABLED) then 
177:                tx_trig_req <= '1'; 
178:            end if;

Count: 20096
Threshold: 1

Signal assignment statement:

177: tx_trig_req <= '1';
Count: 9714
Threshold: 1

Signal assignment statement:

181: is_tseg1 <= '1';
Count: 33145175
Threshold: 1

If statement:

182:            if (segm_end = '1') then 
183:                rx_trig_req <= '1'; 
184:            end if;

Count: 33145175
Threshold: 1

Signal assignment statement:

183: rx_trig_req <= '1';
Count: 22084225
Threshold: 1

Signal assignment statement:

187: is_tseg2 <= '1';
Count: 33104540
Threshold: 1

If statement:

188:            if (segm_end = '1') then 
189:                tx_trig_req <= '1'; 
190:            end if;

Count: 33104540
Threshold: 1

Signal assignment statement:

189: tx_trig_req <= '1';
Count: 22068989
Threshold: 1

If statement:

200:        if (res_n = '0') then 
201:            current_state <= s_bt_reset; 
...
205:            end if; 
206:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

201: current_state <= s_bt_reset;
Count: 2418499
Threshold: 1

If statement:

203:            if (bt_fsm_ce = '1') then 
204:                current_state <= next_state; 
205:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

204: current_state <= next_state;
Count: 22078404
Threshold: 1

If statement:

209:    bt_fsm_ce <= '1' when (next_state /= current_state) else 
210:                 '0';

Count: 88337194
Threshold: 1

Signal assignment statement:

209: bt_fsm_ce <= '1' when (next_state /= current_state) else
Count: 44168779
Threshold: 1

Signal assignment statement:

210: '0';
Count: 44168415
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

145: if (mr_settings_ena = CTU_CAN_DISABLED) then

	Evaluated to	Count	Threshold
Bin	True	12177	1
Bin	False	66257634	1

"case" / "with" / "select" choice:

149: when s_bt_tseg1 =>

	Choice of	Count	Threshold
Bin	`s_bt_tseg1`	33142302	1

"if" / "when" / "else" condition:

150: if (segm_end = '1') then

	Evaluated to	Count	Threshold
Bin	True	22084111	1
Bin	False	11058191	1

"case" / "with" / "select" choice:

153: when s_bt_tseg2 =>

	Choice of	Count	Threshold
Bin	`s_bt_tseg2`	33104018	1

"if" / "when" / "else" condition:

154: if (segm_end = '1') then

	Evaluated to	Count	Threshold
Bin	True	22068948	1
Bin	False	11035070	1

"case" / "with" / "select" choice:

157: when s_bt_reset =>

	Choice of	Count	Threshold
Bin	`s_bt_reset`	11314	1

"case" / "with" / "select" choice:

175: when s_bt_reset =>

	Choice of	Count	Threshold
Bin	`s_bt_reset`	20096	1

"if" / "when" / "else" condition:

176: if (mr_settings_ena = CTU_CAN_ENABLED) then

	Evaluated to	Count	Threshold
Bin	True	9714	1
Bin	False	10382	1

"case" / "with" / "select" choice:

180: when s_bt_tseg1 =>

	Choice of	Count	Threshold
Bin	`s_bt_tseg1`	33145175	1

"if" / "when" / "else" condition:

182: if (segm_end = '1') then

	Evaluated to	Count	Threshold
Bin	True	22084225	1
Bin	False	11060950	1

"case" / "with" / "select" choice:

186: when s_bt_tseg2 =>

	Choice of	Count	Threshold
Bin	`s_bt_tseg2`	33104540	1

"if" / "when" / "else" condition:

188: if (segm_end = '1') then

	Evaluated to	Count	Threshold
Bin	True	22068989	1
Bin	False	11035551	1

"if" / "when" / "else" condition:

200: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

202: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

203: if (bt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	22078404	1
Bin	False	504295896	1

"if" / "when" / "else" condition:

209: bt_fsm_ce <= '1' when (next_state /= current_state) else

	Evaluated to	Count	Threshold
Bin	True	44168779	1
Bin	False	44168415	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

SEGM_END

	From	To	Count	Threshold
Bin	0	1	22084411	1
Bin	1	0	22086011	1

Port:

IS_TSEG1

	From	To	Count	Threshold
Bin	0	1	11041544	1
Bin	1	0	11041536	1

Port:

IS_TSEG2

	From	To	Count	Threshold
Bin	0	1	11035219	1
Bin	1	0	11036818	1

Port:

RX_TRIG_REQ

	From	To	Count	Threshold
Bin	0	1	22084127	1
Bin	1	0	22085727	1

Port:

TX_TRIG_REQ

	From	To	Count	Threshold
Bin	0	1	22078288	1
Bin	1	0	22079887	1

Signal:

BT_FSM_CE

	From	To	Count	Threshold
Bin	0	1	44166816	1
Bin	1	0	44168415	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

145: if (mr_settings_ena = CTU_CAN_DISABLED) then

	Evaluated to	Count	Threshold
Bin	False	66257634	1
Bin	True	12177	1

"=" expression

150: if (segm_end = '1') then

	Evaluated to	Count	Threshold
Bin	False	11058191	1
Bin	True	22084111	1

"=" expression

154: if (segm_end = '1') then

	Evaluated to	Count	Threshold
Bin	False	11035070	1
Bin	True	22068948	1

"=" expression

176: if (mr_settings_ena = CTU_CAN_ENABLED) then

	Evaluated to	Count	Threshold
Bin	False	10382	1
Bin	True	9714	1

"=" expression

182: if (segm_end = '1') then

	Evaluated to	Count	Threshold
Bin	False	11060950	1
Bin	True	22084225	1

"=" expression

188: if (segm_end = '1') then

	Evaluated to	Count	Threshold
Bin	False	11035551	1
Bin	True	22068989	1

"=" expression

200: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

203: if (bt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	504295896	1
Bin	True	22078404	1

"/=" expression

209: bt_fsm_ce <= '1' when (next_state /= current_state) else

	Evaluated to	Count	Threshold
Bin	False	44168415	1
Bin	True	44168779	1

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

"T_BIT_TIME" FSM

130: signal current_state : t_bit_time;

	State	Count	Threshold
Bin	S_BT_TSEG1	11041544	1
Bin	S_BT_TSEG2	11035219	1
Bin	S_BT_RESET	8072	1

"T_BIT_TIME" FSM

131: signal next_state : t_bit_time;

	State	Count	Threshold
Bin	S_BT_TSEG1	33126706	1
Bin	S_BT_TSEG2	33119181	1
Bin	S_BT_RESET	8072	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_fsm.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

If statement:

Signal assignment statement:

Sequential statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Sequential statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"=" expression

"=" expression

"=" expression

"=" expression

"=" expression

"=" expression