NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST.BYTE_SHIFT_REG_GEN(1)

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_byte.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
NEXT_BYTES_GEN	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (7/7)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST.BYTE_SHIFT_REG_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

153:            if (res_n = G_RESET_POLARITY) then 
154:                shift_reg_q(i) <= (others => '0'); -- G_RESET_VALUE(i * 8 + 7 downto i * 8); 
...
159:                end if; 
160:            end if;

Count: 1055287652
Threshold: 1

Signal assignment statement:

154:                shift_reg_q(i) <= (others => '0'); -- G_RESET_VALUE(i * 8 + 7 downto i * 8);

Count: 2597318
Threshold: 1

If statement:

156:                if (byte_clock_ena(i) = '1') then 
157:                    shift_reg_q(i) <= shift_reg_q(i)(6 downto 0) & 
158:                                         shift_reg_in(i); 
159:                end if;

Count: 526312533
Threshold: 1

Signal assignment statement:

157:                    shift_reg_q(i) <= shift_reg_q(i)(6 downto 0) & 
158:                                         shift_reg_in(i);

Count: 2737922
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

153: if (res_n = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	True	2597318	1
Bin	False	1052690334	1

"if" / "when" / "else" condition:

155: elsif (rising_edge(clk)) then

	Evaluated to	Count	Threshold
Bin	True	526312533	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

156: if (byte_clock_ena(i) = '1') then

	Evaluated to	Count	Threshold
Bin	True	2737922	1
Bin	False	523574611	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

153: if (res_n = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	False	1052690334	1
Bin	True	2597318	1

"=" expression

156: if (byte_clock_ena(i) = '1') then

	Evaluated to	Count	Threshold
Bin	False	523574611	1
Bin	True	2737922	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST.BYTE_SHIFT_REG_GEN(1)

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_byte.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: