File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_byte.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Byte shift register.
71: --
72: -- Purpose:
73: -- Shift register which is split into bytes. Operates in two modes: Linear mode
74: -- and Byte mode. Number of Bytes is configurable. In Linear mode, shift register
75: -- forms one long shift register and input to each byte is output from previous
76: -- byte. In Byte mode, shift register forms N byte shift regsiters and input to
77: -- each byte is directly from input of shift register. Each byte has separate
78: -- clock enable. No pre-load is implemented.
79: --------------------------------------------------------------------------------
80:
81: Library ieee;
82: use ieee.std_logic_1164.all;
83:
84: entity shift_reg_byte is
85: generic (
86: -- Reset polarity
87: G_RESET_POLARITY : std_logic;
88:
89: -- Reset value
90: G_RESET_VALUE : std_logic_vector;
91:
92: -- Shift register width
93: G_NUM_BYTES : natural
94: );
95: port (
96: -------------------------------------------------------------------------------------------
97: -- Clock and Asyncrhonous reset
98: -------------------------------------------------------------------------------------------
99: clk : in std_logic;
100: res_n : in std_logic;
101:
102: -------------------------------------------------------------------------------------------
103: -- Control signals
104: -------------------------------------------------------------------------------------------
105: -- Shift register input
106: input : in std_logic;
107:
108: -- Clock enable for shifting each byte of the shift register.
109: byte_clock_ena : in std_logic_vector(G_NUM_BYTES - 1 downto 0);
110:
111: -- Input source selector for each byte
112: -- (0-Previous byte output, 1- Shift reg input)
113: byte_input_sel : in std_logic_vector(G_NUM_BYTES - 1 downto 1);
114:
115: -------------------------------------------------------------------------------------------
116: -- Status signals
117: -------------------------------------------------------------------------------------------
118: -- Shift register status
119: reg_stat : out std_logic_vector(8 * G_NUM_BYTES - 1 downto 0)
120: );
121: end shift_reg_byte;
122:
123: architecture rtl of shift_reg_byte is
124:
125: type t_byte_shift_reg is array (0 to G_NUM_BYTES - 1) of
126: std_logic_vector(7 downto 0);
127:
128: signal shift_reg_q : t_byte_shift_reg;
129: signal shift_reg_in : std_logic_vector(G_NUM_BYTES - 1 downto 0);
130:
131: begin
132:
133: byte_shift_reg_gen : for i in 0 to G_NUM_BYTES - 1 generate
134: begin
135:
136: first_byte_gen : if (i = 0) generate
137: shift_reg_in(i) <= input;
138: end generate;
139:
140: -- Shift register input mux
141: next_bytes_gen : if (i > 0) generate
142: shift_reg_in(i) <= shift_reg_q(i - 1)(7) when (byte_input_sel(i) = '0')
143: else
144: input;
145: end generate;
146:
147: -------------------------------------------------------------------------------------------
148: -- Shift register assignment
149: -------------------------------------------------------------------------------------------
150: shift_reg_proc : process(clk, res_n)
151: begin
152: if (res_n = G_RESET_POLARITY) then
153: shift_reg_q(i) <= (others => '0'); -- G_RESET_VALUE(i * 8 + 7 downto i * 8);
154: elsif (rising_edge(clk)) then
155: if (byte_clock_ena(i) = '1') then
156: shift_reg_q(i) <= shift_reg_q(i)(6 downto 0) &
157: shift_reg_in(i);
158: end if;
159: end if;
160: end process;
161:
162: -- Propagation to output
163: reg_stat(i * 8 + 7 downto i * 8) <= shift_reg_q(i);
164:
165: end generate;
166:
167: end rtl;