Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| CLK_GATE_TXT_BUFFER_RAM_COMP |
100.0 % (4/4) |
100.0 % (2/2) |
100.0 % (10/10) |
100.0 % (8/8) |
N.A. |
N.A. |
100.0 % (24/24) |
| TXT_BUFFER_RAM_INST |
100.0 % (51/51) |
100.0 % (38/38) |
100.0 % (2160/2160) |
100.0 % (62/62) |
N.A. |
N.A. |
100.0 % (2311/2311) |
| TXT_BUFFER_FSM_INST |
100.0 % (79/79) |
100.0 % (94/94) |
100.0 % (70/70) |
100.0 % (151/151) |
100.0 % (16/16) |
N.A. |
100.0 % (410/410) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
254: else
255: '0'; Count: 93748
Threshold: 1
Signal assignment statement:
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') Count: 45078
Threshold: 1
Signal assignment statement:
255: '0'; Count: 48670
Threshold: 1
If statement:
266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
267: else
268: (others => '0'); Count: 17955
Threshold: 1
Signal assignment statement:
266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') Count: 6078
Threshold: 1
Signal assignment statement:
268: (others => '0'); Count: 11877
Threshold: 1
If statement:
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
277: else
278: '1' when (mr_tst_control_tmaena = '1')
279: else
280: '0'; Count: 145490
Threshold: 1
Signal assignment statement:
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') Count: 70789
Threshold: 1
Signal assignment statement:
278: '1' when (mr_tst_control_tmaena = '1') Count: 636
Threshold: 1
Signal assignment statement:
280: '0'; Count: 74065
Threshold: 1
If statement:
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
288: txtb_parity_check_valid = '1' and
289: txtb_index_muxed = G_ID)
290: else
291: '0'; Count: 138098
Threshold: 1
Signal assignment statement:
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and Count: 346
Threshold: 1
Signal assignment statement:
291: '0'; Count: 137752
Threshold: 1
If statement:
301: if (res_n = '0') then
302: mr_tx_command_txce_q <= '0';
...
308: mr_tx_command_txca_q <= mr_tx_command_txca;
309: end if; Count: 162324562
Threshold: 1
Signal assignment statement:
302: mr_tx_command_txce_q <= '0'; Count: 1737046
Threshold: 1
Signal assignment statement:
303: mr_tx_command_txcr_q <= '0'; Count: 1737046
Threshold: 1
Signal assignment statement:
304: mr_tx_command_txca_q <= '0'; Count: 1737046
Threshold: 1
Signal assignment statement:
306: mr_tx_command_txce_q <= mr_tx_command_txce; Count: 80292006
Threshold: 1
Signal assignment statement:
307: mr_tx_command_txcr_q <= mr_tx_command_txcr; Count: 80292006
Threshold: 1
Signal assignment statement:
308: mr_tx_command_txca_q <= mr_tx_command_txca; Count: 80292006
Threshold: 1
If statement:
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
313: else
314: '0'; Count: 3420
Threshold: 1
Signal assignment statement:
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') Count: 93
Threshold: 1
Signal assignment statement:
314: '0'; Count: 3327
Threshold: 1
If statement:
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
316: else
317: '0'; Count: 21324
Threshold: 1
Signal assignment statement:
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') Count: 1013
Threshold: 1
Signal assignment statement:
317: '0'; Count: 20311
Threshold: 1
If statement:
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
320: else
321: '0'; Count: 5732
Threshold: 1
Signal assignment statement:
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') Count: 181
Threshold: 1
Signal assignment statement:
321: '0'; Count: 5551
Threshold: 1
If statement:
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
324: (txtb_is_bb = '1'))
325: else
326: '0'; Count: 19270
Threshold: 1
Signal assignment statement:
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and Count: 21
Threshold: 1
Signal assignment statement:
326: '0'; Count: 19249
Threshold: 1
Signal assignment statement:
328: abort_or_skipped <= abort_applied or buffer_skipped; Count: 1724
Threshold: 1
If statement:
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
334: else
335: '0'; Count: 2728
Threshold: 1
Signal assignment statement:
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') Count: 175
Threshold: 1
Signal assignment statement:
335: '0'; Count: 2553
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 45078 | 1 |
| Bin | False | 48670 | 1 |
"if" / "when" / "else" condition:
266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 6078 | 1 |
| Bin | False | 11877 | 1 |
"if" / "when" / "else" condition:
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 70789 | 1 |
| Bin | False | 74701 | 1 |
"if" / "when" / "else" condition:
278: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 636 | 1 |
| Bin | False | 74065 | 1 |
"if" / "when" / "else" condition:
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
288: txtb_parity_check_valid = '1' and
289: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 346 | 1 |
| Bin | False | 137752 | 1 |
"if" / "when" / "else" condition:
301: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1737046 | 1 |
| Bin | False | 160587516 | 1 |
"if" / "when" / "else" condition:
305: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 80292006 | 1 |
| Bin | False | 80295510 | 1 |
"if" / "when" / "else" condition:
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 93 | 1 |
| Bin | False | 3327 | 1 |
"if" / "when" / "else" condition:
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1013 | 1 |
| Bin | False | 20311 | 1 |
"if" / "when" / "else" condition:
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 181 | 1 |
| Bin | False | 5551 | 1 |
"if" / "when" / "else" condition:
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
324: (txtb_is_bb = '1')) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 21 | 1 |
| Bin | False | 19249 | 1 |
"if" / "when" / "else" condition:
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 175 | 1 |
| Bin | False | 2553 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 81158777 | 1 |
| Bin | 1 | 0 | 81159437 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2844 | 1 |
| Bin | 1 | 0 | 2844 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4 | 1 |
| Bin | 1 | 0 | 664 | 1 |
Port:
MR_MODE_BMM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12 | 1 |
| Bin | 1 | 0 | 672 | 1 |
Port:
MR_MODE_ROM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32 | 1 |
| Bin | 1 | 0 | 692 | 1 |
Port:
MR_MODE_TXBBM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 688 | 1 |
Port:
MR_SETTINGS_TBFBO | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 784 | 1 |
| Bin | 1 | 0 | 124 | 1 |
Port:
MR_SETTINGS_PCHKE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 770 | 1 |
Port:
MR_TX_COMMAND_TXCE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 340 | 1 |
| Bin | 1 | 0 | 11836 | 1 |
Port:
MR_TX_COMMAND_TXCR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9340 | 1 |
| Bin | 1 | 0 | 11836 | 1 |
Port:
MR_TX_COMMAND_TXCA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1496 | 1 |
| Bin | 1 | 0 | 11836 | 1 |
Port:
MR_TX_COMMAND_TXBI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 380 | 1 |
| Bin | 1 | 0 | 1040 | 1 |
Port:
MR_TST_CONTROL_TMAENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 636 | 1 |
| Bin | 1 | 0 | 1296 | 1 |
Port:
MR_TST_CONTROL_TWRSTB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31329 | 1 |
| Bin | 1 | 0 | 33257 | 1 |
Port:
MR_TST_DEST_TST_ADDR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3406 | 1 |
| Bin | 1 | 0 | 4066 | 1 |
Port:
MR_TST_DEST_TST_ADDR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4810 | 1 |
| Bin | 1 | 0 | 5470 | 1 |
Port:
MR_TST_DEST_TST_ADDR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9862 | 1 |
| Bin | 1 | 0 | 10522 | 1 |
Port:
MR_TST_DEST_TST_ADDR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21367 | 1 |
| Bin | 1 | 0 | 22027 | 1 |
Port:
MR_TST_DEST_TST_ADDR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42723 | 1 |
| Bin | 1 | 0 | 43383 | 1 |
Port:
MR_TST_DEST_TST_MTGT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 214 | 1 |
| Bin | 1 | 0 | 874 | 1 |
Port:
MR_TST_DEST_TST_MTGT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 353 | 1 |
| Bin | 1 | 0 | 1013 | 1 |
Port:
MR_TST_DEST_TST_MTGT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 472 | 1 |
| Bin | 1 | 0 | 1132 | 1 |
Port:
MR_TST_DEST_TST_MTGT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 896 | 1 |
| Bin | 1 | 0 | 1556 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1490 | 1 |
| Bin | 1 | 0 | 2150 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1437 | 1 |
| Bin | 1 | 0 | 2097 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1448 | 1 |
| Bin | 1 | 0 | 2108 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1585 | 1 |
| Bin | 1 | 0 | 2245 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1607 | 1 |
| Bin | 1 | 0 | 2267 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1590 | 1 |
| Bin | 1 | 0 | 2250 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1603 | 1 |
| Bin | 1 | 0 | 2263 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1673 | 1 |
| Bin | 1 | 0 | 2333 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1542 | 1 |
| Bin | 1 | 0 | 2202 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1481 | 1 |
| Bin | 1 | 0 | 2141 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1519 | 1 |
| Bin | 1 | 0 | 2179 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1613 | 1 |
| Bin | 1 | 0 | 2273 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1608 | 1 |
| Bin | 1 | 0 | 2268 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1595 | 1 |
| Bin | 1 | 0 | 2255 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1591 | 1 |
| Bin | 1 | 0 | 2251 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1629 | 1 |
| Bin | 1 | 0 | 2289 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1530 | 1 |
| Bin | 1 | 0 | 2190 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1465 | 1 |
| Bin | 1 | 0 | 2125 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1515 | 1 |
| Bin | 1 | 0 | 2175 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1598 | 1 |
| Bin | 1 | 0 | 2258 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1604 | 1 |
| Bin | 1 | 0 | 2264 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1606 | 1 |
| Bin | 1 | 0 | 2266 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1630 | 1 |
| Bin | 1 | 0 | 2290 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1644 | 1 |
| Bin | 1 | 0 | 2304 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1589 | 1 |
| Bin | 1 | 0 | 2249 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1527 | 1 |
| Bin | 1 | 0 | 2187 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1554 | 1 |
| Bin | 1 | 0 | 2214 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1594 | 1 |
| Bin | 1 | 0 | 2254 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1602 | 1 |
| Bin | 1 | 0 | 2262 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1615 | 1 |
| Bin | 1 | 0 | 2275 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1616 | 1 |
| Bin | 1 | 0 | 2276 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1677 | 1 |
| Bin | 1 | 0 | 2337 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 471 | 1 |
| Bin | 1 | 0 | 1131 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 467 | 1 |
| Bin | 1 | 0 | 1127 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 473 | 1 |
| Bin | 1 | 0 | 1133 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 510 | 1 |
| Bin | 1 | 0 | 1170 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 503 | 1 |
| Bin | 1 | 0 | 1163 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 517 | 1 |
| Bin | 1 | 0 | 1177 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 526 | 1 |
| Bin | 1 | 0 | 1186 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 515 | 1 |
| Bin | 1 | 0 | 1175 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 525 | 1 |
| Bin | 1 | 0 | 1185 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 518 | 1 |
| Bin | 1 | 0 | 1178 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 533 | 1 |
| Bin | 1 | 0 | 1193 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 525 | 1 |
| Bin | 1 | 0 | 1185 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 505 | 1 |
| Bin | 1 | 0 | 1165 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 503 | 1 |
| Bin | 1 | 0 | 1163 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 493 | 1 |
| Bin | 1 | 0 | 1153 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 494 | 1 |
| Bin | 1 | 0 | 1154 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 497 | 1 |
| Bin | 1 | 0 | 1157 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 490 | 1 |
| Bin | 1 | 0 | 1150 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 492 | 1 |
| Bin | 1 | 0 | 1152 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 507 | 1 |
| Bin | 1 | 0 | 1167 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 514 | 1 |
| Bin | 1 | 0 | 1174 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 504 | 1 |
| Bin | 1 | 0 | 1164 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 484 | 1 |
| Bin | 1 | 0 | 1144 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 498 | 1 |
| Bin | 1 | 0 | 1158 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 521 | 1 |
| Bin | 1 | 0 | 1181 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 488 | 1 |
| Bin | 1 | 0 | 1148 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 513 | 1 |
| Bin | 1 | 0 | 1173 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 475 | 1 |
| Bin | 1 | 0 | 1135 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 491 | 1 |
| Bin | 1 | 0 | 1151 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 483 | 1 |
| Bin | 1 | 0 | 1143 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 515 | 1 |
| Bin | 1 | 0 | 1175 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 498 | 1 |
| Bin | 1 | 0 | 1158 | 1 |
Port:
TXTB_PORT_A_DATA_IN(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26356 | 1 |
| Bin | 1 | 0 | 762824 | 1 |
Port:
TXTB_PORT_A_DATA_IN(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28657 | 1 |
| Bin | 1 | 0 | 760523 | 1 |
Port:
TXTB_PORT_A_DATA_IN(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27152 | 1 |
| Bin | 1 | 0 | 762028 | 1 |
Port:
TXTB_PORT_A_DATA_IN(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44044 | 1 |
| Bin | 1 | 0 | 745136 | 1 |
Port:
TXTB_PORT_A_DATA_IN(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37637 | 1 |
| Bin | 1 | 0 | 751543 | 1 |
Port:
TXTB_PORT_A_DATA_IN(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35980 | 1 |
| Bin | 1 | 0 | 753200 | 1 |
Port:
TXTB_PORT_A_DATA_IN(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49211 | 1 |
| Bin | 1 | 0 | 739969 | 1 |
Port:
TXTB_PORT_A_DATA_IN(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36691 | 1 |
| Bin | 1 | 0 | 752489 | 1 |
Port:
TXTB_PORT_A_DATA_IN(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35471 | 1 |
| Bin | 1 | 0 | 753709 | 1 |
Port:
TXTB_PORT_A_DATA_IN(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44528 | 1 |
| Bin | 1 | 0 | 744652 | 1 |
Port:
TXTB_PORT_A_DATA_IN(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 38824 | 1 |
| Bin | 1 | 0 | 750356 | 1 |
Port:
TXTB_PORT_A_DATA_IN(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37253 | 1 |
| Bin | 1 | 0 | 751927 | 1 |
Port:
TXTB_PORT_A_DATA_IN(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 64725 | 1 |
| Bin | 1 | 0 | 724455 | 1 |
Port:
TXTB_PORT_A_DATA_IN(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 84831 | 1 |
| Bin | 1 | 0 | 704349 | 1 |
Port:
TXTB_PORT_A_DATA_IN(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79950 | 1 |
| Bin | 1 | 0 | 709230 | 1 |
Port:
TXTB_PORT_A_DATA_IN(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 141786 | 1 |
| Bin | 1 | 0 | 647394 | 1 |
Port:
TXTB_PORT_A_DATA_IN(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33296 | 1 |
| Bin | 1 | 0 | 755884 | 1 |
Port:
TXTB_PORT_A_DATA_IN(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 41814 | 1 |
| Bin | 1 | 0 | 747366 | 1 |
Port:
TXTB_PORT_A_DATA_IN(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36216 | 1 |
| Bin | 1 | 0 | 752964 | 1 |
Port:
TXTB_PORT_A_DATA_IN(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40217 | 1 |
| Bin | 1 | 0 | 748963 | 1 |
Port:
TXTB_PORT_A_DATA_IN(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58401 | 1 |
| Bin | 1 | 0 | 730779 | 1 |
Port:
TXTB_PORT_A_DATA_IN(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61314 | 1 |
| Bin | 1 | 0 | 727866 | 1 |
Port:
TXTB_PORT_A_DATA_IN(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79096 | 1 |
| Bin | 1 | 0 | 710084 | 1 |
Port:
TXTB_PORT_A_DATA_IN(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80705 | 1 |
| Bin | 1 | 0 | 708475 | 1 |
Port:
TXTB_PORT_A_DATA_IN(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 68788 | 1 |
| Bin | 1 | 0 | 720392 | 1 |
Port:
TXTB_PORT_A_DATA_IN(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 65064 | 1 |
| Bin | 1 | 0 | 724116 | 1 |
Port:
TXTB_PORT_A_DATA_IN(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 65949 | 1 |
| Bin | 1 | 0 | 723231 | 1 |
Port:
TXTB_PORT_A_DATA_IN(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 83106 | 1 |
| Bin | 1 | 0 | 706074 | 1 |
Port:
TXTB_PORT_A_DATA_IN(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 90500 | 1 |
| Bin | 1 | 0 | 698680 | 1 |
Port:
TXTB_PORT_A_DATA_IN(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100212 | 1 |
| Bin | 1 | 0 | 688968 | 1 |
Port:
TXTB_PORT_A_DATA_IN(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 165652 | 1 |
| Bin | 1 | 0 | 623528 | 1 |
Port:
TXTB_PORT_A_DATA_IN(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 141015 | 1 |
| Bin | 1 | 0 | 648165 | 1 |
Port:
TXTB_PORT_A_PARITY | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640015 | 1 |
| Bin | 1 | 0 | 149165 | 1 |
Port:
TXTB_PORT_A_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 249017 | 1 |
| Bin | 1 | 0 | 24501565 | 1 |
Port:
TXTB_PORT_A_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 396175 | 1 |
| Bin | 1 | 0 | 24354407 | 1 |
Port:
TXTB_PORT_A_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 299014 | 1 |
| Bin | 1 | 0 | 24451568 | 1 |
Port:
TXTB_PORT_A_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24194275 | 1 |
| Bin | 1 | 0 | 556307 | 1 |
Port:
TXTB_PORT_A_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15940744 | 1 |
| Bin | 1 | 0 | 8809838 | 1 |
Port:
TXTB_PORT_A_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45318 | 1 |
| Bin | 1 | 0 | 45978 | 1 |
Port:
TXTB_PORT_A_BE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24721305 | 1 |
| Bin | 1 | 0 | 28617 | 1 |
Port:
TXTB_PORT_A_BE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24721613 | 1 |
| Bin | 1 | 0 | 28309 | 1 |
Port:
TXTB_PORT_A_BE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24633047 | 1 |
| Bin | 1 | 0 | 116875 | 1 |
Port:
TXTB_PORT_A_BE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24634059 | 1 |
| Bin | 1 | 0 | 115863 | 1 |
Port:
TXTB_STATE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1118 | 1 |
| Bin | 1 | 0 | 458 | 1 |
Port:
TXTB_STATE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 852 | 1 |
| Bin | 1 | 0 | 1512 | 1 |
Port:
TXTB_STATE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1027 | 1 |
| Bin | 1 | 0 | 1687 | 1 |
Port:
TXTB_STATE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 958 | 1 |
| Bin | 1 | 0 | 1618 | 1 |
Port:
TXTB_IS_BB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37 | 1 |
| Bin | 1 | 0 | 697 | 1 |
Port:
TXTB_HW_CMD_INT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 724 | 1 |
| Bin | 1 | 0 | 1384 | 1 |
Port:
TXTB_HW_CMD.LOCK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9751 | 1 |
| Bin | 1 | 0 | 10411 | 1 |
Port:
TXTB_HW_CMD.VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3808 | 1 |
| Bin | 1 | 0 | 4468 | 1 |
Port:
TXTB_HW_CMD.ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1091 | 1 |
| Bin | 1 | 0 | 1751 | 1 |
Port:
TXTB_HW_CMD.ARBL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44 | 1 |
| Bin | 1 | 0 | 704 | 1 |
Port:
TXTB_HW_CMD.FAILED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4800 | 1 |
| Bin | 1 | 0 | 5460 | 1 |
Port:
TXTB_HW_CMD_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 364 | 1 |
| Bin | 1 | 0 | 1024 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 260 | 1 |
| Bin | 1 | 0 | 920 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 287 | 1 |
| Bin | 1 | 0 | 947 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 927 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1005 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 997 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 973 | 1 |
| Bin | 1 | 0 | 1633 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1052 | 1 |
| Bin | 1 | 0 | 1712 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1049 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1206 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1033 | 1 |
| Bin | 1 | 0 | 1693 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1115 | 1 |
| Bin | 1 | 0 | 1775 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1091 | 1 |
| Bin | 1 | 0 | 1751 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1122 | 1 |
| Bin | 1 | 0 | 1782 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1017 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 661 | 1 |
| Bin | 1 | 0 | 1321 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 769 | 1 |
| Bin | 1 | 0 | 1429 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 647 | 1 |
| Bin | 1 | 0 | 1307 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 636 | 1 |
| Bin | 1 | 0 | 1296 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 738 | 1 |
| Bin | 1 | 0 | 1398 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 791 | 1 |
| Bin | 1 | 0 | 1451 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 759 | 1 |
| Bin | 1 | 0 | 1419 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 816 | 1 |
| Bin | 1 | 0 | 1476 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1059 | 1 |
| Bin | 1 | 0 | 1719 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 717 | 1 |
| Bin | 1 | 0 | 1377 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1394 | 1 |
| Bin | 1 | 0 | 2054 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1155 | 1 |
| Bin | 1 | 0 | 1815 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1117 | 1 |
| Bin | 1 | 0 | 1777 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 678 | 1 |
| Bin | 1 | 0 | 1338 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 979 | 1 |
| Bin | 1 | 0 | 1639 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1042 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1110 | 1 |
| Bin | 1 | 0 | 1770 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1219 | 1 |
| Bin | 1 | 0 | 1879 | 1 |
Port:
TXTB_PORT_B_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10515 | 1 |
| Bin | 1 | 0 | 11175 | 1 |
Port:
TXTB_PORT_B_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 346 | 1 |
| Bin | 1 | 0 | 1006 | 1 |
Port:
TXTB_PORT_B_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15447 | 1 |
| Bin | 1 | 0 | 16107 | 1 |
Port:
TXTB_PORT_B_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12158 | 1 |
| Bin | 1 | 0 | 12158 | 1 |
Port:
TXTB_PORT_B_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34271 | 1 |
| Bin | 1 | 0 | 34931 | 1 |
Port:
TXTB_PORT_B_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25711 | 1 |
| Bin | 1 | 0 | 26371 | 1 |
Port:
IS_BUS_OFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2960 | 1 |
| Bin | 1 | 0 | 2960 | 1 |
Port:
TXTB_AVAILABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1049 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
Port:
TXTB_ALLOW_BB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 896 | 1 |
| Bin | 1 | 0 | 1556 | 1 |
Port:
TXTB_PARITY_CHECK_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56623 | 1 |
| Bin | 1 | 0 | 57283 | 1 |
Port:
TXTB_PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1541 | 1 |
| Bin | 1 | 0 | 2201 | 1 |
Port:
TXTB_PARITY_ERROR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 346 | 1 |
| Bin | 1 | 0 | 1006 | 1 |
Port:
TXTB_BB_PARITY_ERROR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 175 | 1 |
| Bin | 1 | 0 | 835 | 1 |
Signal:
TXTB_USER_ACCESSIBLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1556 | 1 |
| Bin | 1 | 0 | 896 | 1 |
Signal:
TXTB_UNMASK_DATA_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 896 | 1 |
| Bin | 1 | 0 | 1556 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 797 | 1 |
| Bin | 1 | 0 | 1417 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 824 | 1 |
| Bin | 1 | 0 | 1444 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 888 | 1 |
| Bin | 1 | 0 | 1508 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2429 | 1 |
| Bin | 1 | 0 | 3038 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2410 | 1 |
| Bin | 1 | 0 | 3009 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2341 | 1 |
| Bin | 1 | 0 | 2951 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2351 | 1 |
| Bin | 1 | 0 | 2956 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2251 | 1 |
| Bin | 1 | 0 | 2861 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2638 | 1 |
| Bin | 1 | 0 | 3241 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2473 | 1 |
| Bin | 1 | 0 | 3078 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2750 | 1 |
| Bin | 1 | 0 | 3346 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2473 | 1 |
| Bin | 1 | 0 | 3078 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2365 | 1 |
| Bin | 1 | 0 | 2962 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2495 | 1 |
| Bin | 1 | 0 | 3095 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1523 | 1 |
| Bin | 1 | 0 | 2137 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1651 | 1 |
| Bin | 1 | 0 | 2267 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1565 | 1 |
| Bin | 1 | 0 | 2180 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1605 | 1 |
| Bin | 1 | 0 | 2219 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1539 | 1 |
| Bin | 1 | 0 | 2155 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1729 | 1 |
| Bin | 1 | 0 | 2341 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1747 | 1 |
| Bin | 1 | 0 | 2361 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1696 | 1 |
| Bin | 1 | 0 | 2311 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2507 | 1 |
| Bin | 1 | 0 | 3109 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1680 | 1 |
| Bin | 1 | 0 | 2293 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3152 | 1 |
| Bin | 1 | 0 | 3741 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2395 | 1 |
| Bin | 1 | 0 | 2993 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2387 | 1 |
| Bin | 1 | 0 | 2999 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1721 | 1 |
| Bin | 1 | 0 | 2337 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1906 | 1 |
| Bin | 1 | 0 | 2506 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2312 | 1 |
| Bin | 1 | 0 | 2911 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2184 | 1 |
| Bin | 1 | 0 | 2778 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2823 | 1 |
| Bin | 1 | 0 | 3416 | 1 |
Signal:
TXTB_PARITY_ERROR_VALID_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 346 | 1 |
| Bin | 1 | 0 | 1006 | 1 |
Signal:
MR_TX_COMMAND_TXCE_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 340 | 1 |
| Bin | 1 | 0 | 1000 | 1 |
Signal:
MR_TX_COMMAND_TXCR_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9292 | 1 |
| Bin | 1 | 0 | 9952 | 1 |
Signal:
MR_TX_COMMAND_TXCA_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1496 | 1 |
| Bin | 1 | 0 | 2156 | 1 |
Signal:
TX_COMMAND_TXCE_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 93 | 1 |
| Bin | 1 | 0 | 753 | 1 |
Signal:
TX_COMMAND_TXCR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1013 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
Signal:
ABORT_APPLIED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 181 | 1 |
| Bin | 1 | 0 | 841 | 1 |
Signal:
BUFFER_SKIPPED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 681 | 1 |
Signal:
ABORT_OR_SKIPPED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 202 | 1 |
| Bin | 1 | 0 | 862 | 1 |
Signal:
TXTB_PORT_A_WRITE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45078 | 1 |
| Bin | 1 | 0 | 45738 | 1 |
Signal:
TXTB_RAM_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 71425 | 1 |
| Bin | 1 | 0 | 72085 | 1 |
Signal:
CLK_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13640743 | 1 |
| Bin | 1 | 0 | 13641403 | 1 |
Signal:
PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1541 | 1 |
| Bin | 1 | 0 | 2201 | 1 |
Covered expressions:
"=" expression
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 48430 | 1 |
| Bin | True | 45318 | 1 |
"=" expression
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2036 | 1 |
| Bin | True | 91712 | 1 |
"and" expression
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
<-------LHS--------> <----------RHS-----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 46634 | 1 |
| Bin | True | False | 240 | 1 |
| Bin | True | True | 45078 | 1 |
"=" expression
266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 11877 | 1 |
| Bin | True | 6078 | 1 |
"=" expression
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 119779 | 1 |
| Bin | True | 25711 | 1 |
"=" expression
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 100412 | 1 |
| Bin | True | 45078 | 1 |
"or" expression
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
<---------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 74701 | 1 |
| Bin | False | True | 45078 | 1 |
| Bin | True | False | 25711 | 1 |
"=" expression
278: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 74065 | 1 |
| Bin | True | 636 | 1 |
"=" expression
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 132646 | 1 |
| Bin | True | 5452 | 1 |
"=" expression
288: txtb_parity_check_valid = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 79882 | 1 |
| Bin | True | 58216 | 1 |
"and" expression
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
288: txtb_parity_check_valid = '1' and | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 55593 | 1 |
| Bin | True | False | 2829 | 1 |
| Bin | True | True | 2623 | 1 |
"=" expression
289: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 116790 | 1 |
| Bin | True | 21308 | 1 |
"and" expression
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
288: txtb_parity_check_valid = '1' and
289: txtb_index_muxed = G_ID) | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 20962 | 1 |
| Bin | True | False | 2277 | 1 |
| Bin | True | True | 346 | 1 |
"=" expression
301: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 160587516 | 1 |
| Bin | True | 1737046 | 1 |
"=" expression
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 3067 | 1 |
| Bin | True | 353 | 1 |
"=" expression
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2867 | 1 |
| Bin | True | 553 | 1 |
"and" expression
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 460 | 1 |
| Bin | True | False | 260 | 1 |
| Bin | True | True | 93 | 1 |
"=" expression
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 11543 | 1 |
| Bin | True | 9781 | 1 |
"=" expression
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 19407 | 1 |
| Bin | True | 1917 | 1 |
"and" expression
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 904 | 1 |
| Bin | True | False | 8768 | 1 |
| Bin | True | True | 1013 | 1 |
"=" expression
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 4236 | 1 |
| Bin | True | 1496 | 1 |
"=" expression
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 4990 | 1 |
| Bin | True | 742 | 1 |
"and" expression
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 561 | 1 |
| Bin | True | False | 1315 | 1 |
| Bin | True | True | 181 | 1 |
"=" expression
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 14470 | 1 |
| Bin | True | 4800 | 1 |
"=" expression
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 15462 | 1 |
| Bin | True | 3808 | 1 |
"or" expression
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
<---------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 10662 | 1 |
| Bin | False | True | 3808 | 1 |
| Bin | True | False | 4800 | 1 |
"=" expression
324: (txtb_is_bb = '1')) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 19191 | 1 |
| Bin | True | 79 | 1 |
"and" expression
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
324: (txtb_is_bb = '1')) | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 58 | 1 |
| Bin | True | False | 8587 | 1 |
| Bin | True | True | 21 | 1 |
"or" expression
328: abort_or_skipped <= abort_applied or buffer_skipped;
<----LHS----> <----RHS-----> | LHS | RHS | Count | Threshold |
|---|
| Bin | '0' | '0' | 862 | 1 |
| Bin | '0' | '1' | 21 | 1 |
| Bin | '1' | '0' | 181 | 1 |
"=" expression
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2382 | 1 |
| Bin | True | 346 | 1 |
"=" expression
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2350 | 1 |
| Bin | True | 378 | 1 |
"and" expression
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
<-------------LHS-------------> <-------RHS-------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 203 | 1 |
| Bin | True | False | 171 | 1 |
| Bin | True | True | 175 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: