NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CLK_GATE_TXT_BUFFER_RAM_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
TXT_BUFFER_RAM_INST	100.0 % (52/52)	100.0 % (38/38)	100.0 % (2160/2160)	93.1 % (54/58)	N.A.	N.A.	99.8 % (2304/2308)
TXT_BUFFER_FSM_INST	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CLK_GATE_TXT_BUFFER_RAM_COMP

100.0 % (5/5)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (25/25)

TXT_BUFFER_RAM_INST

100.0 % (52/52)

100.0 % (38/38)

100.0 % (2160/2160)

93.1 % (54/58)

N.A.

99.8 % (2304/2308)

TXT_BUFFER_FSM_INST

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST	100.0 % (38/38)	100.0 % (24/24)	100.0 % (468/468)	100.0 % (75/75)	N.A.	N.A.	100.0 % (605/605)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST

100.0 % (38/38)

100.0 % (24/24)

100.0 % (468/468)

100.0 % (75/75)

N.A.

100.0 % (605/605)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 255:

253:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
254:                             else 
255:                         '0';

Count: 93718
Threshold: 1

Signal assignment statement on line 253:

253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 45074
Threshold: 1

Signal assignment statement on line 255:

255: '0';
Count: 48644
Threshold: 1

If statement on lines 266 to 268:

266:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
267:                                                   else 
268:                                    (others => '0');

Count: 18137
Threshold: 1

Signal assignment statement on line 266:

266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 6212
Threshold: 1

Signal assignment statement on line 268:

268: (others => '0');
Count: 11925
Threshold: 1

If statement on lines 276 to 280:

276:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
277:                           else 
278:                       '1' when (mr_tst_control_tmaena = '1') 
279:                           else 
280:                       '0';

Count: 149862
Threshold: 1

Signal assignment statement on line 276:

276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 72975
Threshold: 1

Signal assignment statement on line 278:

278: '1' when (mr_tst_control_tmaena = '1')
Count: 636
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 76251
Threshold: 1

If statement on lines 287 to 291:

287:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
288:                                           txtb_parity_check_valid = '1' and 
289:                                           txtb_index_muxed = G_ID) 
290:                                     else 
291:                                 '0';

Count: 144706
Threshold: 1

Signal assignment statement on line 287:

287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 342
Threshold: 1

Signal assignment statement on line 291:

291: '0';
Count: 144364
Threshold: 1

Signal assignment statement on line 293:

293: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 2004
Threshold: 1

If statement on lines 301 to 309:

301:        if (res_n = '0') then 
302:            mr_tx_command_txce_q <= '0'; 
...
308:            mr_tx_command_txca_q <= mr_tx_command_txca; 
309:        end if;

Count: 165318284
Threshold: 1

Signal assignment statement on line 302:

302: mr_tx_command_txce_q <= '0';
Count: 1737682
Threshold: 1

Signal assignment statement on line 303:

303: mr_tx_command_txcr_q <= '0';
Count: 1737682
Threshold: 1

Signal assignment statement on line 304:

304: mr_tx_command_txca_q <= '0';
Count: 1737682
Threshold: 1

Signal assignment statement on line 306:

306: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 81788549
Threshold: 1

Signal assignment statement on line 307:

307: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 81788549
Threshold: 1

Signal assignment statement on line 308:

308: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 81788549
Threshold: 1

If statement on lines 312 to 314:

312:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
313:                                 else 
314:                             '0';

Count: 3420
Threshold: 1

Signal assignment statement on line 312:

312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 93
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 3327
Threshold: 1

If statement on lines 315 to 317:

315:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
316:                                 else 
317:                             '0';

Count: 21944
Threshold: 1

Signal assignment statement on line 315:

315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 1004
Threshold: 1

Signal assignment statement on line 317:

317: '0';
Count: 20940
Threshold: 1

If statement on lines 319 to 321:

319:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
320:                         else 
321:                     '0';

Count: 5732
Threshold: 1

Signal assignment statement on line 319:

319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 181
Threshold: 1

Signal assignment statement on line 321:

321: '0';
Count: 5551
Threshold: 1

If statement on lines 323 to 326:

323:    buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and 
324:                                (txtb_is_bb = '1')) 
325:                        else 
326:                    '0';

Count: 19860
Threshold: 1

Signal assignment statement on line 323:

323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
Count: 23
Threshold: 1

Signal assignment statement on line 326:

326: '0';
Count: 19837
Threshold: 1

Signal assignment statement on line 328:

328: abort_or_skipped <= abort_applied or buffer_skipped;
Count: 1728
Threshold: 1

If statement on lines 333 to 335:

333:    txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') 
334:                                else 
335:                            '0';

Count: 2720
Threshold: 1

Signal assignment statement on line 333:

333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
Count: 166
Threshold: 1

Signal assignment statement on line 335:

335: '0';
Count: 2554
Threshold: 1

Signal assignment statement on line 423:

423: txtb_parity_mismatch <= parity_mismatch;
Count: 4026
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	45074	1
Bin	False	48644	1

"if" / "when" / "else" condition on line 266:

266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	6212	1
Bin	False	11925	1

"if" / "when" / "else" condition on line 276:

276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	72975	1
Bin	False	76887	1

"if" / "when" / "else" condition on line 278:

278: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	636	1
Bin	False	76251	1

"if" / "when" / "else" condition on lines 287 to 289:

287:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
288:                                           txtb_parity_check_valid = '1' and 
289:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	342	1
Bin	False	144364	1

"if" / "when" / "else" condition on line 301:

301: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	1737682	1
Bin	False	163580602	1

"if" / "when" / "else" condition on line 305:

305: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	81788549	1
Bin	False	81792053	1

"if" / "when" / "else" condition on line 312:

312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	93	1
Bin	False	3327	1

"if" / "when" / "else" condition on line 315:

315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	1004	1
Bin	False	20940	1

"if" / "when" / "else" condition on line 319:

319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	181	1
Bin	False	5551	1

"if" / "when" / "else" condition on lines 323 to 324:

323:    buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and 
324:                                (txtb_is_bb = '1'))

	Evaluated to	Count	Threshold
Bin	True	23	1
Bin	False	19837	1

"if" / "when" / "else" condition on line 333:

333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')

	Evaluated to	Count	Threshold
Bin	True	166	1
Bin	False	2554	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_IS_BB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	480	1
Bin	(31)	1	0	1140	1
Bin	(30)	0	1	480	1
Bin	(30)	1	0	1140	1
Bin	(29)	0	1	456	1
Bin	(29)	1	0	1116	1
Bin	(28)	0	1	505	1
Bin	(28)	1	0	1165	1
Bin	(27)	0	1	503	1
Bin	(27)	1	0	1163	1
Bin	(26)	0	1	506	1
Bin	(26)	1	0	1166	1
Bin	(25)	0	1	509	1
Bin	(25)	1	0	1169	1
Bin	(24)	0	1	493	1
Bin	(24)	1	0	1153	1
Bin	(23)	0	1	515	1
Bin	(23)	1	0	1175	1
Bin	(22)	0	1	502	1
Bin	(22)	1	0	1162	1
Bin	(21)	0	1	531	1
Bin	(21)	1	0	1191	1
Bin	(20)	0	1	517	1
Bin	(20)	1	0	1177	1
Bin	(19)	0	1	512	1
Bin	(19)	1	0	1172	1
Bin	(18)	0	1	526	1
Bin	(18)	1	0	1186	1
Bin	(17)	0	1	493	1
Bin	(17)	1	0	1153	1
Bin	(16)	0	1	483	1
Bin	(16)	1	0	1143	1
Bin	(15)	0	1	512	1
Bin	(15)	1	0	1172	1
Bin	(14)	0	1	510	1
Bin	(14)	1	0	1170	1
Bin	(13)	0	1	512	1
Bin	(13)	1	0	1172	1
Bin	(12)	0	1	497	1
Bin	(12)	1	0	1157	1
Bin	(11)	0	1	498	1
Bin	(11)	1	0	1158	1
Bin	(10)	0	1	514	1
Bin	(10)	1	0	1174	1
Bin	(9)	0	1	507	1
Bin	(9)	1	0	1167	1
Bin	(8)	0	1	516	1
Bin	(8)	1	0	1176	1
Bin	(7)	0	1	519	1
Bin	(7)	1	0	1179	1
Bin	(6)	0	1	491	1
Bin	(6)	1	0	1151	1
Bin	(5)	0	1	507	1
Bin	(5)	1	0	1167	1
Bin	(4)	0	1	503	1
Bin	(4)	1	0	1163	1
Bin	(3)	0	1	501	1
Bin	(3)	1	0	1161	1
Bin	(2)	0	1	496	1
Bin	(2)	1	0	1156	1
Bin	(1)	0	1	512	1
Bin	(1)	1	0	1172	1
Bin	(0)	0	1	499	1
Bin	(0)	1	0	1159	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1120	1
Bin	(3)	1	0	460	1
Bin	(2)	0	1	838	1
Bin	(2)	1	0	1498	1
Bin	(1)	0	1	1020	1
Bin	(1)	1	0	1680	1
Bin	(0)	0	1	948	1
Bin	(0)	1	0	1608	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	707	1
Bin	1	0	1367	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	10075	1
Bin	LOCK	1	0	10735	1
Bin	VALID	0	1	3820	1
Bin	VALID	1	0	4480	1
Bin	ERR	0	1	1122	1
Bin	ERR	1	0	1782	1
Bin	ARBL	0	1	44	1
Bin	ARBL	1	0	704	1
Bin	FAILED	0	1	5081	1
Bin	FAILED	1	0	5741	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	276	1
Bin	(31)	1	0	936	1
Bin	(30)	0	1	334	1
Bin	(30)	1	0	994	1
Bin	(29)	0	1	270	1
Bin	(29)	1	0	930	1
Bin	(28)	0	1	1039	1
Bin	(28)	1	0	1699	1
Bin	(27)	0	1	1072	1
Bin	(27)	1	0	1732	1
Bin	(26)	0	1	1112	1
Bin	(26)	1	0	1772	1
Bin	(25)	0	1	1035	1
Bin	(25)	1	0	1695	1
Bin	(24)	0	1	1035	1
Bin	(24)	1	0	1695	1
Bin	(23)	0	1	1077	1
Bin	(23)	1	0	1737	1
Bin	(22)	0	1	1078	1
Bin	(22)	1	0	1738	1
Bin	(21)	0	1	1054	1
Bin	(21)	1	0	1714	1
Bin	(20)	0	1	1099	1
Bin	(20)	1	0	1759	1
Bin	(19)	0	1	1076	1
Bin	(19)	1	0	1736	1
Bin	(18)	0	1	1079	1
Bin	(18)	1	0	1739	1
Bin	(17)	0	1	634	1
Bin	(17)	1	0	1294	1
Bin	(16)	0	1	679	1
Bin	(16)	1	0	1339	1
Bin	(15)	0	1	751	1
Bin	(15)	1	0	1411	1
Bin	(14)	0	1	751	1
Bin	(14)	1	0	1411	1
Bin	(13)	0	1	712	1
Bin	(13)	1	0	1372	1
Bin	(12)	0	1	699	1
Bin	(12)	1	0	1359	1
Bin	(11)	0	1	719	1
Bin	(11)	1	0	1379	1
Bin	(10)	0	1	860	1
Bin	(10)	1	0	1520	1
Bin	(9)	0	1	1107	1
Bin	(9)	1	0	1767	1
Bin	(8)	0	1	757	1
Bin	(8)	1	0	1417	1
Bin	(7)	0	1	1423	1
Bin	(7)	1	0	2083	1
Bin	(6)	0	1	1278	1
Bin	(6)	1	0	1938	1
Bin	(5)	0	1	1003	1
Bin	(5)	1	0	1663	1
Bin	(4)	0	1	884	1
Bin	(4)	1	0	1544	1
Bin	(3)	0	1	972	1
Bin	(3)	1	0	1632	1
Bin	(2)	0	1	988	1
Bin	(2)	1	0	1648	1
Bin	(1)	0	1	1147	1
Bin	(1)	1	0	1807	1
Bin	(0)	0	1	1176	1
Bin	(0)	1	0	1836	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	1046	1
Bin	1	0	1706	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	885	1
Bin	1	0	1545	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1353	1
Bin	1	0	2013	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	342	1
Bin	1	0	1002	1

Port:

TXTB_BB_PARITY_ERROR

	From	To	Count	Threshold
Bin	0	1	166	1
Bin	1	0	826	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	1545	1
Bin	1	0	885	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	885	1
Bin	1	0	1545	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	885	1
Bin	(31)	1	0	1505	1
Bin	(30)	0	1	984	1
Bin	(30)	1	0	1604	1
Bin	(29)	0	1	847	1
Bin	(29)	1	0	1467	1
Bin	(28)	0	1	2160	1
Bin	(28)	1	0	2771	1
Bin	(27)	0	1	2417	1
Bin	(27)	1	0	3028	1
Bin	(26)	0	1	2077	1
Bin	(26)	1	0	2685	1
Bin	(25)	0	1	2315	1
Bin	(25)	1	0	2925	1
Bin	(24)	0	1	2240	1
Bin	(24)	1	0	2843	1
Bin	(23)	0	1	2433	1
Bin	(23)	1	0	3044	1
Bin	(22)	0	1	2383	1
Bin	(22)	1	0	2993	1
Bin	(21)	0	1	2495	1
Bin	(21)	1	0	3098	1
Bin	(20)	0	1	2487	1
Bin	(20)	1	0	3093	1
Bin	(19)	0	1	2547	1
Bin	(19)	1	0	3151	1
Bin	(18)	0	1	2396	1
Bin	(18)	1	0	3004	1
Bin	(17)	0	1	1628	1
Bin	(17)	1	0	2246	1
Bin	(16)	0	1	1683	1
Bin	(16)	1	0	2299	1
Bin	(15)	0	1	1775	1
Bin	(15)	1	0	2394	1
Bin	(14)	0	1	1982	1
Bin	(14)	1	0	2599	1
Bin	(13)	0	1	1839	1
Bin	(13)	1	0	2454	1
Bin	(12)	0	1	1509	1
Bin	(12)	1	0	2126	1
Bin	(11)	0	1	1491	1
Bin	(11)	1	0	2109	1
Bin	(10)	0	1	2125	1
Bin	(10)	1	0	2742	1
Bin	(9)	0	1	2310	1
Bin	(9)	1	0	2909	1
Bin	(8)	0	1	1913	1
Bin	(8)	1	0	2529	1
Bin	(7)	0	1	3053	1
Bin	(7)	1	0	3634	1
Bin	(6)	0	1	2921	1
Bin	(6)	1	0	3513	1
Bin	(5)	0	1	2760	1
Bin	(5)	1	0	3374	1
Bin	(4)	0	1	1997	1
Bin	(4)	1	0	2612	1
Bin	(3)	0	1	2193	1
Bin	(3)	1	0	2793	1
Bin	(2)	0	1	2128	1
Bin	(2)	1	0	2727	1
Bin	(1)	0	1	2225	1
Bin	(1)	1	0	2824	1
Bin	(0)	0	1	2520	1
Bin	(0)	1	0	3115	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	342	1
Bin	1	0	1002	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	1000	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	9602	1
Bin	1	0	10262	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	1496	1
Bin	1	0	2156	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	753	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	1004	1
Bin	1	0	1664	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	841	1

Signal:

BUFFER_SKIPPED

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	683	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	864	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	45074	1
Bin	1	0	45734	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	73611	1
Bin	1	0	74271	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	14859416	1
Bin	1	0	14860076	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1353	1
Bin	1	0	2013	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 253:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	46619	1
Bin	True	False	240	1
Bin	True	True	45074	1

"=" expression on line 253:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	48404	1
Bin	True	45314	1

"=" expression on line 253:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	2025	1
Bin	True	91693	1

"=" expression on line 266:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	11925	1
Bin	True	6212	1

"or" expression on line 276:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	76887	1
Bin	False	True	45074	1
Bin	True	False	27901	1

"=" expression on line 276:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	121961	1
Bin	True	27901	1

"=" expression on line 276:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	104788	1
Bin	True	45074	1

"=" expression on line 278:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	76251	1
Bin	True	636	1

"and" expression on lines 287 to 289:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	21594	1
Bin	True	False	2039	1
Bin	True	True	342	1

"and" expression on lines 287 to 288:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	58676	1
Bin	True	False	2850	1
Bin	True	True	2381	1

"=" expression on line 287:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	139475	1
Bin	True	5231	1

"=" expression on line 288:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	83649	1
Bin	True	61057	1

"=" expression on line 289:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	122770	1
Bin	True	21936	1

"=" expression on line 301:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	163580602	1
Bin	True	1737682	1

"and" expression on line 312:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	460	1
Bin	True	False	260	1
Bin	True	True	93	1

"=" expression on line 312:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	3067	1
Bin	True	353	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	2867	1
Bin	True	553	1

"and" expression on line 315:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	891	1
Bin	True	False	9091	1
Bin	True	True	1004	1

"=" expression on line 315:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	11849	1
Bin	True	10095	1

"=" expression on line 315:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	20049	1
Bin	True	1895	1

"and" expression on line 319:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	561	1
Bin	True	False	1315	1
Bin	True	True	181	1

"=" expression on line 319:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	4236	1
Bin	True	1496	1

"=" expression on line 319:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	4990	1
Bin	True	742	1

"and" expression on lines 323 to 324:

 (txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and (txtb_is_bb = '1') 
  <-----------------------LHS----------------------->       <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	62	1
Bin	True	False	8878	1
Bin	True	True	23	1

"or" expression on line 323:

 txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	10959	1
Bin	False	True	3820	1
Bin	True	False	5081	1

"=" expression on line 323:

txtb_hw_cmd.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	14779	1
Bin	True	5081	1

"=" expression on line 323:

txtb_hw_cmd.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	16040	1
Bin	True	3820	1

"=" expression on line 324:

txtb_is_bb = '1'

	Evaluated to	Count	Threshold
Bin	False	19775	1
Bin	True	85	1

"or" expression on line 328:

 abort_applied or buffer_skipped 
 <----LHS---->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	864	1
Bin	'0'	'1'	23	1
Bin	'1'	'0'	181	1

"and" expression on line 333:

 txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1' 
 <-------------LHS------------->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	194	1
Bin	True	False	176	1
Bin	True	True	166	1

"=" expression on line 333:

txtb_parity_error_valid_i = '1'

	Evaluated to	Count	Threshold
Bin	False	2378	1
Bin	True	342	1

"=" expression on line 333:

mr_mode_txbbm = '1'

	Evaluated to	Count	Threshold
Bin	False	2360	1
Bin	True	360	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 255:

Signal assignment statement on line 253:

Signal assignment statement on line 255:

If statement on lines 266 to 268:

Signal assignment statement on line 266:

Signal assignment statement on line 268:

If statement on lines 276 to 280:

Signal assignment statement on line 276:

Signal assignment statement on line 278:

Signal assignment statement on line 280:

If statement on lines 287 to 291:

Signal assignment statement on line 287:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 301 to 309:

Signal assignment statement on line 302:

Signal assignment statement on line 303:

Signal assignment statement on line 304:

Signal assignment statement on line 306:

Signal assignment statement on line 307:

Signal assignment statement on line 308:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

If statement on lines 315 to 317:

Signal assignment statement on line 315:

Signal assignment statement on line 317:

If statement on lines 319 to 321:

Signal assignment statement on line 319:

Signal assignment statement on line 321:

If statement on lines 323 to 326:

Signal assignment statement on line 323:

Signal assignment statement on line 326:

Signal assignment statement on line 328:

If statement on lines 333 to 335:

Signal assignment statement on line 333:

Signal assignment statement on line 335:

Signal assignment statement on line 423:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

"if" / "when" / "else" condition on line 266:

"if" / "when" / "else" condition on line 276:

"if" / "when" / "else" condition on line 278:

"if" / "when" / "else" condition on lines 287 to 289:

"if" / "when" / "else" condition on line 301:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 312:

"if" / "when" / "else" condition on line 315:

"if" / "when" / "else" condition on line 319:

"if" / "when" / "else" condition on lines 323 to 324:

"if" / "when" / "else" condition on line 333:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port: