NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_PRESCALER_DBT_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_prescaler_dbt.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_PRESCALER_DBT_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (9/9) 100.0 % (11/11)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK
FromToCountThreshold
Bin015275788681
Bin105275804601

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

132:    -- psl dbt_pos_resync_e_less_than_sjw_cov : cover 
133:    --  {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1' 
134:    --   and resync_edge_valid = '1' and 
135:    --   (to_integer(unsigned(phase_err)) < to_integer(unsigned(sjw)))}; 
Count: 551163
Threshold: 1

PSL cover point:

138:    -- psl dbt_pos_resync_e_more_than_sjw_cov : cover 
139:    --  {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1' 
140:    --   and resync_edge_valid = '1' and 
141:    --   (to_integer(unsigned(phase_err)) > to_integer(unsigned(sjw)))}; 
Count: 86576
Threshold: 1

PSL cover point:

144:    -- psl dbt_pos_resync_e_equal_sjw_cov : cover 
145:    --  {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1' 
146:    --   and resync_edge_valid = '1' and 
147:    --   (to_integer(unsigned(phase_err)) = to_integer(unsigned(sjw)))}; 
Count: 63831
Threshold: 1

PSL cover point:

150:    -- psl dbt_neg_resync_e_less_than_sjw_cov : cover 
151:    --  {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and 
152:    --   (to_integer(unsigned(phase_err)) < to_integer(unsigned(sjw)))}; 
Count: 6723
Threshold: 1

PSL cover point:

155:    -- psl dbt_neg_resync_e_more_than_sjw_cov : cover 
156:    --  {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and 
157:    --   (to_integer(unsigned(phase_err)) > to_integer(unsigned(sjw)))}; 
Count: 9185
Threshold: 1

PSL cover point:

160:    -- psl dbt_neg_resync_e_equal_sjw_cov : cover 
161:    --  {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and 
162:    --   (to_integer(unsigned(phase_err)) = to_integer(unsigned(sjw)))}; 
Count: 840
Threshold: 1

PSL cover point:

164:    -- psl dbt_exit_segm_immediate_cov : cover 
165:    --  {exit_segm_req = '1' and exit_ph2_immediate = '1'}; 
Count: 7720
Threshold: 1

PSL cover point:

167:    -- psl dbt_exit_segm_regular_tseg1_cov : cover 
168:    --  {exit_segm_req = '1' and exit_segm_regular_tseg1 = '1' and exit_segm_regular_tseg2 = '0'}; 
Count: 8347918
Threshold: 1

PSL cover point:

170:    -- psl dbt_exit_segm_regular_tseg2_cov : cover 
171:    --  {exit_segm_req = '1' and exit_segm_regular_tseg1 = '0' and exit_segm_regular_tseg2 = '1'}; 
Count: 8282212
Threshold: 1