NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DFF_ENA_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
DFF_FIXED_STUFF_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)
DFF_DATA_OUT_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)
DFF_HALT_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_STUFFING_INST	100.0 % (62/62)	100.0 % (56/56)	100.0 % (92/92)	100.0 % (115/115)	N.A.	N.A.	100.0 % (325/325)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

227:    non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0') 
228:                               else 
229:                           '0';

Count: 48128
Threshold: 1

Signal assignment statement:

227: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0')
Count: 13466
Threshold: 1

Signal assignment statement:

229: '0';
Count: 34662
Threshold: 1

If statement:

236:    fixed_reg_d <= '0'         when (enable_prev = '0') else 
237:                   fixed_stuff when (bst_trigger = '1') else 
238:                   fixed_reg_q;

Count: 22186518
Threshold: 1

Signal assignment statement:

236: fixed_reg_d <= '0' when (enable_prev = '0') else
Count: 16506821
Threshold: 1

Signal assignment statement:

237: fixed_stuff when (bst_trigger = '1') else
Count: 2827672
Threshold: 1

Signal assignment statement:

238: fixed_reg_q;
Count: 2852025
Threshold: 1

Signal assignment statement:

261: bst_ctr_add <= (bst_ctr_q + 1) mod 8;
Count: 294521
Threshold: 1

If statement:

269:    bst_ctr_d <=        "000" when (enable_prev = '0') else 
270:                  bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and 
271:                                    fixed_stuff = '0') else 
272:                    bst_ctr_q;

Count: 23090442
Threshold: 1

Signal assignment statement:

269: bst_ctr_d <= "000" when (enable_prev = '0') else
Count: 16516987
Threshold: 1

Signal assignment statement:

270: bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and
Count: 810115
Threshold: 1

Signal assignment statement:

272: bst_ctr_q;
Count: 5763340
Threshold: 1

If statement:

279:        if (res_n = '0') then 
280:            bst_ctr_q <= (others => '0'); 
...
284:            end if; 
285:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

280: bst_ctr_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

282:            if (stuff_enable = '1') then 
283:                bst_ctr_q <= bst_ctr_d; 
284:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

283: bst_ctr_q <= bst_ctr_d;
Count: 155166029
Threshold: 1

If statement:

294:    same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or 
295:                                   (stuff_lvl_reached = '1') or 
296:                                   (data_in /= data_out_i and fixed_stuff = '0') 
297:                              else 
298:                          '0';

Count: 3230678
Threshold: 1

Signal assignment statement:

294: same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or
Count: 1843612
Threshold: 1

Signal assignment statement:

298: '0';
Count: 1387066
Threshold: 1

If statement:

305:    same_bits_rst <= '1' when (enable_prev = '0') or 
306:                              (bst_trigger = '1' and same_bits_rst_trig = '1') 
307:                         else 
308:                     '0';

Count: 23915440
Threshold: 1

Signal assignment statement:

305: same_bits_rst <= '1' when (enable_prev = '0') or
Count: 18112912
Threshold: 1

Signal assignment statement:

308: '0';
Count: 5802528
Threshold: 1

Signal assignment statement:

313: same_bits_add <= (same_bits_q + 1) mod 8;
Count: 2285345
Threshold: 1

If statement:

321:    tx_no_sof_val <= "10" when (data_in = DOMINANT) else 
322:                     "01";

Count: 1288890
Threshold: 1

Signal assignment statement:

321: tx_no_sof_val <= "10" when (data_in = DOMINANT) else
Count: 642846
Threshold: 1

Signal assignment statement:

322: "01";
Count: 646044
Threshold: 1

If statement:

331:    same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else 
332:                                   "001" when (same_bits_rst = '1') else 
333:                           same_bits_add when (bst_trigger = '1') else 
334:                             same_bits_q;

Count: 29870115
Threshold: 1

Signal assignment statement:

331: same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else
Count: 1642
Threshold: 1

Signal assignment statement:

332: "001" when (same_bits_rst = '1') else
Count: 19557106
Threshold: 1

Signal assignment statement:

333: same_bits_add when (bst_trigger = '1') else
Count: 7261975
Threshold: 1

Signal assignment statement:

334: same_bits_q;
Count: 3049392
Threshold: 1

If statement:

346:    stuff_lvl_reached <= '1' when (same_bits_q = "101") 
347:                             else 
348:                         '0';

Count: 2285345
Threshold: 1

Signal assignment statement:

346: stuff_lvl_reached <= '1' when (same_bits_q = "101")
Count: 310477
Threshold: 1

Signal assignment statement:

348: '0';
Count: 1974868
Threshold: 1

If statement:

355:        if (res_n = '0') then 
356:            same_bits_q <= "001"; 
...
362:            end if; 
363:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

356: same_bits_q <= "001";
Count: 2418499
Threshold: 1

If statement:

358:            if (stuff_enable = '1') then 
359:                same_bits_q <= same_bits_d; 
360:            else 
361:                same_bits_q <= "001"; 
362:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

359: same_bits_q <= same_bits_d;
Count: 155166029
Threshold: 1

Signal assignment statement:

361: same_bits_q <= "001";
Count: 371208271
Threshold: 1

If statement:

371:    insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') 
372:                            else 
373:                        '0';

Count: 650196
Threshold: 1

Signal assignment statement:

371: insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')
Count: 323943
Threshold: 1

Signal assignment statement:

373: '0';
Count: 326253
Threshold: 1

If statement:

382:    data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else 
383:                              data_in  when (bst_trigger = '1') else 
384:                           data_out_i;

Count: 25295300
Threshold: 1

Signal assignment statement:

382: data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else
Count: 1327093
Threshold: 1

Signal assignment statement:

383: data_in when (bst_trigger = '1') else
Count: 12587380
Threshold: 1

Signal assignment statement:

384: data_out_i;
Count: 11380827
Threshold: 1

If statement:

386:    data_out_d <= data_out_d_ena when (stuff_enable = '1') else 
387:                         data_in when (bst_trigger = '1') else 
388:                      data_out_i;

Count: 28007578
Threshold: 1

Signal assignment statement:

386: data_out_d <= data_out_d_ena when (stuff_enable = '1') else
Count: 10981957
Threshold: 1

Signal assignment statement:

387: data_in when (bst_trigger = '1') else
Count: 8511261
Threshold: 1

Signal assignment statement:

388: data_out_i;
Count: 8514360
Threshold: 1

If statement:

390:    data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else 
391:                     '0';

Count: 22142437
Threshold: 1

Signal assignment statement:

390: data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else
Count: 13876447
Threshold: 1

Signal assignment statement:

391: '0';
Count: 8265990
Threshold: 1

If statement:

421:    data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else 
422:                   '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else 
423:                   '0' when (bst_trigger = '1') else 
424:                   data_halt_q;

Count: 23468483
Threshold: 1

Signal assignment statement:

421: data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else
Count: 16561594
Threshold: 1

Signal assignment statement:

422: '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else
Count: 944735
Threshold: 1

Signal assignment statement:

423: '0' when (bst_trigger = '1') else
Count: 3119217
Threshold: 1

Signal assignment statement:

424: data_halt_q;
Count: 2842937
Threshold: 1

If statement:

432:    data_halt <= data_halt_q when (data_halt_q = data_halt_d) else 
433:                 data_halt_d;

Count: 2528528
Threshold: 1

Signal assignment statement:

432: data_halt <= data_halt_q when (data_halt_q = data_halt_d) else
Count: 1265064
Threshold: 1

Signal assignment statement:

433: data_halt_d;
Count: 1263464
Threshold: 1

Signal assignment statement:

454: bst_ctr <= std_logic_vector(bst_ctr_q);
Count: 294521
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

227: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0')

	Evaluated to	Count	Threshold
Bin	True	13466	1
Bin	False	34662	1

"if" / "when" / "else" condition:

236: fixed_reg_d <= '0' when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	True	16506821	1
Bin	False	5679697	1

"if" / "when" / "else" condition:

237: fixed_stuff when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	2827672	1
Bin	False	2852025	1

"if" / "when" / "else" condition:

269: bst_ctr_d <= "000" when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	True	16516987	1
Bin	False	6573455	1

"if" / "when" / "else" condition:

270:                  bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and 
271:                                    fixed_stuff = '0') else

	Evaluated to	Count	Threshold
Bin	True	810115	1
Bin	False	5763340	1

"if" / "when" / "else" condition:

279: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

281: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

282: if (stuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	155166029	1
Bin	False	371208271	1

"if" / "when" / "else" condition:

294:    same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or 
295:                                   (stuff_lvl_reached = '1') or 
296:                                   (data_in /= data_out_i and fixed_stuff = '0')

	Evaluated to	Count	Threshold
Bin	True	1843612	1
Bin	False	1387066	1

"if" / "when" / "else" condition:

305:    same_bits_rst <= '1' when (enable_prev = '0') or 
306:                              (bst_trigger = '1' and same_bits_rst_trig = '1')

	Evaluated to	Count	Threshold
Bin	True	18112912	1
Bin	False	5802528	1

"if" / "when" / "else" condition:

321: tx_no_sof_val <= "10" when (data_in = DOMINANT) else

	Evaluated to	Count	Threshold
Bin	True	642846	1
Bin	False	646044	1

"if" / "when" / "else" condition:

331: same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else

	Evaluated to	Count	Threshold
Bin	True	1642	1
Bin	False	29868473	1

"if" / "when" / "else" condition:

332: "001" when (same_bits_rst = '1') else

	Evaluated to	Count	Threshold
Bin	True	19557106	1
Bin	False	10311367	1

"if" / "when" / "else" condition:

333: same_bits_add when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	7261975	1
Bin	False	3049392	1

"if" / "when" / "else" condition:

346: stuff_lvl_reached <= '1' when (same_bits_q = "101")

	Evaluated to	Count	Threshold
Bin	True	310477	1
Bin	False	1974868	1

"if" / "when" / "else" condition:

355: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

357: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

358: if (stuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	155166029	1
Bin	False	371208271	1

"if" / "when" / "else" condition:

371: insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')

	Evaluated to	Count	Threshold
Bin	True	323943	1
Bin	False	326253	1

"if" / "when" / "else" condition:

382: data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	True	1327093	1
Bin	False	23968207	1

"if" / "when" / "else" condition:

383: data_in when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	12587380	1
Bin	False	11380827	1

"if" / "when" / "else" condition:

386: data_out_d <= data_out_d_ena when (stuff_enable = '1') else

	Evaluated to	Count	Threshold
Bin	True	10981957	1
Bin	False	17025621	1

"if" / "when" / "else" condition:

387: data_in when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	8511261	1
Bin	False	8514360	1

"if" / "when" / "else" condition:

390: data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	13876447	1
Bin	False	8265990	1

"if" / "when" / "else" condition:

421: data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else

	Evaluated to	Count	Threshold
Bin	True	16561594	1
Bin	False	6906889	1

"if" / "when" / "else" condition:

422: '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	True	944735	1
Bin	False	5962154	1

"if" / "when" / "else" condition:

423: '0' when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	3119217	1
Bin	False	2842937	1

"if" / "when" / "else" condition:

432: data_halt <= data_halt_q when (data_halt_q = data_halt_d) else

	Evaluated to	Count	Threshold
Bin	True	1265064	1
Bin	False	1263464	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

DATA_IN

	From	To	Count	Threshold
Bin	0	1	644444	1
Bin	1	0	642846	1

Port:

DATA_OUT

	From	To	Count	Threshold
Bin	0	1	635351	1
Bin	1	0	633753	1

Port:

BST_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

STUFF_ENABLE

	From	To	Count	Threshold
Bin	0	1	24816	1
Bin	1	0	26416	1

Port:

FIXED_STUFF

	From	To	Count	Threshold
Bin	0	1	13466	1
Bin	1	0	15066	1

Port:

TX_FRAME_NO_SOF

	From	To	Count	Threshold
Bin	0	1	354	1
Bin	1	0	1954	1

Port:

BST_CTR(2)

	From	To	Count	Threshold
Bin	0	1	33334	1
Bin	1	0	34934	1

Port:

BST_CTR(1)

	From	To	Count	Threshold
Bin	0	1	70225	1
Bin	1	0	71823	1

Port:

BST_CTR(0)

	From	To	Count	Threshold
Bin	0	1	140700	1
Bin	1	0	142298	1

Port:

DATA_HALT

	From	To	Count	Threshold
Bin	0	1	944735	1
Bin	1	0	946335	1

Signal:

DATA_OUT_I

	From	To	Count	Threshold
Bin	0	1	635351	1
Bin	1	0	633753	1

Signal:

SAME_BITS_Q(2)

	From	To	Count	Threshold
Bin	0	1	353867	1
Bin	1	0	355467	1

Signal:

SAME_BITS_Q(1)

	From	To	Count	Threshold
Bin	0	1	592690	1
Bin	1	0	594290	1

Signal:

SAME_BITS_Q(0)

	From	To	Count	Threshold
Bin	0	1	948157	1
Bin	1	0	946557	1

Signal:

SAME_BITS_ADD(2)

	From	To	Count	Threshold
Bin	0	1	432421	1
Bin	1	0	434021	1

Signal:

SAME_BITS_ADD(1)

	From	To	Count	Threshold
Bin	0	1	434021	1
Bin	1	0	432421	1

Signal:

SAME_BITS_ADD(0)

	From	To	Count	Threshold
Bin	0	1	946557	1
Bin	1	0	948157	1

Signal:

SAME_BITS_D(2)

	From	To	Count	Threshold
Bin	0	1	1169779	1
Bin	1	0	1171379	1

Signal:

SAME_BITS_D(1)

	From	To	Count	Threshold
Bin	0	1	3254756	1
Bin	1	0	3256356	1

Signal:

SAME_BITS_D(0)

	From	To	Count	Threshold
Bin	0	1	4629736	1
Bin	1	0	4628136	1

Signal:

TX_NO_SOF_VAL(1)

	From	To	Count	Threshold
Bin	0	1	642846	1
Bin	1	0	644444	1

Signal:

TX_NO_SOF_VAL(0)

	From	To	Count	Threshold
Bin	0	1	644444	1
Bin	1	0	642846	1

Signal:

DATA_HALT_Q

	From	To	Count	Threshold
Bin	0	1	317129	1
Bin	1	0	318729	1

Signal:

DATA_HALT_D

	From	To	Count	Threshold
Bin	0	1	944735	1
Bin	1	0	946335	1

Signal:

FIXED_REG_Q

	From	To	Count	Threshold
Bin	0	1	8198	1
Bin	1	0	9798	1

Signal:

FIXED_REG_D

	From	To	Count	Threshold
Bin	0	1	8198	1
Bin	1	0	9798	1

Signal:

BST_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	33334	1
Bin	1	0	34934	1

Signal:

BST_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	70225	1
Bin	1	0	71823	1

Signal:

BST_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	140700	1
Bin	1	0	142298	1

Signal:

BST_CTR_ADD(2)

	From	To	Count	Threshold
Bin	0	1	37460	1
Bin	1	0	39059	1

Signal:

BST_CTR_ADD(1)

	From	To	Count	Threshold
Bin	0	1	76853	1
Bin	1	0	78451	1

Signal:

BST_CTR_ADD(0)

	From	To	Count	Threshold
Bin	0	1	142298	1
Bin	1	0	140700	1

Signal:

BST_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	92092	1
Bin	1	0	93692	1

Signal:

BST_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	199735	1
Bin	1	0	201335	1

Signal:

BST_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	411725	1
Bin	1	0	413325	1

Signal:

ENABLE_PREV

	From	To	Count	Threshold
Bin	0	1	24816	1
Bin	1	0	26416	1

Signal:

NON_FIX_TO_FIX_CHNG

	From	To	Count	Threshold
Bin	0	1	13466	1
Bin	1	0	15066	1

Signal:

STUFF_LVL_REACHED

	From	To	Count	Threshold
Bin	0	1	310477	1
Bin	1	0	312077	1

Signal:

SAME_BITS_RST_TRIG

	From	To	Count	Threshold
Bin	0	1	1222243	1
Bin	1	0	1223843	1

Signal:

SAME_BITS_RST

	From	To	Count	Threshold
Bin	0	1	1454810	1
Bin	1	0	1454810	1

Signal:

INSERT_STUFF_BIT

	From	To	Count	Threshold
Bin	0	1	323053	1
Bin	1	0	324653	1

Signal:

DATA_OUT_D_ENA

	From	To	Count	Threshold
Bin	0	1	2143521	1
Bin	1	0	2141923	1

Signal:

DATA_OUT_D

	From	To	Count	Threshold
Bin	0	1	1999675	1
Bin	1	0	1998077	1

Signal:

DATA_OUT_CE

	From	To	Count	Threshold
Bin	0	1	8261191	1
Bin	1	0	8262790	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

227: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0')

	Evaluated to	Count	Threshold
Bin	False	26464	1
Bin	True	21664	1

"=" expression

227: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0')

	Evaluated to	Count	Threshold
Bin	False	19596	1
Bin	True	28532	1

"and" expression

227:    non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0') 
                                         <------LHS------>     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	15066	1
Bin	True	False	8198	1
Bin	True	True	13466	1

"=" expression

236: fixed_reg_d <= '0' when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	False	5679697	1
Bin	True	16506821	1

"=" expression

237: fixed_stuff when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	2852025	1
Bin	True	2827672	1

"=" expression

269: bst_ctr_d <= "000" when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	False	6573455	1
Bin	True	16516987	1

"=" expression

270: bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and

	Evaluated to	Count	Threshold
Bin	False	2871468	1
Bin	True	3701987	1

"=" expression

270: bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and

	Evaluated to	Count	Threshold
Bin	False	5371865	1
Bin	True	1201590	1

"and" expression

270:                  bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and 
                                        <------LHS------>     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	311523	1
Bin	True	False	2811920	1
Bin	True	True	890067	1

"=" expression

271: fixed_stuff = '0') else

	Evaluated to	Count	Threshold
Bin	False	519884	1
Bin	True	6053571	1

"and" expression

270:                  bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and 
271:                                    fixed_stuff = '0') else

	LHS	RHS	Count	Threshold
Bin	False	True	5243456	1
Bin	True	False	79952	1
Bin	True	True	810115	1

"=" expression

279: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

282: if (stuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	False	371208271	1
Bin	True	155166029	1

"=" expression

294: same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or

	Evaluated to	Count	Threshold
Bin	False	3203746	1
Bin	True	26932	1

"=" expression

295: (stuff_lvl_reached = '1') or

	Evaluated to	Count	Threshold
Bin	False	2358836	1
Bin	True	871842	1

"or" expression

294:    same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or 
295:                                   (stuff_lvl_reached = '1') or

	LHS	RHS	Count	Threshold
Bin	False	False	2333684	1
Bin	False	True	870062	1
Bin	True	False	25152	1

"/=" expression

296:                                   (data_in /= data_out_i and fixed_stuff = '0')

	Evaluated to	Count	Threshold
Bin	False	1871743	1
Bin	True	1358935	1

"=" expression

296:                                   (data_in /= data_out_i and fixed_stuff = '0')

	Evaluated to	Count	Threshold
Bin	False	336549	1
Bin	True	2894129	1

"and" expression

296:                                   (data_in /= data_out_i and fixed_stuff = '0') 
                                        <--------LHS-------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	1675946	1
Bin	True	False	140752	1
Bin	True	True	1218183	1

"or" expression

294:    same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or 
295:                                   (stuff_lvl_reached = '1') or 
296:                                   (data_in /= data_out_i and fixed_stuff = '0')

	LHS	RHS	Count	Threshold
Bin	False	False	1387066	1
Bin	False	True	946618	1
Bin	True	False	625429	1

"=" expression

305: same_bits_rst <= '1' when (enable_prev = '0') or

	Evaluated to	Count	Threshold
Bin	False	7233138	1
Bin	True	16682302	1

"=" expression

306: (bst_trigger = '1' and same_bits_rst_trig = '1')

	Evaluated to	Count	Threshold
Bin	False	11420154	1
Bin	True	12495286	1

"=" expression

306: (bst_trigger = '1' and same_bits_rst_trig = '1')

	Evaluated to	Count	Threshold
Bin	False	20833317	1
Bin	True	3082123	1

"and" expression

306:                              (bst_trigger = '1' and same_bits_rst_trig = '1') 
                                   <------LHS------>     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	1442417	1
Bin	True	False	10855580	1
Bin	True	True	1639706	1

"or" expression

305:    same_bits_rst <= '1' when (enable_prev = '0') or 
306:                              (bst_trigger = '1' and same_bits_rst_trig = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	5802528	1
Bin	False	True	1430610	1
Bin	True	False	16473206	1

"=" expression

321: tx_no_sof_val <= "10" when (data_in = DOMINANT) else

	Evaluated to	Count	Threshold
Bin	False	646044	1
Bin	True	642846	1

"=" expression

331: same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else

	Evaluated to	Count	Threshold
Bin	False	29868473	1
Bin	True	1642	1

"=" expression

332: "001" when (same_bits_rst = '1') else

	Evaluated to	Count	Threshold
Bin	False	10311367	1
Bin	True	19557106	1

"=" expression

333: same_bits_add when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	3049392	1
Bin	True	7261975	1

"=" expression

355: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

358: if (stuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	False	371208271	1
Bin	True	155166029	1

"=" expression

371: insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')

	Evaluated to	Count	Threshold
Bin	False	636730	1
Bin	True	13466	1

"=" expression

371: insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')

	Evaluated to	Count	Threshold
Bin	False	338829	1
Bin	True	311367	1

"or" expression

371:    insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') 
                                      <----------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	326253	1
Bin	False	True	310477	1
Bin	True	False	12576	1

"=" expression

382: data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	False	11380827	1
Bin	True	13914473	1

"=" expression

382: data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	False	23490197	1
Bin	True	1805103	1

"and" expression

382:    data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else 
                                                 <------LHS------>     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	478010	1
Bin	True	False	12587380	1
Bin	True	True	1327093	1

"=" expression

383: data_in when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	11380827	1
Bin	True	12587380	1

"=" expression

386: data_out_d <= data_out_d_ena when (stuff_enable = '1') else

	Evaluated to	Count	Threshold
Bin	False	17025621	1
Bin	True	10981957	1

"=" expression

387: data_in when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	8514360	1
Bin	True	8511261	1

"=" expression

390: data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	16502365	1
Bin	True	5640072	1

"=" expression

390: data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	11098434	1
Bin	True	11044003	1

"or" expression

390:    data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else 
                                 <------LHS------->    <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	8265990	1
Bin	False	True	8236375	1
Bin	True	False	2832444	1

"=" expression

421: data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else

	Evaluated to	Count	Threshold
Bin	False	6936278	1
Bin	True	16532205	1

"=" expression

421: data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else

	Evaluated to	Count	Threshold
Bin	False	6931720	1
Bin	True	16536763	1

"or" expression

421:    data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else 
                                 <------LHS------>    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	6906889	1
Bin	False	True	29389	1
Bin	True	False	24831	1

"=" expression

422: '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	False	2842937	1
Bin	True	4063952	1

"=" expression

422: '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	False	5644369	1
Bin	True	1262520	1

"and" expression

422:                   '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else 
                                 <------LHS------>     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	317785	1
Bin	True	False	3119217	1
Bin	True	True	944735	1

"=" expression

423: '0' when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	2842937	1
Bin	True	3119217	1

"=" expression

432: data_halt <= data_halt_q when (data_halt_q = data_halt_d) else

	Evaluated to	Count	Threshold
Bin	False	1263464	1
Bin	True	1265064	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_STUFFING_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/bit_stuffing.vhd

Sub-instances:

Current Instance:

Details:

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Uncovered branches:

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"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

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