NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DFF_ENA_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
DFF_FIXED_STUFF_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)
DFF_DATA_OUT_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)
DFF_HALT_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

DFF_ENA_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

DFF_FIXED_STUFF_REG

100.0 % (4/4)

100.0 % (6/6)

100.0 % (10/10)

100.0 % (4/4)

N.A.

100.0 % (24/24)

DFF_DATA_OUT_REG

100.0 % (4/4)

100.0 % (6/6)

100.0 % (10/10)

100.0 % (4/4)

N.A.

100.0 % (24/24)

DFF_HALT_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_STUFFING_INST	100.0 % (63/63)	100.0 % (56/56)	100.0 % (92/92)	100.0 % (115/115)	N.A.	N.A.	100.0 % (326/326)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_STUFFING_INST

100.0 % (63/63)

100.0 % (56/56)

100.0 % (92/92)

100.0 % (115/115)

N.A.

100.0 % (326/326)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 227 to 229:

227:    non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0') 
228:                               else 
229:                           '0';

Count: 47225
Threshold: 1

Signal assignment statement on line 227:

227: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0')
Count: 13512
Threshold: 1

Signal assignment statement on line 229:

229: '0';
Count: 33713
Threshold: 1

If statement on lines 236 to 238:

236:    fixed_reg_d <= '0'         when (enable_prev = '0') else 
237:                   fixed_stuff when (bst_trigger = '1') else 
238:                   fixed_reg_q;

Count: 22880682
Threshold: 1

Signal assignment statement on line 236:

236: fixed_reg_d <= '0' when (enable_prev = '0') else
Count: 17206125
Threshold: 1

Signal assignment statement on line 237:

237: fixed_stuff when (bst_trigger = '1') else
Count: 2825007
Threshold: 1

Signal assignment statement on line 238:

238: fixed_reg_q;
Count: 2849550
Threshold: 1

Signal assignment statement on line 261:

261: bst_ctr_add <= (bst_ctr_q + 1) mod 8;
Count: 296187
Threshold: 1

If statement on lines 269 to 272:

269:    bst_ctr_d <=        "000" when (enable_prev = '0') else 
270:                  bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and 
271:                                    fixed_stuff = '0') else 
272:                    bst_ctr_q;

Count: 23784699
Threshold: 1

Signal assignment statement on line 269:

269: bst_ctr_d <= "000" when (enable_prev = '0') else
Count: 17216433
Threshold: 1

Signal assignment statement on line 270:

270: bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and
Count: 813921
Threshold: 1

Signal assignment statement on line 272:

272: bst_ctr_q;
Count: 5754345
Threshold: 1

If statement on lines 279 to 285:

279:        if (res_n = '0') then 
280:            bst_ctr_q <= (others => '0'); 
...
284:            end if; 
285:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 280:

280: bst_ctr_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 282 to 284:

282:            if (stuff_enable = '1') then 
283:                bst_ctr_q <= bst_ctr_d; 
284:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 283:

283: bst_ctr_q <= bst_ctr_d;
Count: 154878884
Threshold: 1

If statement on lines 294 to 298:

294:    same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or 
295:                                   (stuff_lvl_reached = '1') or 
296:                                   (data_in /= data_out_i and fixed_stuff = '0') 
297:                              else 
298:                          '0';

Count: 3226742
Threshold: 1

Signal assignment statement on line 294:

294: same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or
Count: 1844740
Threshold: 1

Signal assignment statement on line 298:

298: '0';
Count: 1382002
Threshold: 1

If statement on lines 305 to 308:

305:    same_bits_rst <= '1' when (enable_prev = '0') or 
306:                              (bst_trigger = '1' and same_bits_rst_trig = '1') 
307:                         else 
308:                     '0';

Count: 24612859
Threshold: 1

Signal assignment statement on line 305:

305: same_bits_rst <= '1' when (enable_prev = '0') or
Count: 18813303
Threshold: 1

Signal assignment statement on line 308:

308: '0';
Count: 5799556
Threshold: 1

Signal assignment statement on line 313:

313: same_bits_add <= (same_bits_q + 1) mod 8;
Count: 2280466
Threshold: 1

If statement on lines 321 to 322:

321:    tx_no_sof_val <= "10" when (data_in = DOMINANT) else 
322:                     "01";

Count: 1290280
Threshold: 1

Signal assignment statement on line 321:

321: tx_no_sof_val <= "10" when (data_in = DOMINANT) else
Count: 643541
Threshold: 1

Signal assignment statement on line 322:

322: "01";
Count: 646739
Threshold: 1

If statement on lines 331 to 334:

331:    same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else 
332:                                   "001" when (same_bits_rst = '1') else 
333:                           same_bits_add when (bst_trigger = '1') else 
334:                             same_bits_q;

Count: 30556385
Threshold: 1

Signal assignment statement on line 331:

331: same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else
Count: 1634
Threshold: 1

Signal assignment statement on line 332:

332: "001" when (same_bits_rst = '1') else
Count: 20250934
Threshold: 1

Signal assignment statement on line 333:

333: same_bits_add when (bst_trigger = '1') else
Count: 7255184
Threshold: 1

Signal assignment statement on line 334:

334: same_bits_q;
Count: 3048633
Threshold: 1

If statement on lines 346 to 348:

346:    stuff_lvl_reached <= '1' when (same_bits_q = "101") 
347:                             else 
348:                         '0';

Count: 2280466
Threshold: 1

Signal assignment statement on line 346:

346: stuff_lvl_reached <= '1' when (same_bits_q = "101")
Count: 309196
Threshold: 1

Signal assignment statement on line 348:

348: '0';
Count: 1971270
Threshold: 1

If statement on lines 355 to 363:

355:        if (res_n = '0') then 
356:            same_bits_q <= "001"; 
...
362:            end if; 
363:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 356:

356: same_bits_q <= "001";
Count: 2424883
Threshold: 1

If statement on lines 358 to 362:

358:            if (stuff_enable = '1') then 
359:                same_bits_q <= same_bits_d; 
360:            else 
361:                same_bits_q <= "001"; 
362:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 359:

359: same_bits_q <= same_bits_d;
Count: 154878884
Threshold: 1

Signal assignment statement on line 361:

361: same_bits_q <= "001";
Count: 388912794
Threshold: 1

If statement on lines 371 to 373:

371:    insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') 
372:                            else 
373:                        '0';

Count: 647872
Threshold: 1

Signal assignment statement on line 371:

371: insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')
Count: 322708
Threshold: 1

Signal assignment statement on line 373:

373: '0';
Count: 325164
Threshold: 1

If statement on lines 382 to 384:

382:    data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else 
383:                              data_in  when (bst_trigger = '1') else 
384:                           data_out_i;

Count: 25985580
Threshold: 1

Signal assignment statement on line 382:

382: data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else
Count: 1335611
Threshold: 1

Signal assignment statement on line 383:

383: data_in when (bst_trigger = '1') else
Count: 12920243
Threshold: 1

Signal assignment statement on line 384:

384: data_out_i;
Count: 11729726
Threshold: 1

If statement on lines 386 to 388:

386:    data_out_d <= data_out_d_ena when (stuff_enable = '1') else 
387:                         data_in when (bst_trigger = '1') else 
388:                      data_out_i;

Count: 28721785
Threshold: 1

Signal assignment statement on line 386:

386: data_out_d <= data_out_d_ena when (stuff_enable = '1') else
Count: 10969234
Threshold: 1

Signal assignment statement on line 387:

387: data_in when (bst_trigger = '1') else
Count: 8874612
Threshold: 1

Signal assignment statement on line 388:

388: data_out_i;
Count: 8877939
Threshold: 1

If statement on lines 390 to 391:

390:    data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else 
391:                     '0';

Count: 22837506
Threshold: 1

Signal assignment statement on line 390:

390: data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else
Count: 14222042
Threshold: 1

Signal assignment statement on line 391:

391: '0';
Count: 8615464
Threshold: 1

If statement on lines 421 to 424:

421:    data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else 
422:                   '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else 
423:                   '0' when (bst_trigger = '1') else 
424:                   data_halt_q;

Count: 24158554
Threshold: 1

Signal assignment statement on line 421:

421: data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else
Count: 17262230
Threshold: 1

Signal assignment statement on line 422:

422: '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else
Count: 939896
Threshold: 1

Signal assignment statement on line 423:

423: '0' when (bst_trigger = '1') else
Count: 3115323
Threshold: 1

Signal assignment statement on line 424:

424: data_halt_q;
Count: 2841105
Threshold: 1

If statement on lines 432 to 433:

432:    data_halt <= data_halt_q when (data_halt_q = data_halt_d) else 
433:                 data_halt_d;

Count: 2515295
Threshold: 1

Signal assignment statement on line 432:

432: data_halt <= data_halt_q when (data_halt_q = data_halt_d) else
Count: 1258448
Threshold: 1

Signal assignment statement on line 433:

433: data_halt_d;
Count: 1256847
Threshold: 1

Signal assignment statement on line 454:

454: bst_ctr <= std_logic_vector(bst_ctr_q);
Count: 296187
Threshold: 1

Signal assignment statement on line 455:

455: data_out <= data_out_i;
Count: 1267628
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 227:

227: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0')

	Evaluated to	Count	Threshold
Bin	True	13512	1
Bin	False	33713	1

"if" / "when" / "else" condition on line 236:

236: fixed_reg_d <= '0' when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	True	17206125	1
Bin	False	5674557	1

"if" / "when" / "else" condition on line 237:

237: fixed_stuff when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	2825007	1
Bin	False	2849550	1

"if" / "when" / "else" condition on line 269:

269: bst_ctr_d <= "000" when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	True	17216433	1
Bin	False	6568266	1

"if" / "when" / "else" condition on lines 270 to 271:

270:                  bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and 
271:                                    fixed_stuff = '0') else

	Evaluated to	Count	Threshold
Bin	True	813921	1
Bin	False	5754345	1

"if" / "when" / "else" condition on line 279:

279: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 281:

281: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 282:

282: if (stuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	154878884	1
Bin	False	388912794	1

"if" / "when" / "else" condition on lines 294 to 296:

294:    same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or 
295:                                   (stuff_lvl_reached = '1') or 
296:                                   (data_in /= data_out_i and fixed_stuff = '0')

	Evaluated to	Count	Threshold
Bin	True	1844740	1
Bin	False	1382002	1

"if" / "when" / "else" condition on lines 305 to 306:

305:    same_bits_rst <= '1' when (enable_prev = '0') or 
306:                              (bst_trigger = '1' and same_bits_rst_trig = '1')

	Evaluated to	Count	Threshold
Bin	True	18813303	1
Bin	False	5799556	1

"if" / "when" / "else" condition on line 321:

321: tx_no_sof_val <= "10" when (data_in = DOMINANT) else

	Evaluated to	Count	Threshold
Bin	True	643541	1
Bin	False	646739	1

"if" / "when" / "else" condition on line 331:

331: same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else

	Evaluated to	Count	Threshold
Bin	True	1634	1
Bin	False	30554751	1

"if" / "when" / "else" condition on line 332:

332: "001" when (same_bits_rst = '1') else

	Evaluated to	Count	Threshold
Bin	True	20250934	1
Bin	False	10303817	1

"if" / "when" / "else" condition on line 333:

333: same_bits_add when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	7255184	1
Bin	False	3048633	1

"if" / "when" / "else" condition on line 346:

346: stuff_lvl_reached <= '1' when (same_bits_q = "101")

	Evaluated to	Count	Threshold
Bin	True	309196	1
Bin	False	1971270	1

"if" / "when" / "else" condition on line 355:

355: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 357:

357: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 358:

358: if (stuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	154878884	1
Bin	False	388912794	1

"if" / "when" / "else" condition on line 371:

371: insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')

	Evaluated to	Count	Threshold
Bin	True	322708	1
Bin	False	325164	1

"if" / "when" / "else" condition on line 382:

382: data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	True	1335611	1
Bin	False	24649969	1

"if" / "when" / "else" condition on line 383:

383: data_in when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	12920243	1
Bin	False	11729726	1

"if" / "when" / "else" condition on line 386:

386: data_out_d <= data_out_d_ena when (stuff_enable = '1') else

	Evaluated to	Count	Threshold
Bin	True	10969234	1
Bin	False	17752551	1

"if" / "when" / "else" condition on line 387:

387: data_in when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	8874612	1
Bin	False	8877939	1

"if" / "when" / "else" condition on line 390:

390: data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	14222042	1
Bin	False	8615464	1

"if" / "when" / "else" condition on line 421:

421: data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else

	Evaluated to	Count	Threshold
Bin	True	17262230	1
Bin	False	6896324	1

"if" / "when" / "else" condition on line 422:

422: '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	True	939896	1
Bin	False	5956428	1

"if" / "when" / "else" condition on line 423:

423: '0' when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	3115323	1
Bin	False	2841105	1

"if" / "when" / "else" condition on line 432:

432: data_halt <= data_halt_q when (data_halt_q = data_halt_d) else

	Evaluated to	Count	Threshold
Bin	True	1258448	1
Bin	False	1256847	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BST_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STUFF_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

FIXED_STUFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_FRAME_NO_SOF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

DATA_OUT

	From	To	Count	Threshold
Bin	0	1	633812	1
Bin	1	0	632215	1

Port:

BST_CTR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	33452	1
Bin	(2)	1	0	35053	1
Bin	(1)	0	1	70940	1
Bin	(1)	1	0	72538	1
Bin	(0)	0	1	141315	1
Bin	(0)	1	0	142914	1

Port:

DATA_HALT

	From	To	Count	Threshold
Bin	0	1	939896	1
Bin	1	0	941497	1

Signal:

DATA_OUT_I

	From	To	Count	Threshold
Bin	0	1	633812	1
Bin	1	0	632215	1

Signal:

SAME_BITS_Q

	Element	From	To	Count	Threshold
Bin	(2)	0	1	353228	1
Bin	(2)	1	0	354829	1
Bin	(1)	0	1	591230	1
Bin	(1)	1	0	592831	1
Bin	(0)	0	1	946059	1
Bin	(0)	1	0	944458	1

Signal:

SAME_BITS_ADD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	432380	1
Bin	(2)	1	0	433981	1
Bin	(1)	0	1	433981	1
Bin	(1)	1	0	432380	1
Bin	(0)	0	1	944458	1
Bin	(0)	1	0	946059	1

Signal:

SAME_BITS_D

	Element	From	To	Count	Threshold
Bin	(2)	0	1	1168498	1
Bin	(2)	1	0	1170099	1
Bin	(1)	0	1	3255691	1
Bin	(1)	1	0	3257292	1
Bin	(0)	0	1	4628616	1
Bin	(0)	1	0	4627015	1

Signal:

TX_NO_SOF_VAL

	Element	From	To	Count	Threshold
Bin	(1)	0	1	643541	1
Bin	(1)	1	0	645138	1
Bin	(0)	0	1	645138	1
Bin	(0)	1	0	643541	1

Signal:

DATA_HALT_Q

	From	To	Count	Threshold
Bin	0	1	315350	1
Bin	1	0	316951	1

Signal:

DATA_HALT_D

	From	To	Count	Threshold
Bin	0	1	939896	1
Bin	1	0	941497	1

Signal:

FIXED_REG_Q

	From	To	Count	Threshold
Bin	0	1	7699	1
Bin	1	0	9300	1

Signal:

FIXED_REG_D

	From	To	Count	Threshold
Bin	0	1	7699	1
Bin	1	0	9300	1

Signal:

BST_CTR_Q

	Element	From	To	Count	Threshold
Bin	(2)	0	1	33452	1
Bin	(2)	1	0	35053	1
Bin	(1)	0	1	70940	1
Bin	(1)	1	0	72538	1
Bin	(0)	0	1	141315	1
Bin	(0)	1	0	142914	1

Signal:

BST_CTR_ADD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	37660	1
Bin	(2)	1	0	39260	1
Bin	(1)	0	1	77363	1
Bin	(1)	1	0	78961	1
Bin	(0)	0	1	142914	1
Bin	(0)	1	0	141315	1

Signal:

BST_CTR_D

	Element	From	To	Count	Threshold
Bin	(2)	0	1	92209	1
Bin	(2)	1	0	93810	1
Bin	(1)	0	1	201069	1
Bin	(1)	1	0	202670	1
Bin	(0)	0	1	413617	1
Bin	(0)	1	0	415218	1

Signal:

ENABLE_PREV

	From	To	Count	Threshold
Bin	0	1	25275	1
Bin	1	0	26876	1

Signal:

NON_FIX_TO_FIX_CHNG

	From	To	Count	Threshold
Bin	0	1	13512	1
Bin	1	0	15113	1

Signal:

STUFF_LVL_REACHED

	From	To	Count	Threshold
Bin	0	1	309196	1
Bin	1	0	310797	1

Signal:

SAME_BITS_RST_TRIG

	From	To	Count	Threshold
Bin	0	1	1225733	1
Bin	1	0	1227334	1

Signal:

SAME_BITS_RST

	From	To	Count	Threshold
Bin	0	1	1455473	1
Bin	1	0	1455473	1

Signal:

INSERT_STUFF_BIT

	From	To	Count	Threshold
Bin	0	1	321962	1
Bin	1	0	323563	1

Signal:

DATA_OUT_D_ENA

	From	To	Count	Threshold
Bin	0	1	2154163	1
Bin	1	0	2152566	1

Signal:

DATA_OUT_D

	From	To	Count	Threshold
Bin	0	1	1996239	1
Bin	1	0	1994642	1

Signal:

DATA_OUT_CE

	From	To	Count	Threshold
Bin	0	1	8610662	1
Bin	1	0	8612262	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 227:

 fixed_stuff = '1' and fixed_reg_q = '0' 
 <------LHS------>     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	15113	1
Bin	True	False	7699	1
Bin	True	True	13512	1

"=" expression on line 227:

fixed_stuff = '1'

	Evaluated to	Count	Threshold
Bin	False	26014	1
Bin	True	21211	1

"=" expression on line 227:

fixed_reg_q = '0'

	Evaluated to	Count	Threshold
Bin	False	18600	1
Bin	True	28625	1

"=" expression on line 236:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	5674557	1
Bin	True	17206125	1

"=" expression on line 237:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	2849550	1
Bin	True	2825007	1

"=" expression on line 269:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	6568266	1
Bin	True	17216433	1

"and" expression on lines 270 to 271:

 bst_trigger = '1' and stuff_lvl_reached = '1' and fixed_stuff = '0' 
 <--------------------LHS-------------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	5267732	1
Bin	True	False	74702	1
Bin	True	True	813921	1

"and" expression on line 270:

 bst_trigger = '1' and stuff_lvl_reached = '1' 
 <------LHS------>     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	310096	1
Bin	True	False	2810248	1
Bin	True	True	888623	1

"=" expression on line 270:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	2869395	1
Bin	True	3698871	1

"=" expression on line 270:

stuff_lvl_reached = '1'

	Evaluated to	Count	Threshold
Bin	False	5369547	1
Bin	True	1198719	1

"=" expression on line 271:

fixed_stuff = '0'

	Evaluated to	Count	Threshold
Bin	False	486613	1
Bin	True	6081653	1

"=" expression on line 279:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 282:

stuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	388912794	1
Bin	True	154878884	1

"or" expression on lines 294 to 296:

 (non_fix_to_fix_chng = '1') or (stuff_lvl_reached = '1') or (data_in /= data_out_i and fixed_stuff = '0') 
 <-------------------------LHS-------------------------->     <-------------------RHS------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	1382002	1
Bin	False	True	951059	1
Bin	True	False	620948	1

"or" expression on lines 294 to 295:

 (non_fix_to_fix_chng = '1') or (stuff_lvl_reached = '1') 
  <----------LHS---------->      <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	2333061	1
Bin	False	True	866657	1
Bin	True	False	25532	1

"=" expression on line 294:

non_fix_to_fix_chng = '1'

	Evaluated to	Count	Threshold
Bin	False	3199718	1
Bin	True	27024	1

"=" expression on line 295:

stuff_lvl_reached = '1'

	Evaluated to	Count	Threshold
Bin	False	2358593	1
Bin	True	868149	1

"and" expression on line 296:

 data_in /= data_out_i and fixed_stuff = '0' 
 <--------LHS-------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	1685004	1
Bin	True	False	133002	1
Bin	True	True	1223792	1

"/=" expression on line 296:

data_in /= data_out_i

	Evaluated to	Count	Threshold
Bin	False	1869948	1
Bin	True	1356794	1

"=" expression on line 296:

fixed_stuff = '0'

	Evaluated to	Count	Threshold
Bin	False	317946	1
Bin	True	2908796	1

"or" expression on lines 305 to 306:

 (enable_prev = '0') or (bst_trigger = '1' and same_bits_rst_trig = '1') 
  <------LHS------>      <--------------------RHS--------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	5799556	1
Bin	False	True	1430914	1
Bin	True	False	17159064	1

"=" expression on line 305:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	7230470	1
Bin	True	17382389	1

"and" expression on line 306:

 bst_trigger = '1' and same_bits_rst_trig = '1' 
 <------LHS------>     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	1460486	1
Bin	True	False	11188887	1
Bin	True	True	1654239	1

"=" expression on line 306:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11769733	1
Bin	True	12843126	1

"=" expression on line 306:

same_bits_rst_trig = '1'

	Evaluated to	Count	Threshold
Bin	False	21498134	1
Bin	True	3114725	1

"=" expression on line 321:

data_in = DOMINANT

	Evaluated to	Count	Threshold
Bin	False	646739	1
Bin	True	643541	1

"=" expression on line 331:

tx_frame_no_sof = '1'

	Evaluated to	Count	Threshold
Bin	False	30554751	1
Bin	True	1634	1

"=" expression on line 332:

same_bits_rst = '1'

	Evaluated to	Count	Threshold
Bin	False	10303817	1
Bin	True	20250934	1

"=" expression on line 333:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	3048633	1
Bin	True	7255184	1

"=" expression on line 355:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 358:

stuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	388912794	1
Bin	True	154878884	1

"or" expression on line 371:

 non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1' 
 <----------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	325164	1
Bin	False	True	309196	1
Bin	True	False	12766	1

"=" expression on line 371:

non_fix_to_fix_chng = '1'

	Evaluated to	Count	Threshold
Bin	False	634360	1
Bin	True	13512	1

"=" expression on line 371:

stuff_lvl_reached = '1'

	Evaluated to	Count	Threshold
Bin	False	337930	1
Bin	True	309942	1

"and" expression on line 382:

 bst_trigger = '1' and insert_stuff_bit = '1' 
 <------LHS------>     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	491015	1
Bin	True	False	12920243	1
Bin	True	True	1335611	1

"=" expression on line 382:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11729726	1
Bin	True	14255854	1

"=" expression on line 382:

insert_stuff_bit = '1'

	Evaluated to	Count	Threshold
Bin	False	24158954	1
Bin	True	1826626	1

"=" expression on line 383:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11729726	1
Bin	True	12920243	1

"=" expression on line 386:

stuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	17752551	1
Bin	True	10969234	1

"=" expression on line 387:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	8877939	1
Bin	True	8874612	1

"or" expression on line 390:

 stuff_enable = '1' or bst_trigger = '1' 
 <------LHS------->    <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	8615464	1
Bin	False	True	8585387	1
Bin	True	False	2830965	1

"=" expression on line 390:

stuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	17200851	1
Bin	True	5636655	1

"=" expression on line 390:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11446429	1
Bin	True	11391077	1

"or" expression on line 421:

 enable_prev = '0' or stuff_enable = '0' 
 <------LHS------>    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	6896324	1
Bin	False	True	30103	1
Bin	True	False	25290	1

"=" expression on line 421:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	6926427	1
Bin	True	17232127	1

"=" expression on line 421:

stuff_enable = '0'

	Evaluated to	Count	Threshold
Bin	False	6921614	1
Bin	True	17236940	1

"and" expression on line 422:

 bst_trigger = '1' and insert_stuff_bit = '1' 
 <------LHS------>     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	316149	1
Bin	True	False	3115323	1
Bin	True	True	939896	1

"=" expression on line 422:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	2841105	1
Bin	True	4055219	1

"=" expression on line 422:

insert_stuff_bit = '1'

	Evaluated to	Count	Threshold
Bin	False	5640279	1
Bin	True	1256045	1

"=" expression on line 423:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	2841105	1
Bin	True	3115323	1

"=" expression on line 432:

data_halt_q = data_halt_d

	Evaluated to	Count	Threshold
Bin	False	1256847	1
Bin	True	1258448	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_STUFFING_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 227 to 229:

Signal assignment statement on line 227:

Signal assignment statement on line 229:

If statement on lines 236 to 238:

Signal assignment statement on line 236:

Signal assignment statement on line 237:

Signal assignment statement on line 238:

Signal assignment statement on line 261:

If statement on lines 269 to 272:

Signal assignment statement on line 269:

Signal assignment statement on line 270:

Signal assignment statement on line 272:

If statement on lines 279 to 285:

Signal assignment statement on line 280:

If statement on lines 282 to 284:

Signal assignment statement on line 283:

If statement on lines 294 to 298:

Signal assignment statement on line 294:

Signal assignment statement on line 298:

If statement on lines 305 to 308:

Signal assignment statement on line 305:

Signal assignment statement on line 308:

Signal assignment statement on line 313:

If statement on lines 321 to 322:

Signal assignment statement on line 321:

Signal assignment statement on line 322:

If statement on lines 331 to 334:

Signal assignment statement on line 331:

Signal assignment statement on line 332:

Signal assignment statement on line 333:

Signal assignment statement on line 334:

If statement on lines 346 to 348:

Signal assignment statement on line 346:

Signal assignment statement on line 348:

If statement on lines 355 to 363:

Signal assignment statement on line 356:

If statement on lines 358 to 362:

Signal assignment statement on line 359:

Signal assignment statement on line 361:

If statement on lines 371 to 373:

Signal assignment statement on line 371:

Signal assignment statement on line 373:

If statement on lines 382 to 384:

Signal assignment statement on line 382:

Signal assignment statement on line 383:

Signal assignment statement on line 384:

If statement on lines 386 to 388:

Signal assignment statement on line 386:

Signal assignment statement on line 387:

Signal assignment statement on line 388:

If statement on lines 390 to 391:

Signal assignment statement on line 390:

Signal assignment statement on line 391:

If statement on lines 421 to 424:

Signal assignment statement on line 421:

Signal assignment statement on line 422:

Signal assignment statement on line 423:

Signal assignment statement on line 424:

If statement on lines 432 to 433:

Signal assignment statement on line 432:

Signal assignment statement on line 433:

Signal assignment statement on line 454:

Signal assignment statement on line 455:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 227:

"if" / "when" / "else" condition on line 236:

"if" / "when" / "else" condition on line 237:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on lines 270 to 271:

"if" / "when" / "else" condition on line 279: