NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_RAN_LOW_PRESENT_GEN_T.FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_REG_COMP.BIT_GEN(7)

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_RAN_LOW_PRESENT_GEN_T.FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_REG_COMP.BIT_GEN(7)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

149:            if (res_n = '0') then 
150:                reg_value_r(i)  <= reset_value_i(i); 
...
154:                end if; 
155:            end if;

Count: 6538071
Threshold: 1

Signal assignment statement:

150: reg_value_r(i) <= reset_value_i(i);
Count: 1324
Threshold: 1

If statement:

152:                if (wr_en = '1') then 
153:                    reg_value_r(i)  <= data_in(i); 
154:                end if;

Count: 3267778
Threshold: 1

Signal assignment statement:

153: reg_value_r(i) <= data_in(i);
Count: 14
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

149: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	1324	1
Bin	False	6536747	1

"if" / "when" / "else" condition:

151: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	3267778	1
Bin	False	3268969	1

"if" / "when" / "else" condition:

152: if (wr_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	14	1
Bin	False	3267764	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

149: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	6536747	1
Bin	True	1324	1

"=" expression

152: if (wr_en = '1') then

	Evaluated to	Count	Threshold
Bin	False	3267764	1
Bin	True	14	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_RAN_LOW_PRESENT_GEN_T.FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_REG_COMP.BIT_GEN(7)

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: