NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(6)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(7)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_WDATA_TST_WDATA_SLICE_2_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (60/60)	100.0 % (6/6)	N.A.	N.A.	100.0 % (67/67)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

145: wr_en <= write and cs and (not lock);
Count: 529645
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13267459	1
Bin	1	0	13269059	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	72382	1
Bin	1	0	1017463	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	86120	1
Bin	1	0	1003725	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	76572	1
Bin	1	0	1013273	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	80428	1
Bin	1	0	1009417	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	97296	1
Bin	1	0	992549	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	116973	1
Bin	1	0	972872	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	170870	1
Bin	1	0	918975	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	150526	1
Bin	1	0	939319	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	219247	1
Bin	1	0	220847	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	41349	1
Bin	1	0	42949	1

Port:

LOCK

	From	To	Count	Threshold
Bin	0	1	2626	1
Bin	1	0	1027	1

Port:

REG_VALUE(7)

	From	To	Count	Threshold
Bin	0	1	1575	1
Bin	1	0	3175	1

Port:

REG_VALUE(6)

	From	To	Count	Threshold
Bin	0	1	1501	1
Bin	1	0	3101	1

Port:

REG_VALUE(5)

	From	To	Count	Threshold
Bin	0	1	1559	1
Bin	1	0	3159	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	1640	1
Bin	1	0	3240	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	1646	1
Bin	1	0	3246	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	1646	1
Bin	1	0	3246	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	1672	1
Bin	1	0	3272	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	1681	1
Bin	1	0	3281	1

Signal:

REG_VALUE_R(7)

	From	To	Count	Threshold
Bin	0	1	2841	1
Bin	1	0	5212	1

Signal:

REG_VALUE_R(6)

	From	To	Count	Threshold
Bin	0	1	2948	1
Bin	1	0	5105	1

Signal:

REG_VALUE_R(5)

	From	To	Count	Threshold
Bin	0	1	3082	1
Bin	1	0	4971	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	3080	1
Bin	1	0	4973	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	2944	1
Bin	1	0	5109	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	3007	1
Bin	1	0	5046	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	3057	1
Bin	1	0	4996	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	2978	1
Bin	1	0	5075	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	32319	1
Bin	1	0	33919	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	41349	1
Bin	'1'	'0'	219247	1
Bin	'1'	'1'	41339	1

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	346900	1
Bin	'1'	'0'	9020	1
Bin	'1'	'1'	32319	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_WDATA_TST_WDATA_SLICE_2_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

Signal assignment statement:

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Port:

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Signal:

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Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: