NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/range_filter.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.RANGE_FILTER_INST.GEN_FILT_POS	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (12/12)	N.A.	N.A.	100.0 % (17/17)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.RANGE_FILTER_INST.GEN_FILT_POS

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (12/12)

N.A.

100.0 % (17/17)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 149 to 153:

149:        valid  <= '1' when ((value_dec <= upper_th_dec) and 
150:                            (value_dec >= lower_th_dec) and 
151:                            (enable = '1')) 
152:                      else 
153:                  '0';

Count: 21814
Threshold: 1

Signal assignment statement on line 149:

149: valid <= '1' when ((value_dec <= upper_th_dec) and
Count: 170
Threshold: 1

Signal assignment statement on line 153:

153: '0';
Count: 21644
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 149 to 151:

149:        valid  <= '1' when ((value_dec <= upper_th_dec) and 
150:                            (value_dec >= lower_th_dec) and 
151:                            (enable = '1'))

	Evaluated to	Count	Threshold
Bin	True	170	1
Bin	False	21644	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on lines 149 to 151:

 (value_dec <= upper_th_dec) and (value_dec >= lower_th_dec) and (enable = '1') 
 <---------------------------LHS--------------------------->      <---RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	10	1
Bin	True	False	9057	1
Bin	True	True	170	1

"and" expression on lines 149 to 150:

 (value_dec <= upper_th_dec) and (value_dec >= lower_th_dec) 
  <----------LHS---------->       <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	12575	1
Bin	True	False	12	1
Bin	True	True	9227	1

"<=" expression on line 149:

value_dec <= upper_th_dec

	Evaluated to	Count	Threshold
Bin	False	12575	1
Bin	True	9239	1

">=" expression on line 150:

value_dec >= lower_th_dec

	Evaluated to	Count	Threshold
Bin	False	12	1
Bin	True	21802	1

"=" expression on line 151:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	21634	1
Bin	True	180	1