NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.RANGE_FILTER_INST.GEN_FILT_POS	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (12/12)	N.A.	N.A.	100.0 % (17/17)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

149:        valid  <= '1' when ((value_dec <= upper_th_dec) and 
150:                            (value_dec >= lower_th_dec) and 
151:                            (enable = '1')) 
152:                      else 
153:                  '0';

Count: 19708
Threshold: 1

Signal assignment statement:

149: valid <= '1' when ((value_dec <= upper_th_dec) and
Count: 171
Threshold: 1

Signal assignment statement:

153: '0';
Count: 19537
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

149:        valid  <= '1' when ((value_dec <= upper_th_dec) and 
150:                            (value_dec >= lower_th_dec) and 
151:                            (enable = '1'))

	Evaluated to	Count	Threshold
Bin	True	171	1
Bin	False	19537	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression

149: valid <= '1' when ((value_dec <= upper_th_dec) and

	Evaluated to	Count	Threshold
Bin	False	10488	1
Bin	True	9220	1

">=" expression

150: (value_dec >= lower_th_dec) and

	Evaluated to	Count	Threshold
Bin	False	12	1
Bin	True	19696	1

"and" expression

149:        valid  <= '1' when ((value_dec <= upper_th_dec) and 
150:                            (value_dec >= lower_th_dec) and

	LHS	RHS	Count	Threshold
Bin	False	True	10488	1
Bin	True	False	12	1
Bin	True	True	9208	1

"=" expression

151: (enable = '1'))

	Evaluated to	Count	Threshold
Bin	False	19528	1
Bin	True	180	1

"and" expression

149:        valid  <= '1' when ((value_dec <= upper_th_dec) and 
150:                            (value_dec >= lower_th_dec) and 
151:                            (enable = '1'))

	LHS	RHS	Count	Threshold
Bin	False	True	9	1
Bin	True	False	9037	1
Bin	True	True	171	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.RANGE_FILTER_INST.GEN_FILT_POS

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/range_filter.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression

">=" expression

"and" expression

"=" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: