File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/range_filter.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Range Filter for CAN identifiers.
71: --
72: -- Purpose:
73: -- Filters out CAN identifier based on its decimal value. A CAN Identifier
74: -- passes the filter when decimal value of Identifier is Higher or Equal than
75: -- Lower thresholds and Lower or Equal than Higher threshold.
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: use ieee.std_logic_1164.all;
80: use ieee.numeric_std.ALL;
81:
82: Library ctu_can_fd_rtl;
83: use ctu_can_fd_rtl.can_constants_pkg.all;
84: use ctu_can_fd_rtl.can_types_pkg.all;
85:
86: use ctu_can_fd_rtl.CAN_FD_register_map.all;
87: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
88:
89: entity range_filter is
90: generic(
91: -- Filter width
92: G_WIDTH : natural;
93:
94: -- Filter presence
95: G_IS_PRESENT : boolean
96: );
97: port(
98: -- Upper threshold of a filter
99: filter_upp_th : in std_logic_vector(G_WIDTH - 1 downto 0);
100:
101: -- Lower threshold of a filter
102: filter_low_th : in std_logic_vector(G_WIDTH - 1 downto 0);
103:
104: -- Filter input
105: filter_input : in std_logic_vector(G_WIDTH - 1 downto 0);
106:
107: -- Filter enable (output is stuck at zero when disabled)
108: enable : in std_logic;
109:
110: -- Filter output
111: valid : out std_logic
112: );
113: end entity;
114:
115: architecture rtl of range_filter is
116:
117: -- Upper and lower threshold converted to unsigned values
118: signal upper_th_dec : natural range 0 to (2 ** G_WIDTH - 1);
119: signal lower_th_dec : natural range 0 to (2 ** G_WIDTH - 1);
120:
121: -- Filter input converted to unsigned value
122: signal value_dec : natural range 0 to (2 ** G_WIDTH - 1);
123:
124: procedure ID_reg_to_decimal(
125: signal ID_reg : in std_logic_vector(28 downto 0);
126: signal ID_dec : out natural range 0 to (2 ** 29 - 1)
127: ) is
128: variable base : std_logic_vector(10 downto 0);
129: variable ext : std_logic_vector(17 downto 0);
130: variable conc : std_logic_vector(28 downto 0);
131: begin
132: base := ID_reg(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
133: ext := ID_reg(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
134: conc := base&ext;
135: ID_dec <= to_integer(unsigned(conc));
136: end procedure ID_reg_to_decimal;
137:
138: begin
139:
140: -- Conversion procedures
141: ID_reg_to_decimal(filter_input, value_dec);
142:
143: ID_reg_to_decimal(filter_upp_th, upper_th_dec);
144: ID_reg_to_decimal(filter_low_th, lower_th_dec);
145:
146: -- Filter implementation
147: gen_filt_pos : if (G_IS_PRESENT = true) generate
148: valid <= '1' when ((value_dec <= upper_th_dec) and
149: (value_dec >= lower_th_dec) and
150: (enable = '1'))
151: else
152: '0';
153: end generate;
154:
155: gen_filtRan_neg : if (G_IS_PRESENT = false) generate
156: valid <= '0';
157: end generate;
158:
159: end architecture;