NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
PARITY_CALCULATOR_WRITE_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)
PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.PARITY_TRUE_GEN	100.0 % (10/10)	100.0 % (12/12)	N.A.	100.0 % (8/8)	N.A.	N.A.	100.0 % (30/30)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

227:            if (res_n = '0') then 
228:                parity_word <= (others => '0'); 
...
232:                end if; 
233:            end if;

Count: 26744966
Threshold: 1

Signal assignment statement:

228: parity_word <= (others => '0');
Count: 897696
Threshold: 1

If statement:

230:                if (rxb_port_a_write = '1') then 
231:                    parity_word(to_integer(unsigned(rxb_port_a_address))) <= parity_write; 
232:                end if;

Count: 12921706
Threshold: 1

Signal assignment statement:

231: parity_word(to_integer(unsigned(rxb_port_a_address))) <= parity_write;
Count: 68805
Threshold: 1

If statement:

256:            if (res_n = '0') then 
257:                parity_read_exp <= '0'; 
258:            elsif (rising_edge(clk_sys)) then 
259:                parity_read_exp <= parity_word(to_integer(unsigned(rxb_port_b_address))); 
260:            end if;

Count: 26744966
Threshold: 1

Signal assignment statement:

257: parity_read_exp <= '0';
Count: 897696
Threshold: 1

Signal assignment statement:

259: parity_read_exp <= parity_word(to_integer(unsigned(rxb_port_b_address)));
Count: 12921706
Threshold: 1

If statement:

263:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) 
264:                               else 
265:                           '0';

Count: 48413
Threshold: 1

Signal assignment statement:

263: parity_mismatch <= '1' when (parity_read_real /= parity_read_exp)
Count: 29532
Threshold: 1

Signal assignment statement:

265: '0';
Count: 18881
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

227: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	897696	1
Bin	False	25847270	1

"if" / "when" / "else" condition:

229: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	12921706	1
Bin	False	12925564	1

"if" / "when" / "else" condition:

230: if (rxb_port_a_write = '1') then

	Evaluated to	Count	Threshold
Bin	True	68805	1
Bin	False	12852901	1

"if" / "when" / "else" condition:

256: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	897696	1
Bin	False	25847270	1

"if" / "when" / "else" condition:

258: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	12921706	1
Bin	False	12925564	1

"if" / "when" / "else" condition:

263: parity_mismatch <= '1' when (parity_read_real /= parity_read_exp)

	Evaluated to	Count	Threshold
Bin	True	29532	1
Bin	False	18881	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

227: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	25847270	1
Bin	True	897696	1

"=" expression

230: if (rxb_port_a_write = '1') then

	Evaluated to	Count	Threshold
Bin	False	12852901	1
Bin	True	68805	1

"=" expression

256: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	25847270	1
Bin	True	897696	1

"/=" expression

263: parity_mismatch <= '1' when (parity_read_real /= parity_read_exp)

	Evaluated to	Count	Threshold
Bin	False	18881	1
Bin	True	29532	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.PARITY_TRUE_GEN

File: /__w/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_ram.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"=" expression

"/=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: