NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 48554
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 48554
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 1553728
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 48554
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	2563	1
Bin	1	0	3182	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	2627	1
Bin	1	0	3247	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	2421	1
Bin	1	0	3040	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	6457	1
Bin	1	0	7023	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	6281	1
Bin	1	0	6852	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	6359	1
Bin	1	0	6928	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	6779	1
Bin	1	0	7348	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	5945	1
Bin	1	0	6512	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	6669	1
Bin	1	0	7227	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	6379	1
Bin	1	0	6950	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	6856	1
Bin	1	0	7402	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	6274	1
Bin	1	0	6837	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	7592	1
Bin	1	0	8147	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	6580	1
Bin	1	0	7140	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	4496	1
Bin	1	0	5090	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	4347	1
Bin	1	0	4939	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	4640	1
Bin	1	0	5238	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	5190	1
Bin	1	0	5784	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	4935	1
Bin	1	0	5531	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	5404	1
Bin	1	0	5996	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	4625	1
Bin	1	0	5222	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	4563	1
Bin	1	0	5152	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	7251	1
Bin	1	0	7778	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	5525	1
Bin	1	0	6108	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	10859	1
Bin	1	0	11343	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	9838	1
Bin	1	0	10353	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	7280	1
Bin	1	0	7859	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	5290	1
Bin	1	0	5884	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	7493	1
Bin	1	0	8028	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	7155	1
Bin	1	0	7698	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	7592	1
Bin	1	0	8124	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	8235	1
Bin	1	0	8755	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	12592	1
Bin	1	0	12119	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	396597	1
Bin	'0'	'1'	112103	1
Bin	'1'	'0'	893970	1
Bin	'1'	'1'	129938	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

Variable assignment statement:

Loop statement:

Variable assignment statement:

Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: