NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_PRESCALER_NBT_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_prescaler_nbt.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_PRESCALER_NBT_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (9/9) 100.0 % (11/11)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK
FromToCountThreshold
Bin015275788681
Bin105275804601

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

133:    -- psl nbt_pos_resync_e_less_than_sjw_cov : cover 
134:    --  {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1' 
135:    --   and resync_edge_valid = '1' and 
136:    --   (to_integer(unsigned(phase_err)) < to_integer(unsigned(sjw)))}; 
Count: 550224
Threshold: 1

PSL cover point:

139:    -- psl nbt_pos_resync_e_more_than_sjw_cov : cover 
140:    --  {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1' 
141:    --   and resync_edge_valid = '1' and 
142:    --   (to_integer(unsigned(phase_err)) > to_integer(unsigned(sjw)))}; 
Count: 4405
Threshold: 1

PSL cover point:

145:    -- psl nbt_pos_resync_e_equal_sjw_cov : cover 
146:    --  {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1' 
147:    --   and resync_edge_valid = '1' and 
148:    --   (to_integer(unsigned(phase_err)) = to_integer(unsigned(sjw)))}; 
Count: 146941
Threshold: 1

PSL cover point:

151:    -- psl nbt_neg_resync_e_less_than_sjw_cov : cover 
152:    --  {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and 
153:    --   (to_integer(unsigned(phase_err)) < to_integer(unsigned(sjw)))}; 
Count: 9214
Threshold: 1

PSL cover point:

156:    -- psl nbt_neg_resync_e_more_than_sjw_cov : cover 
157:    --  {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and 
158:    --   (to_integer(unsigned(phase_err)) > to_integer(unsigned(sjw)))}; 
Count: 7442
Threshold: 1

PSL cover point:

161:    -- psl nbt_neg_resync_e_equal_sjw_cov : cover 
162:    --  {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and 
163:    --   (to_integer(unsigned(phase_err)) = to_integer(unsigned(sjw)))}; 
Count: 92
Threshold: 1

PSL cover point:

165:    -- psl nbt_exit_segm_immediate_cov : cover 
166:    --  {exit_segm_req = '1' and exit_ph2_immediate = '1'}; 
Count: 9539
Threshold: 1

PSL cover point:

168:    -- psl nbt_exit_segm_regular_tseg1_cov : cover 
169:    --  {exit_segm_req = '1' and exit_segm_regular_tseg1 = '1' and exit_segm_regular_tseg2 = '0'}; 
Count: 16118554
Threshold: 1

PSL cover point:

171:    -- psl nbt_exit_segm_regular_tseg2_cov : cover 
172:    --  {exit_segm_req = '1' and exit_segm_regular_tseg1 = '0' and exit_segm_regular_tseg2 = '1'}; 
Count: 13600168
Threshold: 1