Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| DP_INF_RAM_BE_INST |
100.0 % (19/19) |
100.0 % (14/14) |
100.0 % (1578/1578) |
100.0 % (30/30) |
N.A. |
N.A. |
100.0 % (1641/1641) |
| PARITY_TRUE_GEN |
100.0 % (14/14) |
100.0 % (12/12) |
100.0 % (66/66) |
100.0 % (17/17) |
N.A. |
N.A. |
100.0 % (109/109) |
| PARITY_FALSE_GEN |
100.0 % (4/4) |
N.A. |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (4/4) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
278: (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))
279: else
280: '0'; Count: 6706
Threshold: 1
Signal assignment statement:
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and Count: 320
Threshold: 1
Signal assignment statement:
280: '0'; Count: 6386
Threshold: 1
If statement:
283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
284: else
285: mr_tst_dest_tst_addr(4 downto 0); Count: 55685183
Threshold: 1
Signal assignment statement:
283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') Count: 55617875
Threshold: 1
Signal assignment statement:
285: mr_tst_dest_tst_addr(4 downto 0); Count: 67308
Threshold: 1
If statement:
287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
288: else
289: mr_tst_control_twrstb; Count: 419441
Threshold: 1
Signal assignment statement:
287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') Count: 413657
Threshold: 1
Signal assignment statement:
289: mr_tst_control_twrstb; Count: 5784
Threshold: 1
If statement:
291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
292: else
293: mr_tst_wdata_tst_wdata; Count: 2193357
Threshold: 1
Signal assignment statement:
291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') Count: 2150285
Threshold: 1
Signal assignment statement:
293: mr_tst_wdata_tst_wdata; Count: 43072
Threshold: 1
If statement:
296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
297: else
298: mr_tst_dest_tst_addr(4 downto 0); Count: 353689
Threshold: 1
Signal assignment statement:
296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') Count: 348443
Threshold: 1
Signal assignment statement:
298: mr_tst_dest_tst_addr(4 downto 0); Count: 5246
Threshold: 1
If statement:
300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
301: else
302: (others => '0'); Count: 139502
Threshold: 1
Signal assignment statement:
300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') Count: 2786
Threshold: 1
Signal assignment statement:
302: (others => '0'); Count: 136716
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
278: (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 320 | 1 |
| Bin | False | 6386 | 1 |
"if" / "when" / "else" condition:
283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 55617875 | 1 |
| Bin | False | 67308 | 1 |
"if" / "when" / "else" condition:
287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 413657 | 1 |
| Bin | False | 5784 | 1 |
"if" / "when" / "else" condition:
291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2150285 | 1 |
| Bin | False | 43072 | 1 |
"if" / "when" / "else" condition:
296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 348443 | 1 |
| Bin | False | 5246 | 1 |
"if" / "when" / "else" condition:
300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2786 | 1 |
| Bin | False | 136716 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14047312 | 1 |
| Bin | 1 | 0 | 14048912 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
MR_SETTINGS_PCHKE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1714 | 1 |
Port:
MR_TST_CONTROL_TMAENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 648 | 1 |
| Bin | 1 | 0 | 2248 | 1 |
Port:
MR_TST_CONTROL_TWRSTB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32309 | 1 |
| Bin | 1 | 0 | 35200 | 1 |
Port:
MR_TST_DEST_TST_ADDR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3617 | 1 |
| Bin | 1 | 0 | 5217 | 1 |
Port:
MR_TST_DEST_TST_ADDR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5031 | 1 |
| Bin | 1 | 0 | 6631 | 1 |
Port:
MR_TST_DEST_TST_ADDR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10323 | 1 |
| Bin | 1 | 0 | 11923 | 1 |
Port:
MR_TST_DEST_TST_ADDR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22448 | 1 |
| Bin | 1 | 0 | 24048 | 1 |
Port:
MR_TST_DEST_TST_ADDR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44884 | 1 |
| Bin | 1 | 0 | 46484 | 1 |
Port:
MR_TST_DEST_TST_MTGT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 235 | 1 |
| Bin | 1 | 0 | 1835 | 1 |
Port:
MR_TST_DEST_TST_MTGT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 374 | 1 |
| Bin | 1 | 0 | 1974 | 1 |
Port:
MR_TST_DEST_TST_MTGT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 514 | 1 |
| Bin | 1 | 0 | 2114 | 1 |
Port:
MR_TST_DEST_TST_MTGT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 979 | 1 |
| Bin | 1 | 0 | 2579 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1535 | 1 |
| Bin | 1 | 0 | 3135 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1484 | 1 |
| Bin | 1 | 0 | 3084 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1491 | 1 |
| Bin | 1 | 0 | 3091 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1631 | 1 |
| Bin | 1 | 0 | 3231 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1645 | 1 |
| Bin | 1 | 0 | 3245 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1629 | 1 |
| Bin | 1 | 0 | 3229 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1641 | 1 |
| Bin | 1 | 0 | 3241 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713 | 1 |
| Bin | 1 | 0 | 3313 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1587 | 1 |
| Bin | 1 | 0 | 3187 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1526 | 1 |
| Bin | 1 | 0 | 3126 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1560 | 1 |
| Bin | 1 | 0 | 3160 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1658 | 1 |
| Bin | 1 | 0 | 3258 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1636 | 1 |
| Bin | 1 | 0 | 3236 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1632 | 1 |
| Bin | 1 | 0 | 3232 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1670 | 1 |
| Bin | 1 | 0 | 3270 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1575 | 1 |
| Bin | 1 | 0 | 3175 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1501 | 1 |
| Bin | 1 | 0 | 3101 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1559 | 1 |
| Bin | 1 | 0 | 3159 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1640 | 1 |
| Bin | 1 | 0 | 3240 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1672 | 1 |
| Bin | 1 | 0 | 3272 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1681 | 1 |
| Bin | 1 | 0 | 3281 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1633 | 1 |
| Bin | 1 | 0 | 3233 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1567 | 1 |
| Bin | 1 | 0 | 3167 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1601 | 1 |
| Bin | 1 | 0 | 3201 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1637 | 1 |
| Bin | 1 | 0 | 3237 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1640 | 1 |
| Bin | 1 | 0 | 3240 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1655 | 1 |
| Bin | 1 | 0 | 3255 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1656 | 1 |
| Bin | 1 | 0 | 3256 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1722 | 1 |
| Bin | 1 | 0 | 3322 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 582 | 1 |
| Bin | 1 | 0 | 2182 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 567 | 1 |
| Bin | 1 | 0 | 2167 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 574 | 1 |
| Bin | 1 | 0 | 2174 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 637 | 1 |
| Bin | 1 | 0 | 2237 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 652 | 1 |
| Bin | 1 | 0 | 2252 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 629 | 1 |
| Bin | 1 | 0 | 2229 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 654 | 1 |
| Bin | 1 | 0 | 2254 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 670 | 1 |
| Bin | 1 | 0 | 2270 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 647 | 1 |
| Bin | 1 | 0 | 2247 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 634 | 1 |
| Bin | 1 | 0 | 2234 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 650 | 1 |
| Bin | 1 | 0 | 2250 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 651 | 1 |
| Bin | 1 | 0 | 2251 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 656 | 1 |
| Bin | 1 | 0 | 2256 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 641 | 1 |
| Bin | 1 | 0 | 2241 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 628 | 1 |
| Bin | 1 | 0 | 2228 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 624 | 1 |
| Bin | 1 | 0 | 2224 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 641 | 1 |
| Bin | 1 | 0 | 2241 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 623 | 1 |
| Bin | 1 | 0 | 2223 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 612 | 1 |
| Bin | 1 | 0 | 2212 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 618 | 1 |
| Bin | 1 | 0 | 2218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 602 | 1 |
| Bin | 1 | 0 | 2202 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 637 | 1 |
| Bin | 1 | 0 | 2237 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640 | 1 |
| Bin | 1 | 0 | 2240 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 620 | 1 |
| Bin | 1 | 0 | 2220 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 654 | 1 |
| Bin | 1 | 0 | 2254 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 652 | 1 |
| Bin | 1 | 0 | 2252 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 645 | 1 |
| Bin | 1 | 0 | 2245 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 621 | 1 |
| Bin | 1 | 0 | 2221 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 637 | 1 |
| Bin | 1 | 0 | 2237 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 636 | 1 |
| Bin | 1 | 0 | 2236 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 651 | 1 |
| Bin | 1 | 0 | 2251 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640 | 1 |
| Bin | 1 | 0 | 2240 | 1 |
Port:
TXTB_PORT_A_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 328560 | 1 |
| Bin | 1 | 0 | 27467073 | 1 |
Port:
TXTB_PORT_A_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576099 | 1 |
| Bin | 1 | 0 | 27219534 | 1 |
Port:
TXTB_PORT_A_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436079 | 1 |
| Bin | 1 | 0 | 27359554 | 1 |
Port:
TXTB_PORT_A_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27015237 | 1 |
| Bin | 1 | 0 | 780396 | 1 |
Port:
TXTB_PORT_A_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17655249 | 1 |
| Bin | 1 | 0 | 10140384 | 1 |
Port:
TXTB_PORT_A_DATA_IN(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61362 | 1 |
| Bin | 1 | 0 | 1030083 | 1 |
Port:
TXTB_PORT_A_DATA_IN(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67108 | 1 |
| Bin | 1 | 0 | 1024337 | 1 |
Port:
TXTB_PORT_A_DATA_IN(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63097 | 1 |
| Bin | 1 | 0 | 1028348 | 1 |
Port:
TXTB_PORT_A_DATA_IN(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91439 | 1 |
| Bin | 1 | 0 | 1000006 | 1 |
Port:
TXTB_PORT_A_DATA_IN(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79643 | 1 |
| Bin | 1 | 0 | 1011802 | 1 |
Port:
TXTB_PORT_A_DATA_IN(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76527 | 1 |
| Bin | 1 | 0 | 1014918 | 1 |
Port:
TXTB_PORT_A_DATA_IN(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88276 | 1 |
| Bin | 1 | 0 | 1003169 | 1 |
Port:
TXTB_PORT_A_DATA_IN(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78188 | 1 |
| Bin | 1 | 0 | 1013257 | 1 |
Port:
TXTB_PORT_A_DATA_IN(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70931 | 1 |
| Bin | 1 | 0 | 1020514 | 1 |
Port:
TXTB_PORT_A_DATA_IN(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108138 | 1 |
| Bin | 1 | 0 | 983307 | 1 |
Port:
TXTB_PORT_A_DATA_IN(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 74867 | 1 |
| Bin | 1 | 0 | 1016578 | 1 |
Port:
TXTB_PORT_A_DATA_IN(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80468 | 1 |
| Bin | 1 | 0 | 1010977 | 1 |
Port:
TXTB_PORT_A_DATA_IN(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110009 | 1 |
| Bin | 1 | 0 | 981436 | 1 |
Port:
TXTB_PORT_A_DATA_IN(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 131558 | 1 |
| Bin | 1 | 0 | 959887 | 1 |
Port:
TXTB_PORT_A_DATA_IN(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123951 | 1 |
| Bin | 1 | 0 | 967494 | 1 |
Port:
TXTB_PORT_A_DATA_IN(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 193513 | 1 |
| Bin | 1 | 0 | 897932 | 1 |
Port:
TXTB_PORT_A_DATA_IN(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 72382 | 1 |
| Bin | 1 | 0 | 1019063 | 1 |
Port:
TXTB_PORT_A_DATA_IN(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 86120 | 1 |
| Bin | 1 | 0 | 1005325 | 1 |
Port:
TXTB_PORT_A_DATA_IN(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76572 | 1 |
| Bin | 1 | 0 | 1014873 | 1 |
Port:
TXTB_PORT_A_DATA_IN(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80428 | 1 |
| Bin | 1 | 0 | 1011017 | 1 |
Port:
TXTB_PORT_A_DATA_IN(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 97296 | 1 |
| Bin | 1 | 0 | 994149 | 1 |
Port:
TXTB_PORT_A_DATA_IN(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116973 | 1 |
| Bin | 1 | 0 | 974472 | 1 |
Port:
TXTB_PORT_A_DATA_IN(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170870 | 1 |
| Bin | 1 | 0 | 920575 | 1 |
Port:
TXTB_PORT_A_DATA_IN(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 150526 | 1 |
| Bin | 1 | 0 | 940919 | 1 |
Port:
TXTB_PORT_A_DATA_IN(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126416 | 1 |
| Bin | 1 | 0 | 965029 | 1 |
Port:
TXTB_PORT_A_DATA_IN(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109550 | 1 |
| Bin | 1 | 0 | 981895 | 1 |
Port:
TXTB_PORT_A_DATA_IN(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103929 | 1 |
| Bin | 1 | 0 | 987516 | 1 |
Port:
TXTB_PORT_A_DATA_IN(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 162358 | 1 |
| Bin | 1 | 0 | 929087 | 1 |
Port:
TXTB_PORT_A_DATA_IN(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 135873 | 1 |
| Bin | 1 | 0 | 955572 | 1 |
Port:
TXTB_PORT_A_DATA_IN(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 159944 | 1 |
| Bin | 1 | 0 | 931501 | 1 |
Port:
TXTB_PORT_A_DATA_IN(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 236123 | 1 |
| Bin | 1 | 0 | 855322 | 1 |
Port:
TXTB_PORT_A_DATA_IN(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 198401 | 1 |
| Bin | 1 | 0 | 893044 | 1 |
Port:
TXTB_PORT_A_PARITY | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640015 | 1 |
| Bin | 1 | 0 | 150105 | 1 |
Port:
TXTB_PORT_A_WRITE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 157246 | 1 |
| Bin | 1 | 0 | 158846 | 1 |
Port:
TXTB_PORT_A_BE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
Port:
TXTB_PORT_A_BE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
Port:
TXTB_PORT_A_BE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
Port:
TXTB_PORT_A_BE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
Port:
TXTB_PORT_B_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26805 | 1 |
| Bin | 1 | 0 | 28405 | 1 |
Port:
TXTB_PORT_B_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3865 | 1 |
| Bin | 1 | 0 | 5465 | 1 |
Port:
TXTB_PORT_B_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45730 | 1 |
| Bin | 1 | 0 | 47330 | 1 |
Port:
TXTB_PORT_B_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37881 | 1 |
| Bin | 1 | 0 | 37884 | 1 |
Port:
TXTB_PORT_B_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101251 | 1 |
| Bin | 1 | 0 | 102848 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7982 | 1 |
| Bin | 1 | 0 | 9531 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8391 | 1 |
| Bin | 1 | 0 | 9941 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7951 | 1 |
| Bin | 1 | 0 | 9500 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21337 | 1 |
| Bin | 1 | 0 | 22803 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18079 | 1 |
| Bin | 1 | 0 | 19542 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21592 | 1 |
| Bin | 1 | 0 | 23060 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19020 | 1 |
| Bin | 1 | 0 | 20484 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21640 | 1 |
| Bin | 1 | 0 | 23098 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19308 | 1 |
| Bin | 1 | 0 | 20759 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21402 | 1 |
| Bin | 1 | 0 | 22867 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19325 | 1 |
| Bin | 1 | 0 | 20764 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21408 | 1 |
| Bin | 1 | 0 | 22873 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19799 | 1 |
| Bin | 1 | 0 | 21245 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22132 | 1 |
| Bin | 1 | 0 | 23584 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12505 | 1 |
| Bin | 1 | 0 | 14008 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13382 | 1 |
| Bin | 1 | 0 | 14882 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12705 | 1 |
| Bin | 1 | 0 | 14215 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13403 | 1 |
| Bin | 1 | 0 | 14907 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13291 | 1 |
| Bin | 1 | 0 | 14792 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14133 | 1 |
| Bin | 1 | 0 | 15641 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12866 | 1 |
| Bin | 1 | 0 | 14378 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13590 | 1 |
| Bin | 1 | 0 | 15048 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24187 | 1 |
| Bin | 1 | 0 | 25506 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14564 | 1 |
| Bin | 1 | 0 | 16054 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32866 | 1 |
| Bin | 1 | 0 | 34054 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 23359 | 1 |
| Bin | 1 | 0 | 24661 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17257 | 1 |
| Bin | 1 | 0 | 18732 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15439 | 1 |
| Bin | 1 | 0 | 16942 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25480 | 1 |
| Bin | 1 | 0 | 26827 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24873 | 1 |
| Bin | 1 | 0 | 26216 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26244 | 1 |
| Bin | 1 | 0 | 27591 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34015 | 1 |
| Bin | 1 | 0 | 35197 | 1 |
Port:
PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2040 | 1 |
| Bin | 1 | 0 | 3640 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 328745 | 1 |
| Bin | 1 | 0 | 27436227 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576261 | 1 |
| Bin | 1 | 0 | 27188665 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436500 | 1 |
| Bin | 1 | 0 | 27328944 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27002546 | 1 |
| Bin | 1 | 0 | 763850 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17632746 | 1 |
| Bin | 1 | 0 | 10135550 | 1 |
Signal:
TXTB_PORT_A_WRITE_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 158440 | 1 |
| Bin | 1 | 0 | 160206 | 1 |
Signal:
TXTB_PORT_A_DATA_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60678 | 1 |
| Bin | 1 | 0 | 1010596 | 1 |
Signal:
TXTB_PORT_A_DATA_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66425 | 1 |
| Bin | 1 | 0 | 1004845 | 1 |
Signal:
TXTB_PORT_A_DATA_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 62427 | 1 |
| Bin | 1 | 0 | 1008859 | 1 |
Signal:
TXTB_PORT_A_DATA_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 90777 | 1 |
| Bin | 1 | 0 | 980547 | 1 |
Signal:
TXTB_PORT_A_DATA_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78972 | 1 |
| Bin | 1 | 0 | 992364 | 1 |
Signal:
TXTB_PORT_A_DATA_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75843 | 1 |
| Bin | 1 | 0 | 995469 | 1 |
Signal:
TXTB_PORT_A_DATA_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 87536 | 1 |
| Bin | 1 | 0 | 983800 | 1 |
Signal:
TXTB_PORT_A_DATA_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 77526 | 1 |
| Bin | 1 | 0 | 993834 | 1 |
Signal:
TXTB_PORT_A_DATA_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70266 | 1 |
| Bin | 1 | 0 | 1001080 | 1 |
Signal:
TXTB_PORT_A_DATA_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107468 | 1 |
| Bin | 1 | 0 | 963864 | 1 |
Signal:
TXTB_PORT_A_DATA_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 74180 | 1 |
| Bin | 1 | 0 | 997130 | 1 |
Signal:
TXTB_PORT_A_DATA_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79802 | 1 |
| Bin | 1 | 0 | 991538 | 1 |
Signal:
TXTB_PORT_A_DATA_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107336 | 1 |
| Bin | 1 | 0 | 963992 | 1 |
Signal:
TXTB_PORT_A_DATA_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126901 | 1 |
| Bin | 1 | 0 | 944475 | 1 |
Signal:
TXTB_PORT_A_DATA_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 113735 | 1 |
| Bin | 1 | 0 | 957669 | 1 |
Signal:
TXTB_PORT_A_DATA_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 186660 | 1 |
| Bin | 1 | 0 | 884685 | 1 |
Signal:
TXTB_PORT_A_DATA_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 71707 | 1 |
| Bin | 1 | 0 | 999609 | 1 |
Signal:
TXTB_PORT_A_DATA_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 85453 | 1 |
| Bin | 1 | 0 | 985883 | 1 |
Signal:
TXTB_PORT_A_DATA_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75886 | 1 |
| Bin | 1 | 0 | 995430 | 1 |
Signal:
TXTB_PORT_A_DATA_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79744 | 1 |
| Bin | 1 | 0 | 991568 | 1 |
Signal:
TXTB_PORT_A_DATA_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96625 | 1 |
| Bin | 1 | 0 | 974687 | 1 |
Signal:
TXTB_PORT_A_DATA_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116273 | 1 |
| Bin | 1 | 0 | 955041 | 1 |
Signal:
TXTB_PORT_A_DATA_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170117 | 1 |
| Bin | 1 | 0 | 901211 | 1 |
Signal:
TXTB_PORT_A_DATA_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 149815 | 1 |
| Bin | 1 | 0 | 921499 | 1 |
Signal:
TXTB_PORT_A_DATA_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 125738 | 1 |
| Bin | 1 | 0 | 945608 | 1 |
Signal:
TXTB_PORT_A_DATA_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108875 | 1 |
| Bin | 1 | 0 | 962477 | 1 |
Signal:
TXTB_PORT_A_DATA_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103248 | 1 |
| Bin | 1 | 0 | 968094 | 1 |
Signal:
TXTB_PORT_A_DATA_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 158887 | 1 |
| Bin | 1 | 0 | 912437 | 1 |
Signal:
TXTB_PORT_A_DATA_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 129939 | 1 |
| Bin | 1 | 0 | 941409 | 1 |
Signal:
TXTB_PORT_A_DATA_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 153812 | 1 |
| Bin | 1 | 0 | 917568 | 1 |
Signal:
TXTB_PORT_A_DATA_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 225548 | 1 |
| Bin | 1 | 0 | 845823 | 1 |
Signal:
TXTB_PORT_A_DATA_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 188750 | 1 |
| Bin | 1 | 0 | 882727 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26992 | 1 |
| Bin | 1 | 0 | 28592 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4027 | 1 |
| Bin | 1 | 0 | 5627 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46153 | 1 |
| Bin | 1 | 0 | 47753 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 38920 | 1 |
| Bin | 1 | 0 | 38923 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103011 | 1 |
| Bin | 1 | 0 | 104608 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7982 | 1 |
| Bin | 1 | 0 | 9531 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8391 | 1 |
| Bin | 1 | 0 | 9941 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7951 | 1 |
| Bin | 1 | 0 | 9500 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21337 | 1 |
| Bin | 1 | 0 | 22803 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18079 | 1 |
| Bin | 1 | 0 | 19542 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21592 | 1 |
| Bin | 1 | 0 | 23060 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19020 | 1 |
| Bin | 1 | 0 | 20484 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21640 | 1 |
| Bin | 1 | 0 | 23098 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19308 | 1 |
| Bin | 1 | 0 | 20759 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21402 | 1 |
| Bin | 1 | 0 | 22867 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19325 | 1 |
| Bin | 1 | 0 | 20764 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21408 | 1 |
| Bin | 1 | 0 | 22873 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19799 | 1 |
| Bin | 1 | 0 | 21245 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22132 | 1 |
| Bin | 1 | 0 | 23584 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12505 | 1 |
| Bin | 1 | 0 | 14008 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13382 | 1 |
| Bin | 1 | 0 | 14882 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12705 | 1 |
| Bin | 1 | 0 | 14215 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13403 | 1 |
| Bin | 1 | 0 | 14907 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13291 | 1 |
| Bin | 1 | 0 | 14792 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14133 | 1 |
| Bin | 1 | 0 | 15641 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12866 | 1 |
| Bin | 1 | 0 | 14378 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13590 | 1 |
| Bin | 1 | 0 | 15048 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24187 | 1 |
| Bin | 1 | 0 | 25506 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14564 | 1 |
| Bin | 1 | 0 | 16054 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32866 | 1 |
| Bin | 1 | 0 | 34054 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 23359 | 1 |
| Bin | 1 | 0 | 24661 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17257 | 1 |
| Bin | 1 | 0 | 18732 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15439 | 1 |
| Bin | 1 | 0 | 16942 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25480 | 1 |
| Bin | 1 | 0 | 26827 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24873 | 1 |
| Bin | 1 | 0 | 26216 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26244 | 1 |
| Bin | 1 | 0 | 27591 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34015 | 1 |
| Bin | 1 | 0 | 35197 | 1 |
Signal:
TST_ENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 320 | 1 |
| Bin | 1 | 0 | 1920 | 1 |
Signal:
PARITY_WORD(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 157 | 1 |
| Bin | 1 | 0 | 8846 | 1 |
Signal:
PARITY_WORD(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9 | 1 |
| Bin | 1 | 0 | 8994 | 1 |
Signal:
PARITY_WORD(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 8963 | 1 |
Signal:
PARITY_WORD(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 8947 | 1 |
Signal:
PARITY_WORD(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 8932 | 1 |
Signal:
PARITY_WORD(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76 | 1 |
| Bin | 1 | 0 | 8927 | 1 |
Signal:
PARITY_WORD(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 8943 | 1 |
Signal:
PARITY_WORD(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 133 | 1 |
| Bin | 1 | 0 | 8870 | 1 |
Signal:
PARITY_WORD(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 152 | 1 |
| Bin | 1 | 0 | 8851 | 1 |
Signal:
PARITY_WORD(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 415 | 1 |
| Bin | 1 | 0 | 8588 | 1 |
Signal:
PARITY_WORD(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 430 | 1 |
| Bin | 1 | 0 | 8573 | 1 |
Signal:
PARITY_WORD(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 312 | 1 |
| Bin | 1 | 0 | 8691 | 1 |
Signal:
PARITY_WORD(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 636 | 1 |
| Bin | 1 | 0 | 8367 | 1 |
Signal:
PARITY_WORD(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 524 | 1 |
| Bin | 1 | 0 | 8479 | 1 |
Signal:
PARITY_WORD(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 646 | 1 |
| Bin | 1 | 0 | 8357 | 1 |
Signal:
PARITY_WORD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1234 | 1 |
| Bin | 1 | 0 | 7769 | 1 |
Signal:
PARITY_WORD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2398 | 1 |
| Bin | 1 | 0 | 6605 | 1 |
Signal:
PARITY_WORD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4281 | 1 |
| Bin | 1 | 0 | 4722 | 1 |
Signal:
PARITY_WORD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5255 | 1 |
| Bin | 1 | 0 | 3748 | 1 |
Signal:
PARITY_WORD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3304 | 1 |
| Bin | 1 | 0 | 5699 | 1 |
Signal:
PARITY_WORD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3441 | 1 |
| Bin | 1 | 0 | 5562 | 1 |
Signal:
PARITY_READ_REAL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12592 | 1 |
| Bin | 1 | 0 | 13059 | 1 |
Signal:
PARITY_READ_EXP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15675 | 1 |
| Bin | 1 | 0 | 17275 | 1 |
Excluded expressions:
"and" expression
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
278: (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) | LHS | RHS | Count | Threshold | Excluded due to |
|---|
| Bin | False | True | 0 | 1 | Unreachable |
Covered expressions:
"=" expression
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 4855 | 1 |
| Bin | True | 1851 | 1 |
"and" expression
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
278: (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) | LHS | RHS | Count | Threshold |
|---|
| Bin | True | False | 1531 | 1 |
| Bin | True | True | 320 | 1 |
"=" expression
283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 67308 | 1 |
| Bin | True | 55617875 | 1 |
"=" expression
287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 5784 | 1 |
| Bin | True | 413657 | 1 |
"=" expression
291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 43072 | 1 |
| Bin | True | 2150285 | 1 |
"=" expression
296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 5246 | 1 |
| Bin | True | 348443 | 1 |
"=" expression
300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 136716 | 1 |
| Bin | True | 2786 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: