NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DP_INF_RAM_BE_INST	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	90.0 % (27/30)	N.A.	N.A.	99.8 % (1638/1641)
PARITY_TRUE_GEN	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (13/13)	N.A.	N.A.	100.0 % (105/105)
PARITY_FALSE_GEN	100.0 % (4/4)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST	100.0 % (19/19)	100.0 % (12/12)	100.0 % (516/516)	100.0 % (15/15)	N.A.	N.A.	100.0 % (562/562)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

208: txtb_port_b_data_out <= txtb_port_b_data_out_i;
Count: 139821
Threshold: 1

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 6708
Threshold: 1

Signal assignment statement on line 277:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 319
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 6389
Threshold: 1

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 55148195
Threshold: 1

Signal assignment statement on line 283:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 55080899
Threshold: 1

Signal assignment statement on line 285:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 67296
Threshold: 1

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 428982
Threshold: 1

Signal assignment statement on line 287:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 423201
Threshold: 1

Signal assignment statement on line 289:

289: mr_tst_control_twrstb;
Count: 5781
Threshold: 1

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 2228100
Threshold: 1

Signal assignment statement on line 291:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 2185037
Threshold: 1

Signal assignment statement on line 293:

293: mr_tst_wdata_tst_wdata;
Count: 43063
Threshold: 1

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 357798
Threshold: 1

Signal assignment statement on line 296:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 352554
Threshold: 1

Signal assignment statement on line 298:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 5244
Threshold: 1

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 142060
Threshold: 1

Signal assignment statement on line 300:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 2780
Threshold: 1

Signal assignment statement on line 302:

302: (others => '0');
Count: 139280
Threshold: 1

	Evaluated to	Count	Threshold
Bin	True	319	1
Bin	False	6389	1

	Evaluated to	Count	Threshold
Bin	True	55080899	1
Bin	False	67296	1

	Evaluated to	Count	Threshold
Bin	True	423201	1
Bin	False	5781	1

	Evaluated to	Count	Threshold
Bin	True	2185037	1
Bin	False	43063	1

	Evaluated to	Count	Threshold
Bin	True	352554	1
Bin	False	5244	1

	Evaluated to	Count	Threshold
Bin	True	2780	1
Bin	False	139280	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	584	1
Bin	(31)	1	0	2185	1
Bin	(30)	0	1	577	1
Bin	(30)	1	0	2178	1
Bin	(29)	0	1	579	1
Bin	(29)	1	0	2180	1
Bin	(28)	0	1	648	1
Bin	(28)	1	0	2249	1
Bin	(27)	0	1	636	1
Bin	(27)	1	0	2237	1
Bin	(26)	0	1	655	1
Bin	(26)	1	0	2256	1
Bin	(25)	0	1	646	1
Bin	(25)	1	0	2247	1
Bin	(24)	0	1	635	1
Bin	(24)	1	0	2236	1
Bin	(23)	0	1	656	1
Bin	(23)	1	0	2257	1
Bin	(22)	0	1	637	1
Bin	(22)	1	0	2238	1
Bin	(21)	0	1	659	1
Bin	(21)	1	0	2260	1
Bin	(20)	0	1	654	1
Bin	(20)	1	0	2255	1
Bin	(19)	0	1	662	1
Bin	(19)	1	0	2263	1
Bin	(18)	0	1	663	1
Bin	(18)	1	0	2264	1
Bin	(17)	0	1	634	1
Bin	(17)	1	0	2235	1
Bin	(16)	0	1	600	1
Bin	(16)	1	0	2201	1
Bin	(15)	0	1	629	1
Bin	(15)	1	0	2230	1
Bin	(14)	0	1	625	1
Bin	(14)	1	0	2226	1
Bin	(13)	0	1	619	1
Bin	(13)	1	0	2220	1
Bin	(12)	0	1	633	1
Bin	(12)	1	0	2234	1
Bin	(11)	0	1	609	1
Bin	(11)	1	0	2210	1
Bin	(10)	0	1	624	1
Bin	(10)	1	0	2225	1
Bin	(9)	0	1	625	1
Bin	(9)	1	0	2226	1
Bin	(8)	0	1	614	1
Bin	(8)	1	0	2215	1
Bin	(7)	0	1	648	1
Bin	(7)	1	0	2249	1
Bin	(6)	0	1	646	1
Bin	(6)	1	0	2247	1
Bin	(5)	0	1	644	1
Bin	(5)	1	0	2245	1
Bin	(4)	0	1	608	1
Bin	(4)	1	0	2209	1
Bin	(3)	0	1	641	1
Bin	(3)	1	0	2242	1
Bin	(2)	0	1	630	1
Bin	(2)	1	0	2231	1
Bin	(1)	0	1	642	1
Bin	(1)	1	0	2243	1
Bin	(0)	0	1	625	1
Bin	(0)	1	0	2226	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8196	1
Bin	(31)	1	0	9747	1
Bin	(30)	0	1	8279	1
Bin	(30)	1	0	9830	1
Bin	(29)	0	1	7965	1
Bin	(29)	1	0	9516	1
Bin	(28)	0	1	22115	1
Bin	(28)	1	0	23579	1
Bin	(27)	0	1	18547	1
Bin	(27)	1	0	20024	1
Bin	(26)	0	1	20808	1
Bin	(26)	1	0	22271	1
Bin	(25)	0	1	18728	1
Bin	(25)	1	0	20187	1
Bin	(24)	0	1	22083	1
Bin	(24)	1	0	23556	1
Bin	(23)	0	1	19176	1
Bin	(23)	1	0	20631	1
Bin	(22)	0	1	21513	1
Bin	(22)	1	0	22971	1
Bin	(21)	0	1	19521	1
Bin	(21)	1	0	20962	1
Bin	(20)	0	1	21310	1
Bin	(20)	1	0	22779	1
Bin	(19)	0	1	20038	1
Bin	(19)	1	0	21481	1
Bin	(18)	0	1	21634	1
Bin	(18)	1	0	23086	1
Bin	(17)	0	1	13269	1
Bin	(17)	1	0	14774	1
Bin	(16)	0	1	13435	1
Bin	(16)	1	0	14941	1
Bin	(15)	0	1	13227	1
Bin	(15)	1	0	14736	1
Bin	(14)	0	1	13738	1
Bin	(14)	1	0	15246	1
Bin	(13)	0	1	13395	1
Bin	(13)	1	0	14896	1
Bin	(12)	0	1	13849	1
Bin	(12)	1	0	15347	1
Bin	(11)	0	1	13820	1
Bin	(11)	1	0	15329	1
Bin	(10)	0	1	15348	1
Bin	(10)	1	0	16799	1
Bin	(9)	0	1	24174	1
Bin	(9)	1	0	25497	1
Bin	(8)	0	1	14700	1
Bin	(8)	1	0	16192	1
Bin	(7)	0	1	33045	1
Bin	(7)	1	0	34246	1
Bin	(6)	0	1	23230	1
Bin	(6)	1	0	24534	1
Bin	(5)	0	1	18006	1
Bin	(5)	1	0	19484	1
Bin	(4)	0	1	15787	1
Bin	(4)	1	0	17280	1
Bin	(3)	0	1	25683	1
Bin	(3)	1	0	27032	1
Bin	(2)	0	1	26512	1
Bin	(2)	1	0	27847	1
Bin	(1)	0	1	27253	1
Bin	(1)	1	0	28583	1
Bin	(0)	0	1	35110	1
Bin	(0)	1	0	36295	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1860	1
Bin	1	0	3461	1

Signal:

TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	328851	1
Bin	(4)	1	0	27167606	1
Bin	(3)	0	1	588370	1
Bin	(3)	1	0	26908043	1
Bin	(2)	0	1	446271	1
Bin	(2)	1	0	27050658	1
Bin	(1)	0	1	26727336	1
Bin	(1)	1	0	770541	1
Bin	(0)	0	1	17569607	1
Bin	(0)	1	0	9930160	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	163158	1
Bin	1	0	164925	1

Signal:

TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	68855	1
Bin	(31)	1	0	1019765	1
Bin	(30)	0	1	72603	1
Bin	(30)	1	0	1016019	1
Bin	(29)	0	1	72676	1
Bin	(29)	1	0	1015974	1
Bin	(28)	0	1	98447	1
Bin	(28)	1	0	990231	1
Bin	(27)	0	1	89687	1
Bin	(27)	1	0	999007	1
Bin	(26)	0	1	87606	1
Bin	(26)	1	0	1001066	1
Bin	(25)	0	1	92525	1
Bin	(25)	1	0	996129	1
Bin	(24)	0	1	85455	1
Bin	(24)	1	0	1003221	1
Bin	(23)	0	1	77722	1
Bin	(23)	1	0	1010968	1
Bin	(22)	0	1	112028	1
Bin	(22)	1	0	976644	1
Bin	(21)	0	1	77477	1
Bin	(21)	1	0	1011221	1
Bin	(20)	0	1	86829	1
Bin	(20)	1	0	1001877	1
Bin	(19)	0	1	114674	1
Bin	(19)	1	0	974038	1
Bin	(18)	0	1	129748	1
Bin	(18)	1	0	958982	1
Bin	(17)	0	1	118025	1
Bin	(17)	1	0	970731	1
Bin	(16)	0	1	191619	1
Bin	(16)	1	0	897079	1
Bin	(15)	0	1	78298	1
Bin	(15)	1	0	1010388	1
Bin	(14)	0	1	93570	1
Bin	(14)	1	0	995114	1
Bin	(13)	0	1	82656	1
Bin	(13)	1	0	1006016	1
Bin	(12)	0	1	85641	1
Bin	(12)	1	0	1003041	1
Bin	(11)	0	1	104973	1
Bin	(11)	1	0	983689	1
Bin	(10)	0	1	126455	1
Bin	(10)	1	0	962241	1
Bin	(9)	0	1	181078	1
Bin	(9)	1	0	907614	1
Bin	(8)	0	1	157182	1
Bin	(8)	1	0	931496	1
Bin	(7)	0	1	133124	1
Bin	(7)	1	0	955584	1
Bin	(6)	0	1	114992	1
Bin	(6)	1	0	973722	1
Bin	(5)	0	1	108428	1
Bin	(5)	1	0	980288	1
Bin	(4)	0	1	166504	1
Bin	(4)	1	0	922150	1
Bin	(3)	0	1	141775	1
Bin	(3)	1	0	946926	1
Bin	(2)	0	1	166354	1
Bin	(2)	1	0	922355	1
Bin	(1)	0	1	233558	1
Bin	(1)	1	0	855184	1
Bin	(0)	0	1	194672	1
Bin	(0)	1	0	894164	1

Signal:

TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	27449	1
Bin	(4)	1	0	29050	1
Bin	(3)	0	1	3988	1
Bin	(3)	1	0	5589	1
Bin	(2)	0	1	47095	1
Bin	(2)	1	0	48696	1
Bin	(1)	0	1	39202	1
Bin	(1)	1	0	39206	1
Bin	(0)	0	1	104340	1
Bin	(0)	1	0	105937	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8196	1
Bin	(31)	1	0	9747	1
Bin	(30)	0	1	8279	1
Bin	(30)	1	0	9830	1
Bin	(29)	0	1	7965	1
Bin	(29)	1	0	9516	1
Bin	(28)	0	1	22115	1
Bin	(28)	1	0	23579	1
Bin	(27)	0	1	18547	1
Bin	(27)	1	0	20024	1
Bin	(26)	0	1	20808	1
Bin	(26)	1	0	22271	1
Bin	(25)	0	1	18728	1
Bin	(25)	1	0	20187	1
Bin	(24)	0	1	22083	1
Bin	(24)	1	0	23556	1
Bin	(23)	0	1	19176	1
Bin	(23)	1	0	20631	1
Bin	(22)	0	1	21513	1
Bin	(22)	1	0	22971	1
Bin	(21)	0	1	19521	1
Bin	(21)	1	0	20962	1
Bin	(20)	0	1	21310	1
Bin	(20)	1	0	22779	1
Bin	(19)	0	1	20038	1
Bin	(19)	1	0	21481	1
Bin	(18)	0	1	21634	1
Bin	(18)	1	0	23086	1
Bin	(17)	0	1	13269	1
Bin	(17)	1	0	14774	1
Bin	(16)	0	1	13435	1
Bin	(16)	1	0	14941	1
Bin	(15)	0	1	13227	1
Bin	(15)	1	0	14736	1
Bin	(14)	0	1	13738	1
Bin	(14)	1	0	15246	1
Bin	(13)	0	1	13395	1
Bin	(13)	1	0	14896	1
Bin	(12)	0	1	13849	1
Bin	(12)	1	0	15347	1
Bin	(11)	0	1	13820	1
Bin	(11)	1	0	15329	1
Bin	(10)	0	1	15348	1
Bin	(10)	1	0	16799	1
Bin	(9)	0	1	24174	1
Bin	(9)	1	0	25497	1
Bin	(8)	0	1	14700	1
Bin	(8)	1	0	16192	1
Bin	(7)	0	1	33045	1
Bin	(7)	1	0	34246	1
Bin	(6)	0	1	23230	1
Bin	(6)	1	0	24534	1
Bin	(5)	0	1	18006	1
Bin	(5)	1	0	19484	1
Bin	(4)	0	1	15787	1
Bin	(4)	1	0	17280	1
Bin	(3)	0	1	25683	1
Bin	(3)	1	0	27032	1
Bin	(2)	0	1	26512	1
Bin	(2)	1	0	27847	1
Bin	(1)	0	1	27253	1
Bin	(1)	1	0	28583	1
Bin	(0)	0	1	35110	1
Bin	(0)	1	0	36295	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	319	1
Bin	1	0	1920	1

Signal:

PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	164	1
Bin	(20)	1	0	8996	1
Bin	(19)	0	1	13	1
Bin	(19)	1	0	9147	1
Bin	(18)	0	1	21	1
Bin	(18)	1	0	9139	1
Bin	(17)	0	1	369	1
Bin	(17)	1	0	8791	1
Bin	(16)	0	1	50	1
Bin	(16)	1	0	9110	1
Bin	(15)	0	1	108	1
Bin	(15)	1	0	9052	1
Bin	(14)	0	1	105	1
Bin	(14)	1	0	9055	1
Bin	(13)	0	1	423	1
Bin	(13)	1	0	8737	1
Bin	(12)	0	1	473	1
Bin	(12)	1	0	8687	1
Bin	(11)	0	1	454	1
Bin	(11)	1	0	8706	1
Bin	(10)	0	1	425	1
Bin	(10)	1	0	8735	1
Bin	(9)	0	1	364	1
Bin	(9)	1	0	8796	1
Bin	(8)	0	1	775	1
Bin	(8)	1	0	8385	1
Bin	(7)	0	1	649	1
Bin	(7)	1	0	8511	1
Bin	(6)	0	1	812	1
Bin	(6)	1	0	8348	1
Bin	(5)	0	1	1440	1
Bin	(5)	1	0	7720	1
Bin	(4)	0	1	2488	1
Bin	(4)	1	0	6672	1
Bin	(3)	0	1	4512	1
Bin	(3)	1	0	4648	1
Bin	(2)	0	1	5449	1
Bin	(2)	1	0	3711	1
Bin	(1)	0	1	3346	1
Bin	(1)	1	0	5814	1
Bin	(0)	0	1	3567	1
Bin	(0)	1	0	5593	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	13253	1
Bin	1	0	13702	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	16844	1
Bin	1	0	18444	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_even.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

If statement on lines 277 to 280:

Signal assignment statement on line 277:

Signal assignment statement on line 280:

If statement on lines 283 to 285:

Signal assignment statement on line 283:

Signal assignment statement on line 285:

If statement on lines 287 to 289:

Signal assignment statement on line 287:

Signal assignment statement on line 289:

If statement on lines 291 to 293:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 296 to 298:

Signal assignment statement on line 296:

Signal assignment statement on line 298:

If statement on lines 300 to 302:

Signal assignment statement on line 300:

Signal assignment statement on line 302:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 277 to 278:

"if" / "when" / "else" condition on line 283:

"if" / "when" / "else" condition on line 287:

"if" / "when" / "else" condition on line 291:

"if" / "when" / "else" condition on line 296:

"if" / "when" / "else" condition on line 300:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

"and" expression on lines 277 to 278:

Covered expressions:

"and" expression on lines 277 to 278:

"=" expression on line 277:

"=" expression on line 283:

"=" expression on line 287:

"=" expression on line 291:

"=" expression on line 296:

"=" expression on line 300:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage: