NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_FSM_INST	100.0 % (79/79)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (410/410)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready)) 
178:                          else 
179:                      '0';

Count: 910
Threshold: 1

Signal assignment statement:

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or
Count: 449
Threshold: 1

Signal assignment statement:

179: '0';
Count: 461
Threshold: 1

If statement:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED) 
184:                        else 
185:                    '0';

Count: 1933
Threshold: 1

Signal assignment statement:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

Count: 776
Threshold: 1

Signal assignment statement:

185: '0';
Count: 1157
Threshold: 1

If statement:

187:    txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1') 
188:                                 else 
189:                     (others => '0');

Count: 12473
Threshold: 1

Signal assignment statement:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')
Count: 857
Threshold: 1

Signal assignment statement:

189: (others => '0');
Count: 11616
Threshold: 1

If statement:

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
192:                   '0';

Count: 416
Threshold: 1

Signal assignment statement:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else
Count: 43
Threshold: 1

Signal assignment statement:

192: '0';
Count: 373
Threshold: 1

Signal assignment statement:

203: next_state <= curr_state;
Count: 4280
Threshold: 1

Sequential statement:

205:        case curr_state is 
206: 
...
360: 
361:        end case;

Count: 4280
Threshold: 1

If statement:

213:            if (tx_command_txcr_valid = '1') then 
214:                next_state <= s_txt_ready; 
215:            end if;

Count: 2036
Threshold: 1

Signal assignment statement:

214: next_state <= s_txt_ready;
Count: 96
Threshold: 1

If statement:

223:            if (go_to_failed = '1') then 
224:                next_state <= s_txt_failed; 
...
242:                next_state <= s_txt_aborted; 
243:            end if;

Count: 864
Threshold: 1

Signal assignment statement:

224: next_state <= s_txt_failed;
Count: 11
Threshold: 1

Signal assignment statement:

228: next_state <= s_txt_parity_err;
Count: 40
Threshold: 1

If statement:

234:                if (abort_applied = '1') then 
235:                    next_state <= s_txt_ab_prog; 
236:                else 
237:                    next_state <= s_txt_tx_prog; 
238:                end if;

Count: 196
Threshold: 1

Signal assignment statement:

235: next_state <= s_txt_ab_prog;
Count: 1
Threshold: 1

Signal assignment statement:

237: next_state <= s_txt_tx_prog;
Count: 195
Threshold: 1

Signal assignment statement:

242: next_state <= s_txt_aborted;
Count: 35
Threshold: 1

If statement:

251:            if (go_to_failed = '1') then 
252:                next_state <= s_txt_failed; 
...
276:                next_state <= s_txt_ab_prog; 
277:            end if;

Count: 700
Threshold: 1

Signal assignment statement:

252: next_state <= s_txt_failed;
Count: 2
Threshold: 1

Signal assignment statement:

256: next_state <= s_txt_parity_err;
Count: 37
Threshold: 1

Signal assignment statement:

260: next_state <= s_txt_failed;
Count: 40
Threshold: 1

Signal assignment statement:

264: next_state <= s_txt_ok;
Count: 98
Threshold: 1

If statement:

268:                if (abort_applied = '1') then 
269:                    next_state <= s_txt_aborted; 
270:                else 
271:                    next_state <= s_txt_ready; 
272:                end if;

Count: 38
Threshold: 1

Signal assignment statement:

269: next_state <= s_txt_aborted;
Count: 1
Threshold: 1

Signal assignment statement:

271: next_state <= s_txt_ready;
Count: 37
Threshold: 1

Signal assignment statement:

276: next_state <= s_txt_ab_prog;
Count: 26
Threshold: 1

If statement:

285:            if (go_to_failed = '1') then 
286:                next_state <= s_txt_failed; 
...
302:                next_state <= s_txt_aborted; 
303:            end if;

Count: 56
Threshold: 1

Signal assignment statement:

286: next_state <= s_txt_failed;
Count: 1
Threshold: 1

Signal assignment statement:

290: next_state <= s_txt_parity_err;
Count: 1
Threshold: 1

Signal assignment statement:

294: next_state <= s_txt_failed;
Count: 5
Threshold: 1

Signal assignment statement:

298: next_state <= s_txt_ok;
Count: 3
Threshold: 1

Signal assignment statement:

302: next_state <= s_txt_aborted;
Count: 4
Threshold: 1

If statement:

311:            if (tx_command_txcr_valid = '1') then 
312:                next_state <= s_txt_ready; 
...
316:                next_state <= s_txt_empty; 
317:            end if;

Count: 139
Threshold: 1

Signal assignment statement:

312: next_state <= s_txt_ready;
Count: 25
Threshold: 1

Signal assignment statement:

316: next_state <= s_txt_empty;
Count: 5
Threshold: 1

If statement:

325:            if (tx_command_txcr_valid = '1') then 
326:                next_state <= s_txt_ready; 
...
330:                next_state <= s_txt_empty; 
331:            end if;

Count: 151
Threshold: 1

Signal assignment statement:

326: next_state <= s_txt_ready;
Count: 34
Threshold: 1

Signal assignment statement:

330: next_state <= s_txt_empty;
Count: 1
Threshold: 1

If statement:

339:            if (tx_command_txcr_valid = '1') then 
340:                next_state <= s_txt_ready; 
...
344:                next_state <= s_txt_empty; 
345:            end if;

Count: 286
Threshold: 1

Signal assignment statement:

340: next_state <= s_txt_ready;
Count: 60
Threshold: 1

Signal assignment statement:

344: next_state <= s_txt_empty;
Count: 13
Threshold: 1

If statement:

353:            if (tx_command_txcr_valid = '1') then 
354:                next_state <= s_txt_ready; 
...
358:                next_state <= s_txt_empty; 
359:            end if;

Count: 48
Threshold: 1

Signal assignment statement:

354: next_state <= s_txt_ready;
Count: 6
Threshold: 1

Signal assignment statement:

358: next_state <= s_txt_empty;
Count: 3
Threshold: 1

If statement:

368:    txt_fsm_ce <= '1' when (next_state /= curr_state) else 
369:                  '0';

Count: 1830
Threshold: 1

Signal assignment statement:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else
Count: 833
Threshold: 1

Signal assignment statement:

369: '0';
Count: 997
Threshold: 1

If statement:

376:        if (res_n = '0') then 
377:            curr_state <= s_txt_empty; 
...
381:            end if; 
382:        end if;

Count: 35370646
Threshold: 1

Signal assignment statement:

377: curr_state <= s_txt_empty;
Count: 760516
Threshold: 1

If statement:

379:            if (txt_fsm_ce = '1') then 
380:                curr_state <= next_state; 
381:            end if;

Count: 17304621
Threshold: 1

Signal assignment statement:

380: curr_state <= next_state;
Count: 674
Threshold: 1

If statement:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog)) 
392:                                  else 
393:                            '1';

Count: 910
Threshold: 1

Signal assignment statement:

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or
Count: 449
Threshold: 1

Signal assignment statement:

393: '1';
Count: 461
Threshold: 1

If statement:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
...
406:                           else 
407:                       '0';

Count: 4304
Threshold: 1

Signal assignment statement:

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely
Count: 599
Threshold: 1

Signal assignment statement:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

Count: 16
Threshold: 1

Signal assignment statement:

407: '0';
Count: 3689
Threshold: 1

If statement:

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
412:                            else 
413:                        '0';

Count: 1167
Threshold: 1

Signal assignment statement:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))
Count: 241
Threshold: 1

Signal assignment statement:

413: '0';
Count: 926
Threshold: 1

Sequential statement:

416:    with curr_state select txtb_state <= 
417:        TXT_RDY   when s_txt_ready, 
...
423:        TXT_ETY   when s_txt_empty, 
424:        TXT_PER   when s_txt_parity_err;

Count: 910
Threshold: 1

Signal assignment statement:

417: TXT_RDY when s_txt_ready,
Count: 241
Threshold: 1

Signal assignment statement:

418: TXT_TRAN when s_txt_tx_prog,
Count: 195
Threshold: 1

Signal assignment statement:

419: TXT_ABTP when s_txt_ab_prog,
Count: 13
Threshold: 1

Signal assignment statement:

420: TXT_TOK when s_txt_ok,
Count: 101
Threshold: 1

Signal assignment statement:

421: TXT_ERR when s_txt_failed,
Count: 55
Threshold: 1

Signal assignment statement:

422: TXT_ABT when s_txt_aborted,
Count: 39
Threshold: 1

Signal assignment statement:

423: TXT_ETY when s_txt_empty,
Count: 257
Threshold: 1

Signal assignment statement:

424: TXT_PER when s_txt_parity_err;
Count: 9
Threshold: 1

If statement:

432:    txtb_unmask_data_ram <= '1' when (transient_state = '1') 
433:                                else 
434:                            '0';

Count: 738
Threshold: 1

Signal assignment statement:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')
Count: 204
Threshold: 1

Signal assignment statement:

434: '0';
Count: 534
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	True	449	1
Bin	False	461	1

"if" / "when" / "else" condition:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	776	1
Bin	False	1157	1

"if" / "when" / "else" condition:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	True	857	1
Bin	False	11616	1

"if" / "when" / "else" condition:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	True	43	1
Bin	False	373	1

"case" / "with" / "select" choice:

210: when s_txt_empty =>

	Choice of	Count	Threshold
Bin	`s_txt_empty`	2036	1

"if" / "when" / "else" condition:

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	96	1
Bin	False	1940	1

"case" / "with" / "select" choice:

220: when s_txt_ready =>

	Choice of	Count	Threshold
Bin	`s_txt_ready`	864	1

"if" / "when" / "else" condition:

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	11	1
Bin	False	853	1

"if" / "when" / "else" condition:

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	40	1
Bin	False	813	1

"if" / "when" / "else" condition:

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	196	1
Bin	False	617	1

"if" / "when" / "else" condition:

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	195	1

"if" / "when" / "else" condition:

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	True	35	1
Bin	False	582	1

"case" / "with" / "select" choice:

248: when s_txt_tx_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	700	1

"if" / "when" / "else" condition:

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	698	1

"if" / "when" / "else" condition:

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	37	1
Bin	False	661	1

"if" / "when" / "else" condition:

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	40	1
Bin	False	621	1

"if" / "when" / "else" condition:

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	98	1
Bin	False	523	1

"if" / "when" / "else" condition:

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	38	1
Bin	False	485	1

"if" / "when" / "else" condition:

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	37	1

"if" / "when" / "else" condition:

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	26	1
Bin	False	459	1

"case" / "with" / "select" choice:

282: when s_txt_ab_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	56	1

"if" / "when" / "else" condition:

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	55	1

"if" / "when" / "else" condition:

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	54	1

"if" / "when" / "else" condition:

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	49	1

"if" / "when" / "else" condition:

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	3	1
Bin	False	46	1

"if" / "when" / "else" condition:

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	42	1

"case" / "with" / "select" choice:

308: when s_txt_failed =>

	Choice of	Count	Threshold
Bin	`s_txt_failed`	139	1

"if" / "when" / "else" condition:

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	25	1
Bin	False	114	1

"if" / "when" / "else" condition:

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	109	1

"case" / "with" / "select" choice:

322: when s_txt_aborted =>

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	151	1

"if" / "when" / "else" condition:

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	34	1
Bin	False	117	1

"if" / "when" / "else" condition:

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	116	1

"case" / "with" / "select" choice:

336: when s_txt_ok =>

	Choice of	Count	Threshold
Bin	`s_txt_ok`	286	1

"if" / "when" / "else" condition:

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	60	1
Bin	False	226	1

"if" / "when" / "else" condition:

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	13	1
Bin	False	213	1

"case" / "with" / "select" choice:

350: when s_txt_parity_err =>

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	48	1

"if" / "when" / "else" condition:

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	6	1
Bin	False	42	1

"if" / "when" / "else" condition:

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	3	1
Bin	False	39	1

"if" / "when" / "else" condition:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	True	833	1
Bin	False	997	1

"if" / "when" / "else" condition:

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	760516	1
Bin	False	34610130	1

"if" / "when" / "else" condition:

378: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	17304621	1
Bin	False	17305509	1

"if" / "when" / "else" condition:

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	674	1
Bin	False	17303947	1

"if" / "when" / "else" condition:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	True	449	1
Bin	False	461	1

"if" / "when" / "else" condition:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	True	599	1
Bin	False	3705	1

"if" / "when" / "else" condition:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	16	1
Bin	False	3689	1

"if" / "when" / "else" condition:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	True	241	1
Bin	False	926	1

"case" / "with" / "select" choice:

417: TXT_RDY when s_txt_ready,

	Choice of	Count	Threshold
Bin	`s_txt_ready`	241	1

"case" / "with" / "select" choice:

418: TXT_TRAN when s_txt_tx_prog,

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	195	1

"case" / "with" / "select" choice:

419: TXT_ABTP when s_txt_ab_prog,

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	13	1

"case" / "with" / "select" choice:

420: TXT_TOK when s_txt_ok,

	Choice of	Count	Threshold
Bin	`s_txt_ok`	101	1

"case" / "with" / "select" choice:

421: TXT_ERR when s_txt_failed,

	Choice of	Count	Threshold
Bin	`s_txt_failed`	55	1

"case" / "with" / "select" choice:

422: TXT_ABT when s_txt_aborted,

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	39	1

"case" / "with" / "select" choice:

423: TXT_ETY when s_txt_empty,

	Choice of	Count	Threshold
Bin	`s_txt_empty`	257	1

"case" / "with" / "select" choice:

424: TXT_PER when s_txt_parity_err;

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	9	1

"if" / "when" / "else" condition:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	204	1
Bin	False	534	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	17684435	1
Bin	1	0	17684600	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	723	1
Bin	1	0	723	1

Port:

MR_MODE_BMM

	From	To	Count	Threshold
Bin	0	1	3	1
Bin	1	0	168	1

Port:

MR_MODE_ROM

	From	To	Count	Threshold
Bin	0	1	8	1
Bin	1	0	173	1

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold
Bin	0	1	199	1
Bin	1	0	34	1

Port:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	188	1

Port:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	221	1
Bin	1	0	386	1

Port:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Port:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	214	1

Port:

TXTB_HW_CMD.LOCK

	From	To	Count	Threshold
Bin	0	1	2959	1
Bin	1	0	3124	1

Port:

TXTB_HW_CMD.VALID

	From	To	Count	Threshold
Bin	0	1	1153	1
Bin	1	0	1318	1

Port:

TXTB_HW_CMD.ERR

	From	To	Count	Threshold
Bin	0	1	403	1
Bin	1	0	568	1

Port:

TXTB_HW_CMD.ARBL

	From	To	Count	Threshold
Bin	0	1	17	1
Bin	1	0	182	1

Port:

TXTB_HW_CMD.FAILED

	From	To	Count	Threshold
Bin	0	1	1384	1
Bin	1	0	1549	1

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	238	1

Port:

IS_BUS_OFF

	From	To	Count	Threshold
Bin	0	1	758	1
Bin	1	0	758	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	250	1

Port:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	369	1
Bin	1	0	204	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	369	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	165	1
Bin	1	0	330	1

Port:

TXTB_STATE(3)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	98	1

Port:

TXTB_STATE(2)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	360	1

Port:

TXTB_STATE(1)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	404	1

Port:

TXTB_STATE(0)

	From	To	Count	Threshold
Bin	0	1	221	1
Bin	1	0	386	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	241	1
Bin	1	0	406	1

Port:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	369	1

Signal:

TXT_FSM_CE

	From	To	Count	Threshold
Bin	0	1	832	1
Bin	1	0	997	1

Signal:

GO_TO_FAILED

	From	To	Count	Threshold
Bin	0	1	751	1
Bin	1	0	751	1

Signal:

TRANSIENT_STATE

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	369	1

Port:

TXTB_HW_CMD_I.LOCK

	From	To	Count	Threshold
Bin	0	1	196	1
Bin	1	0	361	1

Port:

TXTB_HW_CMD_I.VALID

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	266	1

Port:

TXTB_HW_CMD_I.ERR

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	207	1

Port:

TXTB_HW_CMD_I.ARBL

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	166	1

Port:

TXTB_HW_CMD_I.FAILED

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	217	1

Signal:

ARBL_OR_ERR

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	208	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or

	Evaluated to	Count	Threshold
Bin	False	897	1
Bin	True	13	1

"=" expression

176: (curr_state = s_txt_tx_prog) or

	Evaluated to	Count	Threshold
Bin	False	715	1
Bin	True	195	1

"or" expression

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or

	LHS	RHS	Count	Threshold
Bin	False	False	702	1
Bin	False	True	195	1
Bin	True	False	13	1

"=" expression

177: (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	False	669	1
Bin	True	241	1

"or" expression

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	LHS	RHS	Count	Threshold
Bin	False	False	461	1
Bin	False	True	241	1
Bin	True	False	208	1

"=" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

	Evaluated to	Count	Threshold
Bin	False	964	1
Bin	True	969	1

"=" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

	Evaluated to	Count	Threshold
Bin	False	579	1
Bin	True	1354	1

"and" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
                                   <-----LHS------>     <----------------------RHS---------------------->

	LHS	RHS	Count	Threshold
Bin	False	True	594	1
Bin	True	False	209	1
Bin	True	True	760	1

"=" expression

182: mr_mode_bmm = BMM_ENABLED or

	Evaluated to	Count	Threshold
Bin	False	1923	1
Bin	True	10	1

"or" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or

	LHS	RHS	Count	Threshold
Bin	False	False	1165	1
Bin	False	True	8	1
Bin	True	False	758	1

"=" expression

183: mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	False	1918	1
Bin	True	15	1

"or" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	LHS	RHS	Count	Threshold
Bin	False	False	1157	1
Bin	False	True	8	1
Bin	True	False	761	1

"=" expression

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	False	11616	1
Bin	True	857	1

"=" expression

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	False	374	1
Bin	True	42	1

"=" expression

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	False	415	1
Bin	True	1	1

"or" expression

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
                                 <---------LHS--------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	373	1
Bin	False	True	1	1
Bin	True	False	42	1

"=" expression

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	1940	1
Bin	True	96	1

"=" expression

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	853	1
Bin	True	11	1

"=" expression

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	813	1
Bin	True	40	1

"=" expression

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	617	1
Bin	True	196	1

"=" expression

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	195	1
Bin	True	1	1

"=" expression

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	False	582	1
Bin	True	35	1

"=" expression

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	698	1
Bin	True	2	1

"=" expression

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	661	1
Bin	True	37	1

"=" expression

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	621	1
Bin	True	40	1

"=" expression

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	523	1
Bin	True	98	1

"=" expression

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	False	485	1
Bin	True	38	1

"=" expression

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	37	1
Bin	True	1	1

"=" expression

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	459	1
Bin	True	26	1

"=" expression

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	55	1
Bin	True	1	1

"=" expression

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	54	1
Bin	True	1	1

"=" expression

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	49	1
Bin	True	5	1

"=" expression

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	46	1
Bin	True	3	1

"=" expression

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	False	42	1
Bin	True	4	1

"=" expression

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	114	1
Bin	True	25	1

"=" expression

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	109	1
Bin	True	5	1

"=" expression

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	117	1
Bin	True	34	1

"=" expression

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	116	1
Bin	True	1	1

"=" expression

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	226	1
Bin	True	60	1

"=" expression

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	213	1
Bin	True	13	1

"=" expression

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	42	1
Bin	True	6	1

"=" expression

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	39	1
Bin	True	3	1

"/=" expression

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	False	997	1
Bin	True	833	1

"=" expression

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	34610130	1
Bin	True	760516	1

"=" expression

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	17303947	1
Bin	True	674	1

"=" expression

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or

	Evaluated to	Count	Threshold
Bin	False	669	1
Bin	True	241	1

"=" expression

390: (curr_state = s_txt_tx_prog) or

	Evaluated to	Count	Threshold
Bin	False	715	1
Bin	True	195	1

"or" expression

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or

	LHS	RHS	Count	Threshold
Bin	False	False	474	1
Bin	False	True	195	1
Bin	True	False	241	1

"=" expression

391: (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	False	897	1
Bin	True	13	1

"or" expression

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	LHS	RHS	Count	Threshold
Bin	False	False	461	1
Bin	False	True	13	1
Bin	True	False	436	1

"=" expression

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely

	Evaluated to	Count	Threshold
Bin	False	4117	1
Bin	True	187	1

"=" expression

397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK

	Evaluated to	Count	Threshold
Bin	False	3900	1
Bin	True	404	1

"or" expression

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK

	LHS	RHS	Count	Threshold
Bin	False	False	3713	1
Bin	False	True	404	1
Bin	True	False	187	1

"=" expression

398: ((txtb_hw_cmd_i.arbl = '1' or

	Evaluated to	Count	Threshold
Bin	False	4300	1
Bin	True	4	1

"=" expression

399: txtb_hw_cmd_i.err = '1') and

	Evaluated to	Count	Threshold
Bin	False	4173	1
Bin	True	131	1

"or" expression

398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and

	LHS	RHS	Count	Threshold
Bin	False	False	4169	1
Bin	False	True	131	1
Bin	True	False	4	1

"=" expression

400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	False	4266	1
Bin	True	38	1

"and" expression

398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	LHS	RHS	Count	Threshold
Bin	False	True	30	1
Bin	True	False	127	1
Bin	True	True	8	1

"or" expression

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	LHS	RHS	Count	Threshold
Bin	False	False	3705	1
Bin	False	True	8	1
Bin	True	False	591	1

"=" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

	Evaluated to	Count	Threshold
Bin	False	2901	1
Bin	True	804	1

"=" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

	Evaluated to	Count	Threshold
Bin	False	3599	1
Bin	True	106	1

"and" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
                                     <-----LHS------>     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	70	1
Bin	True	False	768	1
Bin	True	True	36	1

"=" expression

405: transient_state = '1')

	Evaluated to	Count	Threshold
Bin	False	2679	1
Bin	True	1026	1

"and" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	1010	1
Bin	True	False	20	1
Bin	True	True	16	1

"=" expression

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	False	894	1
Bin	True	273	1

"=" expression

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	False	256	1
Bin	True	911	1

"and" expression

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
                                       <---------LHS---------->       <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	670	1
Bin	True	False	32	1
Bin	True	True	241	1

"=" expression

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	False	534	1
Bin	True	204	1

	State	Count	Threshold
Bin	S_TXT_EMPTY	262	1
Bin	S_TXT_READY	296	1
Bin	S_TXT_TX_PROG	226	1
Bin	S_TXT_AB_PROG	14	1
Bin	S_TXT_OK	112	1
Bin	S_TXT_FAILED	57	1
Bin	S_TXT_ABORTED	40	1
Bin	S_TXT_PARITY_ERR	78	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_fsm.vhd

Sub-instances:

Current Instance:

Details:

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Uncovered statements:

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Covered statements:

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