NVC code coverage report

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_FSM_INST	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 175 to 179:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready)) 
178:                          else 
179:                      '0';

Count: 876
Threshold: 1

Signal assignment statement on line 175:

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or
Count: 431
Threshold: 1

Signal assignment statement on line 179:

179: '0';
Count: 445
Threshold: 1

If statement on lines 181 to 185:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED) 
184:                        else 
185:                    '0';

Count: 1933
Threshold: 1

Signal assignment statement on line 181:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

Count: 776
Threshold: 1

Signal assignment statement on line 185:

185: '0';
Count: 1157
Threshold: 1

If statement on lines 187 to 189:

187:    txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1') 
188:                                 else 
189:                     (others => '0');

Count: 12779
Threshold: 1

Signal assignment statement on line 187:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')
Count: 816
Threshold: 1

Signal assignment statement on line 189:

189: (others => '0');
Count: 11963
Threshold: 1

If statement on lines 191 to 192:

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
192:                   '0';

Count: 438
Threshold: 1

Signal assignment statement on line 191:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else
Count: 54
Threshold: 1

Signal assignment statement on line 192:

192: '0';
Count: 384
Threshold: 1

Signal assignment statement on line 194:

194: txtb_allow_bb <= transient_state;
Count: 706
Threshold: 1

Signal assignment statement on line 203:

203: next_state <= curr_state;
Count: 4182
Threshold: 1

Sequential statement on lines 205 to 361:

205:        case curr_state is 
206: 
...
360: 
361:        end case;

Count: 4182
Threshold: 1

If statement on lines 213 to 215:

213:            if (tx_command_txcr_valid = '1') then 
214:                next_state <= s_txt_ready; 
215:            end if;

Count: 2036
Threshold: 1

Signal assignment statement on line 214:

214: next_state <= s_txt_ready;
Count: 96
Threshold: 1

If statement on lines 223 to 243:

223:            if (go_to_failed = '1') then 
224:                next_state <= s_txt_failed; 
...
242:                next_state <= s_txt_aborted; 
243:            end if;

Count: 858
Threshold: 1

Signal assignment statement on line 224:

224: next_state <= s_txt_failed;
Count: 11
Threshold: 1

Signal assignment statement on line 228:

228: next_state <= s_txt_parity_err;
Count: 47
Threshold: 1

If statement on lines 234 to 238:

234:                if (abort_applied = '1') then 
235:                    next_state <= s_txt_ab_prog; 
236:                else 
237:                    next_state <= s_txt_tx_prog; 
238:                end if;

Count: 186
Threshold: 1

Signal assignment statement on line 235:

235: next_state <= s_txt_ab_prog;
Count: 1
Threshold: 1

Signal assignment statement on line 237:

237: next_state <= s_txt_tx_prog;
Count: 185
Threshold: 1

Signal assignment statement on line 242:

242: next_state <= s_txt_aborted;
Count: 35
Threshold: 1

If statement on lines 251 to 277:

251:            if (go_to_failed = '1') then 
252:                next_state <= s_txt_failed; 
...
276:                next_state <= s_txt_ab_prog; 
277:            end if;

Count: 648
Threshold: 1

Signal assignment statement on line 252:

252: next_state <= s_txt_failed;
Count: 2
Threshold: 1

Signal assignment statement on line 256:

256: next_state <= s_txt_parity_err;
Count: 22
Threshold: 1

Signal assignment statement on line 260:

260: next_state <= s_txt_failed;
Count: 24
Threshold: 1

Signal assignment statement on line 264:

264: next_state <= s_txt_ok;
Count: 96
Threshold: 1

If statement on lines 268 to 272:

268:                if (abort_applied = '1') then 
269:                    next_state <= s_txt_aborted; 
270:                else 
271:                    next_state <= s_txt_ready; 
272:                end if;

Count: 46
Threshold: 1

Signal assignment statement on line 269:

269: next_state <= s_txt_aborted;
Count: 1
Threshold: 1

Signal assignment statement on line 271:

271: next_state <= s_txt_ready;
Count: 45
Threshold: 1

Signal assignment statement on line 276:

276: next_state <= s_txt_ab_prog;
Count: 26
Threshold: 1

If statement on lines 285 to 303:

285:            if (go_to_failed = '1') then 
286:                next_state <= s_txt_failed; 
...
302:                next_state <= s_txt_aborted; 
303:            end if;

Count: 59
Threshold: 1

Signal assignment statement on line 286:

286: next_state <= s_txt_failed;
Count: 1
Threshold: 1

Signal assignment statement on line 290:

290: next_state <= s_txt_parity_err;
Count: 1
Threshold: 1

Signal assignment statement on line 294:

294: next_state <= s_txt_failed;
Count: 2
Threshold: 1

Signal assignment statement on line 298:

298: next_state <= s_txt_ok;
Count: 3
Threshold: 1

Signal assignment statement on line 302:

302: next_state <= s_txt_aborted;
Count: 7
Threshold: 1

If statement on lines 311 to 317:

311:            if (tx_command_txcr_valid = '1') then 
312:                next_state <= s_txt_ready; 
...
316:                next_state <= s_txt_empty; 
317:            end if;

Count: 83
Threshold: 1

Signal assignment statement on line 312:

312: next_state <= s_txt_ready;
Count: 7
Threshold: 1

Signal assignment statement on line 316:

316: next_state <= s_txt_empty;
Count: 5
Threshold: 1

If statement on lines 325 to 331:

325:            if (tx_command_txcr_valid = '1') then 
326:                next_state <= s_txt_ready; 
...
330:                next_state <= s_txt_empty; 
331:            end if;

Count: 163
Threshold: 1

Signal assignment statement on line 326:

326: next_state <= s_txt_ready;
Count: 37
Threshold: 1

Signal assignment statement on line 330:

330: next_state <= s_txt_empty;
Count: 1
Threshold: 1

If statement on lines 339 to 345:

339:            if (tx_command_txcr_valid = '1') then 
340:                next_state <= s_txt_ready; 
...
344:                next_state <= s_txt_empty; 
345:            end if;

Count: 280
Threshold: 1

Signal assignment statement on line 340:

340: next_state <= s_txt_ready;
Count: 58
Threshold: 1

Signal assignment statement on line 344:

344: next_state <= s_txt_empty;
Count: 13
Threshold: 1

If statement on lines 353 to 359:

353:            if (tx_command_txcr_valid = '1') then 
354:                next_state <= s_txt_ready; 
...
358:                next_state <= s_txt_empty; 
359:            end if;

Count: 55
Threshold: 1

Signal assignment statement on line 354:

354: next_state <= s_txt_ready;
Count: 8
Threshold: 1

Signal assignment statement on line 358:

358: next_state <= s_txt_empty;
Count: 3
Threshold: 1

If statement on lines 368 to 369:

368:    txt_fsm_ce <= '1' when (next_state /= curr_state) else 
369:                  '0';

Count: 1744
Threshold: 1

Signal assignment statement on line 368:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else
Count: 790
Threshold: 1

Signal assignment statement on line 369:

369: '0';
Count: 954
Threshold: 1

If statement on lines 376 to 382:

376:        if (res_n = '0') then 
377:            curr_state <= s_txt_empty; 
...
381:            end if; 
382:        end if;

Count: 35169394
Threshold: 1

Signal assignment statement on line 377:

377: curr_state <= s_txt_empty;
Count: 760504
Threshold: 1

If statement on lines 379 to 381:

379:            if (txt_fsm_ce = '1') then 
380:                curr_state <= next_state; 
381:            end if;

Count: 17204001
Threshold: 1

Signal assignment statement on line 380:

380: curr_state <= next_state;
Count: 640
Threshold: 1

If statement on lines 389 to 393:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog)) 
392:                                  else 
393:                            '1';

Count: 876
Threshold: 1

Signal assignment statement on line 389:

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or
Count: 431
Threshold: 1

Signal assignment statement on line 393:

393: '1';
Count: 445
Threshold: 1

If statement on lines 396 to 407:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
...
406:                           else 
407:                       '0';

Count: 4166
Threshold: 1

Signal assignment statement on line 396:

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely
Count: 521
Threshold: 1

Signal assignment statement on line 404:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

Count: 16
Threshold: 1

Signal assignment statement on line 407:

407: '0';
Count: 3629
Threshold: 1

If statement on lines 411 to 413:

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
412:                            else 
413:                        '0';

Count: 1133
Threshold: 1

Signal assignment statement on line 411:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))
Count: 233
Threshold: 1

Signal assignment statement on line 413:

413: '0';
Count: 900
Threshold: 1

Sequential statement on lines 416 to 424:

416:    with curr_state select txtb_state <= 
417:        TXT_RDY   when s_txt_ready, 
...
423:        TXT_ETY   when s_txt_empty, 
424:        TXT_PER   when s_txt_parity_err;

Count: 876
Threshold: 1

Signal assignment statement on line 417:

417: TXT_RDY when s_txt_ready,
Count: 233
Threshold: 1

Signal assignment statement on line 418:

418: TXT_TRAN when s_txt_tx_prog,
Count: 185
Threshold: 1

Signal assignment statement on line 419:

419: TXT_ABTP when s_txt_ab_prog,
Count: 13
Threshold: 1

Signal assignment statement on line 420:

420: TXT_TOK when s_txt_ok,
Count: 99
Threshold: 1

Signal assignment statement on line 421:

421: TXT_ERR when s_txt_failed,
Count: 36
Threshold: 1

Signal assignment statement on line 422:

422: TXT_ABT when s_txt_aborted,
Count: 42
Threshold: 1

Signal assignment statement on line 423:

423: TXT_ETY when s_txt_empty,
Count: 257
Threshold: 1

Signal assignment statement on line 424:

424: TXT_PER when s_txt_parity_err;
Count: 11
Threshold: 1

If statement on lines 432 to 434:

432:    txtb_unmask_data_ram <= '1' when (transient_state = '1') 
433:                                else 
434:                            '0';

Count: 706
Threshold: 1

Signal assignment statement on line 432:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')
Count: 188
Threshold: 1

Signal assignment statement on line 434:

434: '0';
Count: 518
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 175 to 177:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	True	431	1
Bin	False	445	1

"if" / "when" / "else" condition on lines 181 to 183:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	776	1
Bin	False	1157	1

"if" / "when" / "else" condition on line 187:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	True	816	1
Bin	False	11963	1

"if" / "when" / "else" condition on line 191:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	True	54	1
Bin	False	384	1

"case" / "with" / "select" choice on line 210:

210: when s_txt_empty =>

	Choice of	Count	Threshold
Bin	`s_txt_empty`	2036	1

"if" / "when" / "else" condition on line 213:

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	96	1
Bin	False	1940	1

"case" / "with" / "select" choice on line 220:

220: when s_txt_ready =>

	Choice of	Count	Threshold
Bin	`s_txt_ready`	858	1

"if" / "when" / "else" condition on line 223:

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	11	1
Bin	False	847	1

"if" / "when" / "else" condition on line 227:

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	47	1
Bin	False	800	1

"if" / "when" / "else" condition on line 231:

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	186	1
Bin	False	614	1

"if" / "when" / "else" condition on line 234:

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	185	1

"if" / "when" / "else" condition on line 241:

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	True	35	1
Bin	False	579	1

"case" / "with" / "select" choice on line 248:

248: when s_txt_tx_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	648	1

"if" / "when" / "else" condition on line 251:

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	646	1

"if" / "when" / "else" condition on line 255:

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	22	1
Bin	False	624	1

"if" / "when" / "else" condition on line 259:

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	24	1
Bin	False	600	1

"if" / "when" / "else" condition on line 263:

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	96	1
Bin	False	504	1

"if" / "when" / "else" condition on line 267:

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	46	1
Bin	False	458	1

"if" / "when" / "else" condition on line 268:

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	45	1

"if" / "when" / "else" condition on line 275:

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	26	1
Bin	False	432	1

"case" / "with" / "select" choice on line 282:

282: when s_txt_ab_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	59	1

"if" / "when" / "else" condition on line 285:

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	58	1

"if" / "when" / "else" condition on line 289:

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	57	1

"if" / "when" / "else" condition on line 293:

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	55	1

"if" / "when" / "else" condition on line 297:

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	3	1
Bin	False	52	1

"if" / "when" / "else" condition on line 301:

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	7	1
Bin	False	45	1

"case" / "with" / "select" choice on line 308:

308: when s_txt_failed =>

	Choice of	Count	Threshold
Bin	`s_txt_failed`	83	1

"if" / "when" / "else" condition on line 311:

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	7	1
Bin	False	76	1

"if" / "when" / "else" condition on line 315:

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	71	1

"case" / "with" / "select" choice on line 322:

322: when s_txt_aborted =>

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	163	1

"if" / "when" / "else" condition on line 325:

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	37	1
Bin	False	126	1

"if" / "when" / "else" condition on line 329:

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	1	1
Bin	False	125	1

"case" / "with" / "select" choice on line 336:

336: when s_txt_ok =>

	Choice of	Count	Threshold
Bin	`s_txt_ok`	280	1

"if" / "when" / "else" condition on line 339:

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	58	1
Bin	False	222	1

"if" / "when" / "else" condition on line 343:

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	13	1
Bin	False	209	1

"case" / "with" / "select" choice on line 350:

350: when s_txt_parity_err =>

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	55	1

"if" / "when" / "else" condition on line 353:

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	8	1
Bin	False	47	1

"if" / "when" / "else" condition on line 357:

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	3	1
Bin	False	44	1

"if" / "when" / "else" condition on line 368:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	True	790	1
Bin	False	954	1

"if" / "when" / "else" condition on line 376:

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	760504	1
Bin	False	34408890	1

"if" / "when" / "else" condition on line 378:

378: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	17204001	1
Bin	False	17204889	1

"if" / "when" / "else" condition on line 379:

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	640	1
Bin	False	17203361	1

"if" / "when" / "else" condition on lines 389 to 391:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	True	431	1
Bin	False	445	1

"if" / "when" / "else" condition on lines 396 to 400:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	True	521	1
Bin	False	3645	1

"if" / "when" / "else" condition on lines 404 to 405:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	16	1
Bin	False	3629	1

"if" / "when" / "else" condition on line 411:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	True	233	1
Bin	False	900	1

"case" / "with" / "select" choice on line 417:

417: TXT_RDY when s_txt_ready,

	Choice of	Count	Threshold
Bin	`s_txt_ready`	233	1

"case" / "with" / "select" choice on line 418:

418: TXT_TRAN when s_txt_tx_prog,

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	185	1

"case" / "with" / "select" choice on line 419:

419: TXT_ABTP when s_txt_ab_prog,

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	13	1

"case" / "with" / "select" choice on line 420:

420: TXT_TOK when s_txt_ok,

	Choice of	Count	Threshold
Bin	`s_txt_ok`	99	1

"case" / "with" / "select" choice on line 421:

421: TXT_ERR when s_txt_failed,

	Choice of	Count	Threshold
Bin	`s_txt_failed`	36	1

"case" / "with" / "select" choice on line 422:

422: TXT_ABT when s_txt_aborted,

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	42	1

"case" / "with" / "select" choice on line 423:

423: TXT_ETY when s_txt_empty,

	Choice of	Count	Threshold
Bin	`s_txt_empty`	257	1

"case" / "with" / "select" choice on line 424:

424: TXT_PER when s_txt_parity_err;

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	11	1

"if" / "when" / "else" condition on line 432:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	188	1
Bin	False	518	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ABORT_APPLIED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ABORT_OR_SKIPPED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	3036	1
Bin	LOCK	1	0	3201	1
Bin	VALID	0	1	1158	1
Bin	VALID	1	0	1323	1
Bin	ERR	0	1	442	1
Bin	ERR	1	0	607	1
Bin	ARBL	0	1	17	1
Bin	ARBL	1	0	182	1
Bin	FAILED	0	1	1417	1
Bin	FAILED	1	0	1582	1

Port:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	353	1
Bin	1	0	188	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	353	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	147	1
Bin	1	0	312	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	264	1
Bin	(3)	1	0	99	1
Bin	(2)	0	1	177	1
Bin	(2)	1	0	342	1
Bin	(1)	0	1	229	1
Bin	(1)	1	0	394	1
Bin	(0)	0	1	209	1
Bin	(0)	1	0	374	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	398	1

Port:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	353	1

Signal:

TXT_FSM_CE

	From	To	Count	Threshold
Bin	0	1	789	1
Bin	1	0	954	1

Signal:

GO_TO_FAILED

	From	To	Count	Threshold
Bin	0	1	751	1
Bin	1	0	751	1

Signal:

TRANSIENT_STATE

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	353	1

Signal:

TXTB_HW_CMD_I

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	186	1
Bin	LOCK	1	0	351	1
Bin	VALID	0	1	99	1
Bin	VALID	1	0	264	1
Bin	ERR	0	1	53	1
Bin	ERR	1	0	218	1
Bin	ARBL	0	1	1	1
Bin	ARBL	1	0	166	1
Bin	FAILED	0	1	33	1
Bin	FAILED	1	0	198	1

Signal:

ARBL_OR_ERR

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	219	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on lines 175 to 177:

 (curr_state = s_txt_ab_prog) or (curr_state = s_txt_tx_prog) or (curr_state = s_txt_ready) 
 <---------------------------LHS---------------------------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	445	1
Bin	False	True	233	1
Bin	True	False	198	1

"or" expression on lines 175 to 176:

 (curr_state = s_txt_ab_prog) or (curr_state = s_txt_tx_prog) 
  <----------LHS----------->      <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	678	1
Bin	False	True	185	1
Bin	True	False	13	1

"=" expression on line 175:

curr_state = s_txt_ab_prog

	Evaluated to	Count	Threshold
Bin	False	863	1
Bin	True	13	1

"=" expression on line 176:

curr_state = s_txt_tx_prog

	Evaluated to	Count	Threshold
Bin	False	691	1
Bin	True	185	1

"=" expression on line 177:

curr_state = s_txt_ready

	Evaluated to	Count	Threshold
Bin	False	643	1
Bin	True	233	1

"or" expression on lines 181 to 183:

 (is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or mr_mode_bmm = BMM_ENABLED or mr_mode_rom = ROM_ENABLED 
 <------------------------------------------------LHS------------------------------------------------>    <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	1157	1
Bin	False	True	8	1
Bin	True	False	761	1

"or" expression on lines 181 to 182:

 (is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or mr_mode_bmm = BMM_ENABLED 
  <--------------------------------LHS--------------------------------->     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	1165	1
Bin	False	True	8	1
Bin	True	False	758	1

"and" expression on line 181:

 is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED 
 <-----LHS------>     <----------------------RHS---------------------->

	LHS	RHS	Count	Threshold
Bin	False	True	594	1
Bin	True	False	209	1
Bin	True	True	760	1

"=" expression on line 181:

is_bus_off = '1'

	Evaluated to	Count	Threshold
Bin	False	964	1
Bin	True	969	1

"=" expression on line 181:

mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED

	Evaluated to	Count	Threshold
Bin	False	579	1
Bin	True	1354	1

"=" expression on line 182:

mr_mode_bmm = BMM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	1923	1
Bin	True	10	1

"=" expression on line 183:

mr_mode_rom = ROM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	1918	1
Bin	True	15	1

"=" expression on line 187:

txtb_hw_cmd_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	11963	1
Bin	True	816	1

"or" expression on line 191:

 txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1' 
 <---------LHS--------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	384	1
Bin	False	True	1	1
Bin	True	False	53	1

"=" expression on line 191:

txtb_hw_cmd_i.err = '1'

	Evaluated to	Count	Threshold
Bin	False	385	1
Bin	True	53	1

"=" expression on line 191:

txtb_hw_cmd_i.arbl = '1'

	Evaluated to	Count	Threshold
Bin	False	437	1
Bin	True	1	1

"=" expression on line 213:

tx_command_txcr_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	1940	1
Bin	True	96	1

"=" expression on line 223:

go_to_failed = '1'

	Evaluated to	Count	Threshold
Bin	False	847	1
Bin	True	11	1

"=" expression on line 227:

txtb_parity_error_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	800	1
Bin	True	47	1

"=" expression on line 231:

txtb_hw_cmd_i.lock = '1'

	Evaluated to	Count	Threshold
Bin	False	614	1
Bin	True	186	1

"=" expression on line 234:

abort_applied = '1'

	Evaluated to	Count	Threshold
Bin	False	185	1
Bin	True	1	1

"=" expression on line 241:

abort_or_skipped = '1'

	Evaluated to	Count	Threshold
Bin	False	579	1
Bin	True	35	1

"=" expression on line 251:

go_to_failed = '1'

	Evaluated to	Count	Threshold
Bin	False	646	1
Bin	True	2	1

"=" expression on line 255:

txtb_parity_error_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	624	1
Bin	True	22	1

"=" expression on line 259:

txtb_hw_cmd_i.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	600	1
Bin	True	24	1

"=" expression on line 263:

txtb_hw_cmd_i.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	504	1
Bin	True	96	1

"=" expression on line 267:

arbl_or_err = '1'

	Evaluated to	Count	Threshold
Bin	False	458	1
Bin	True	46	1

"=" expression on line 268:

abort_applied = '1'

	Evaluated to	Count	Threshold
Bin	False	45	1
Bin	True	1	1

"=" expression on line 275:

abort_applied = '1'

	Evaluated to	Count	Threshold
Bin	False	432	1
Bin	True	26	1

"=" expression on line 285:

go_to_failed = '1'

	Evaluated to	Count	Threshold
Bin	False	58	1
Bin	True	1	1

"=" expression on line 289:

txtb_parity_error_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	57	1
Bin	True	1	1

"=" expression on line 293:

txtb_hw_cmd_i.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	55	1
Bin	True	2	1

"=" expression on line 297:

txtb_hw_cmd_i.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	52	1
Bin	True	3	1

"=" expression on line 301:

arbl_or_err = '1'

	Evaluated to	Count	Threshold
Bin	False	45	1
Bin	True	7	1

"=" expression on line 311:

tx_command_txcr_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	76	1
Bin	True	7	1

"=" expression on line 315:

tx_command_txce_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	71	1
Bin	True	5	1

"=" expression on line 325:

tx_command_txcr_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	126	1
Bin	True	37	1

"=" expression on line 329:

tx_command_txce_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	125	1
Bin	True	1	1

"=" expression on line 339:

tx_command_txcr_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	222	1
Bin	True	58	1

"=" expression on line 343:

tx_command_txce_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	209	1
Bin	True	13	1

"=" expression on line 353:

tx_command_txcr_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	47	1
Bin	True	8	1

"=" expression on line 357:

tx_command_txce_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	44	1
Bin	True	3	1

"/=" expression on line 368:

next_state /= curr_state

	Evaluated to	Count	Threshold
Bin	False	954	1
Bin	True	790	1

"=" expression on line 376:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	34408890	1
Bin	True	760504	1

"=" expression on line 379:

txt_fsm_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	17203361	1
Bin	True	640	1

"or" expression on lines 389 to 391:

 (curr_state = s_txt_ready) or (curr_state = s_txt_tx_prog) or (curr_state = s_txt_ab_prog) 
 <--------------------------LHS--------------------------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	445	1
Bin	False	True	13	1
Bin	True	False	418	1

"or" expression on lines 389 to 390:

 (curr_state = s_txt_ready) or (curr_state = s_txt_tx_prog) 
  <---------LHS---------->      <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	458	1
Bin	False	True	185	1
Bin	True	False	233	1

"=" expression on line 389:

curr_state = s_txt_ready

	Evaluated to	Count	Threshold
Bin	False	643	1
Bin	True	233	1

"=" expression on line 390:

curr_state = s_txt_tx_prog

	Evaluated to	Count	Threshold
Bin	False	691	1
Bin	True	185	1

"=" expression on line 391:

curr_state = s_txt_ab_prog

	Evaluated to	Count	Threshold
Bin	False	863	1
Bin	True	13	1

"or" expression on lines 396 to 400:

 (txtb_hw_cmd_i.failed = '1') or (txtb_hw_cmd_i.valid = '1') or ((txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.err = '1') and (curr_state = s_txt_ab_prog)) 
 <---------------------------LHS--------------------------->     <----------------------------------------RHS----------------------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	3645	1
Bin	False	True	14	1
Bin	True	False	507	1

"or" expression on lines 396 to 397:

 (txtb_hw_cmd_i.failed = '1') or (txtb_hw_cmd_i.valid = '1') 
  <----------LHS----------->      <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	3659	1
Bin	False	True	396	1
Bin	True	False	111	1

"=" expression on line 396:

txtb_hw_cmd_i.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	4055	1
Bin	True	111	1

"=" expression on line 397:

txtb_hw_cmd_i.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	3770	1
Bin	True	396	1

"and" expression on lines 398 to 400:

 (txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.err = '1') and (curr_state = s_txt_ab_prog) 
  <-----------------------LHS----------------------->       <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	24	1
Bin	True	False	157	1
Bin	True	True	14	1

"or" expression on lines 398 to 399:

 txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.err = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	3995	1
Bin	False	True	167	1
Bin	True	False	4	1

"=" expression on line 398:

txtb_hw_cmd_i.arbl = '1'

	Evaluated to	Count	Threshold
Bin	False	4162	1
Bin	True	4	1

"=" expression on line 399:

txtb_hw_cmd_i.err = '1'

	Evaluated to	Count	Threshold
Bin	False	3999	1
Bin	True	167	1

"=" expression on line 400:

curr_state = s_txt_ab_prog

	Evaluated to	Count	Threshold
Bin	False	4128	1
Bin	True	38	1

"and" expression on lines 404 to 405:

 is_bus_off = '1' and next_state = s_txt_failed and transient_state = '1' 
 <--------------------LHS--------------------->     <--------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	993	1
Bin	True	False	20	1
Bin	True	True	16	1

"and" expression on line 404:

 is_bus_off = '1' and next_state = s_txt_failed 
 <-----LHS------>     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	50	1
Bin	True	False	768	1
Bin	True	True	36	1

"=" expression on line 404:

is_bus_off = '1'

	Evaluated to	Count	Threshold
Bin	False	2841	1
Bin	True	804	1

"=" expression on line 404:

next_state = s_txt_failed

	Evaluated to	Count	Threshold
Bin	False	3559	1
Bin	True	86	1

"=" expression on line 405:

transient_state = '1'

	Evaluated to	Count	Threshold
Bin	False	2636	1
Bin	True	1009	1

"and" expression on line 411:

 (curr_state = s_txt_ready) and (abort_applied = '0') 
  <---------LHS---------->       <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	644	1
Bin	True	False	32	1
Bin	True	True	233	1

"=" expression on line 411:

curr_state = s_txt_ready

	Evaluated to	Count	Threshold
Bin	False	868	1
Bin	True	265	1

"=" expression on line 411:

abort_applied = '0'

	Evaluated to	Count	Threshold
Bin	False	256	1
Bin	True	877	1

"=" expression on line 432:

transient_state = '1'

	Evaluated to	Count	Threshold
Bin	False	518	1
Bin	True	188	1

	State	Count	Threshold
Bin	S_TXT_EMPTY	262	1
Bin	S_TXT_READY	294	1
Bin	S_TXT_TX_PROG	201	1
Bin	S_TXT_AB_PROG	14	1
Bin	S_TXT_OK	110	1
Bin	S_TXT_FAILED	38	1
Bin	S_TXT_ABORTED	43	1
Bin	S_TXT_PARITY_ERR	71	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_odd.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 175 to 179:

Signal assignment statement on line 175:

Signal assignment statement on line 179:

If statement on lines 181 to 185:

Signal assignment statement on line 181:

Signal assignment statement on line 185:

If statement on lines 187 to 189:

Signal assignment statement on line 187:

Signal assignment statement on line 189:

If statement on lines 191 to 192:

Signal assignment statement on line 191:

Signal assignment statement on line 192:

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Sequential statement on lines 205 to 361:

If statement on lines 213 to 215:

Signal assignment statement on line 214:

If statement on lines 223 to 243:

Signal assignment statement on line 224:

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Signal assignment statement on line 235:

Signal assignment statement on line 237:

Signal assignment statement on line 242:

If statement on lines 251 to 277:

Signal assignment statement on line 252:

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Signal assignment statement on line 260:

Signal assignment statement on line 264:

If statement on lines 268 to 272:

Signal assignment statement on line 269:

Signal assignment statement on line 271:

Signal assignment statement on line 276:

If statement on lines 285 to 303:

Signal assignment statement on line 286:

Signal assignment statement on line 290:

Signal assignment statement on line 294:

Signal assignment statement on line 298:

Signal assignment statement on line 302:

If statement on lines 311 to 317:

Signal assignment statement on line 312:

Signal assignment statement on line 316:

If statement on lines 325 to 331:

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If statement on lines 339 to 345:

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If statement on lines 353 to 359:

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Signal assignment statement on line 368:

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Signal assignment statement on line 393:

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Signal assignment statement on line 396:

Signal assignment statement on line 404:

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If statement on lines 411 to 413:

Signal assignment statement on line 411:

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Sequential statement on lines 416 to 424:

Signal assignment statement on line 417:

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Signal assignment statement on line 419: