NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CLK_GATE_TXT_BUFFER_RAM_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (23/23)
TXT_BUFFER_RAM_INST	100.0 % (52/52)	100.0 % (38/38)	100.0 % (2160/2160)	93.1 % (54/58)	N.A.	N.A.	99.8 % (2304/2308)
TXT_BUFFER_FSM_INST	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CLK_GATE_TXT_BUFFER_RAM_COMP

100.0 % (3/3)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (23/23)

TXT_BUFFER_RAM_INST

100.0 % (52/52)

100.0 % (38/38)

100.0 % (2160/2160)

93.1 % (54/58)

N.A.

99.8 % (2304/2308)

TXT_BUFFER_FSM_INST

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST	100.0 % (38/38)	100.0 % (24/24)	100.0 % (468/468)	100.0 % (75/75)	N.A.	N.A.	100.0 % (605/605)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST

100.0 % (38/38)

100.0 % (24/24)

100.0 % (468/468)

100.0 % (75/75)

N.A.

100.0 % (605/605)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 255:

253:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
254:                             else 
255:                         '0';

Count: 22984
Threshold: 1

Signal assignment statement on line 253:

253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 11079
Threshold: 1

Signal assignment statement on line 255:

255: '0';
Count: 11905
Threshold: 1

If statement on lines 266 to 268:

266:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
267:                                                   else 
268:                                    (others => '0');

Count: 4170
Threshold: 1

Signal assignment statement on line 266:

266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 1485
Threshold: 1

Signal assignment statement on line 268:

268: (others => '0');
Count: 2685
Threshold: 1

If statement on lines 276 to 280:

276:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
277:                           else 
278:                       '1' when (mr_tst_control_tmaena = '1') 
279:                           else 
280:                       '0';

Count: 40918
Threshold: 1

Signal assignment statement on line 276:

276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 19889
Threshold: 1

Signal assignment statement on line 278:

278: '1' when (mr_tst_control_tmaena = '1')
Count: 240
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 20789
Threshold: 1

If statement on lines 287 to 291:

287:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
288:                                           txtb_parity_check_valid = '1' and 
289:                                           txtb_index_muxed = G_ID) 
290:                                     else 
291:                                 '0';

Count: 44717
Threshold: 1

Signal assignment statement on line 287:

287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 77
Threshold: 1

Signal assignment statement on line 291:

291: '0';
Count: 44640
Threshold: 1

Signal assignment statement on line 293:

293: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 484
Threshold: 1

If statement on lines 301 to 309:

301:        if (res_n = '0') then 
302:            mr_tx_command_txce_q <= '0'; 
...
308:            mr_tx_command_txca_q <= mr_tx_command_txca; 
309:        end if;

Count: 35169394
Threshold: 1

Signal assignment statement on line 302:

302: mr_tx_command_txce_q <= '0';
Count: 760504
Threshold: 1

Signal assignment statement on line 303:

303: mr_tx_command_txcr_q <= '0';
Count: 760504
Threshold: 1

Signal assignment statement on line 304:

304: mr_tx_command_txca_q <= '0';
Count: 760504
Threshold: 1

Signal assignment statement on line 306:

306: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 17204001
Threshold: 1

Signal assignment statement on line 307:

307: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 17204001
Threshold: 1

Signal assignment statement on line 308:

308: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 17204001
Threshold: 1

If statement on lines 312 to 314:

312:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
313:                                 else 
314:                             '0';

Count: 913
Threshold: 1

Signal assignment statement on line 312:

312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 23
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 890
Threshold: 1

If statement on lines 315 to 317:

315:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
316:                                 else 
317:                             '0';

Count: 6317
Threshold: 1

Signal assignment statement on line 315:

315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 206
Threshold: 1

Signal assignment statement on line 317:

317: '0';
Count: 6111
Threshold: 1

If statement on lines 319 to 321:

319:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
320:                         else 
321:                     '0';

Count: 1665
Threshold: 1

Signal assignment statement on line 319:

319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 46
Threshold: 1

Signal assignment statement on line 321:

321: '0';
Count: 1619
Threshold: 1

If statement on lines 323 to 326:

323:    buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and 
324:                                (txtb_is_bb = '1')) 
325:                        else 
326:                    '0';

Count: 5659
Threshold: 1

Signal assignment statement on line 323:

323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
Count: 3
Threshold: 1

Signal assignment statement on line 326:

326: '0';
Count: 5656
Threshold: 1

Signal assignment statement on line 328:

328: abort_or_skipped <= abort_applied or buffer_skipped;
Count: 428
Threshold: 1

If statement on lines 333 to 335:

333:    txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') 
334:                                else 
335:                            '0';

Count: 663
Threshold: 1

Signal assignment statement on line 333:

333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
Count: 22
Threshold: 1

Signal assignment statement on line 335:

335: '0';
Count: 641
Threshold: 1

Signal assignment statement on line 423:

423: txtb_parity_mismatch <= parity_mismatch;
Count: 1210
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	11079	1
Bin	False	11905	1

"if" / "when" / "else" condition on line 266:

266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	1485	1
Bin	False	2685	1

"if" / "when" / "else" condition on line 276:

276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	19889	1
Bin	False	21029	1

"if" / "when" / "else" condition on line 278:

278: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	240	1
Bin	False	20789	1

"if" / "when" / "else" condition on lines 287 to 289:

287:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
288:                                           txtb_parity_check_valid = '1' and 
289:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	77	1
Bin	False	44640	1

"if" / "when" / "else" condition on line 301:

301: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	760504	1
Bin	False	34408890	1

"if" / "when" / "else" condition on line 305:

305: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	17204001	1
Bin	False	17204889	1

"if" / "when" / "else" condition on line 312:

312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	23	1
Bin	False	890	1

"if" / "when" / "else" condition on line 315:

315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	206	1
Bin	False	6111	1

"if" / "when" / "else" condition on line 319:

319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	46	1
Bin	False	1619	1

"if" / "when" / "else" condition on lines 323 to 324:

323:    buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and 
324:                                (txtb_is_bb = '1'))

	Evaluated to	Count	Threshold
Bin	True	3	1
Bin	False	5656	1

"if" / "when" / "else" condition on line 333:

333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')

	Evaluated to	Count	Threshold
Bin	True	22	1
Bin	False	641	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_IS_BB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	121	1
Bin	(31)	1	0	286	1
Bin	(30)	0	1	116	1
Bin	(30)	1	0	281	1
Bin	(29)	0	1	115	1
Bin	(29)	1	0	280	1
Bin	(28)	0	1	122	1
Bin	(28)	1	0	287	1
Bin	(27)	0	1	124	1
Bin	(27)	1	0	289	1
Bin	(26)	0	1	117	1
Bin	(26)	1	0	282	1
Bin	(25)	0	1	123	1
Bin	(25)	1	0	288	1
Bin	(24)	0	1	120	1
Bin	(24)	1	0	285	1
Bin	(23)	0	1	131	1
Bin	(23)	1	0	296	1
Bin	(22)	0	1	126	1
Bin	(22)	1	0	291	1
Bin	(21)	0	1	128	1
Bin	(21)	1	0	293	1
Bin	(20)	0	1	123	1
Bin	(20)	1	0	288	1
Bin	(19)	0	1	112	1
Bin	(19)	1	0	277	1
Bin	(18)	0	1	128	1
Bin	(18)	1	0	293	1
Bin	(17)	0	1	128	1
Bin	(17)	1	0	293	1
Bin	(16)	0	1	113	1
Bin	(16)	1	0	278	1
Bin	(15)	0	1	122	1
Bin	(15)	1	0	287	1
Bin	(14)	0	1	122	1
Bin	(14)	1	0	287	1
Bin	(13)	0	1	124	1
Bin	(13)	1	0	289	1
Bin	(12)	0	1	122	1
Bin	(12)	1	0	287	1
Bin	(11)	0	1	123	1
Bin	(11)	1	0	288	1
Bin	(10)	0	1	121	1
Bin	(10)	1	0	286	1
Bin	(9)	0	1	118	1
Bin	(9)	1	0	283	1
Bin	(8)	0	1	110	1
Bin	(8)	1	0	275	1
Bin	(7)	0	1	122	1
Bin	(7)	1	0	287	1
Bin	(6)	0	1	117	1
Bin	(6)	1	0	282	1
Bin	(5)	0	1	123	1
Bin	(5)	1	0	288	1
Bin	(4)	0	1	127	1
Bin	(4)	1	0	292	1
Bin	(3)	0	1	124	1
Bin	(3)	1	0	289	1
Bin	(2)	0	1	121	1
Bin	(2)	1	0	286	1
Bin	(1)	0	1	121	1
Bin	(1)	1	0	286	1
Bin	(0)	0	1	126	1
Bin	(0)	1	0	291	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	264	1
Bin	(3)	1	0	99	1
Bin	(2)	0	1	177	1
Bin	(2)	1	0	342	1
Bin	(1)	0	1	229	1
Bin	(1)	1	0	394	1
Bin	(0)	0	1	209	1
Bin	(0)	1	0	374	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	147	1
Bin	1	0	312	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	3036	1
Bin	LOCK	1	0	3201	1
Bin	VALID	0	1	1158	1
Bin	VALID	1	0	1323	1
Bin	ERR	0	1	442	1
Bin	ERR	1	0	607	1
Bin	ARBL	0	1	17	1
Bin	ARBL	1	0	182	1
Bin	FAILED	0	1	1417	1
Bin	FAILED	1	0	1582	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	123	1
Bin	(31)	1	0	288	1
Bin	(30)	0	1	45	1
Bin	(30)	1	0	210	1
Bin	(29)	0	1	76	1
Bin	(29)	1	0	241	1
Bin	(28)	0	1	253	1
Bin	(28)	1	0	418	1
Bin	(27)	0	1	248	1
Bin	(27)	1	0	413	1
Bin	(26)	0	1	195	1
Bin	(26)	1	0	360	1
Bin	(25)	0	1	241	1
Bin	(25)	1	0	406	1
Bin	(24)	0	1	219	1
Bin	(24)	1	0	384	1
Bin	(23)	0	1	285	1
Bin	(23)	1	0	450	1
Bin	(22)	0	1	269	1
Bin	(22)	1	0	434	1
Bin	(21)	0	1	266	1
Bin	(21)	1	0	431	1
Bin	(20)	0	1	258	1
Bin	(20)	1	0	423	1
Bin	(19)	0	1	297	1
Bin	(19)	1	0	462	1
Bin	(18)	0	1	295	1
Bin	(18)	1	0	460	1
Bin	(17)	0	1	186	1
Bin	(17)	1	0	351	1
Bin	(16)	0	1	188	1
Bin	(16)	1	0	353	1
Bin	(15)	0	1	132	1
Bin	(15)	1	0	297	1
Bin	(14)	0	1	152	1
Bin	(14)	1	0	317	1
Bin	(13)	0	1	201	1
Bin	(13)	1	0	366	1
Bin	(12)	0	1	206	1
Bin	(12)	1	0	371	1
Bin	(11)	0	1	186	1
Bin	(11)	1	0	351	1
Bin	(10)	0	1	231	1
Bin	(10)	1	0	396	1
Bin	(9)	0	1	232	1
Bin	(9)	1	0	397	1
Bin	(8)	0	1	196	1
Bin	(8)	1	0	361	1
Bin	(7)	0	1	368	1
Bin	(7)	1	0	533	1
Bin	(6)	0	1	392	1
Bin	(6)	1	0	557	1
Bin	(5)	0	1	269	1
Bin	(5)	1	0	434	1
Bin	(4)	0	1	295	1
Bin	(4)	1	0	460	1
Bin	(3)	0	1	251	1
Bin	(3)	1	0	416	1
Bin	(2)	0	1	348	1
Bin	(2)	1	0	513	1
Bin	(1)	0	1	281	1
Bin	(1)	1	0	446	1
Bin	(0)	0	1	345	1
Bin	(0)	1	0	510	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	398	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	353	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	440	1
Bin	1	0	605	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	242	1

Port:

TXTB_BB_PARITY_ERROR

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	187	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	353	1
Bin	1	0	188	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	353	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	395	1
Bin	(31)	1	0	550	1
Bin	(30)	0	1	318	1
Bin	(30)	1	0	473	1
Bin	(29)	0	1	342	1
Bin	(29)	1	0	497	1
Bin	(28)	0	1	566	1
Bin	(28)	1	0	717	1
Bin	(27)	0	1	641	1
Bin	(27)	1	0	793	1
Bin	(26)	0	1	595	1
Bin	(26)	1	0	744	1
Bin	(25)	0	1	497	1
Bin	(25)	1	0	649	1
Bin	(24)	0	1	593	1
Bin	(24)	1	0	744	1
Bin	(23)	0	1	664	1
Bin	(23)	1	0	815	1
Bin	(22)	0	1	637	1
Bin	(22)	1	0	787	1
Bin	(21)	0	1	690	1
Bin	(21)	1	0	840	1
Bin	(20)	0	1	703	1
Bin	(20)	1	0	855	1
Bin	(19)	0	1	526	1
Bin	(19)	1	0	674	1
Bin	(18)	0	1	501	1
Bin	(18)	1	0	651	1
Bin	(17)	0	1	501	1
Bin	(17)	1	0	654	1
Bin	(16)	0	1	411	1
Bin	(16)	1	0	566	1
Bin	(15)	0	1	574	1
Bin	(15)	1	0	726	1
Bin	(14)	0	1	462	1
Bin	(14)	1	0	615	1
Bin	(13)	0	1	479	1
Bin	(13)	1	0	631	1
Bin	(12)	0	1	633	1
Bin	(12)	1	0	785	1
Bin	(11)	0	1	545	1
Bin	(11)	1	0	700	1
Bin	(10)	0	1	419	1
Bin	(10)	1	0	571	1
Bin	(9)	0	1	744	1
Bin	(9)	1	0	889	1
Bin	(8)	0	1	574	1
Bin	(8)	1	0	728	1
Bin	(7)	0	1	871	1
Bin	(7)	1	0	1014	1
Bin	(6)	0	1	898	1
Bin	(6)	1	0	1042	1
Bin	(5)	0	1	470	1
Bin	(5)	1	0	622	1
Bin	(4)	0	1	716	1
Bin	(4)	1	0	868	1
Bin	(3)	0	1	731	1
Bin	(3)	1	0	878	1
Bin	(2)	0	1	583	1
Bin	(2)	1	0	729	1
Bin	(1)	0	1	705	1
Bin	(1)	1	0	857	1
Bin	(0)	0	1	608	1
Bin	(0)	1	0	754	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	242	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	301	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	2838	1
Bin	1	0	3003	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	512	1
Bin	1	0	677	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	188	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	371	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Signal:

BUFFER_SKIPPED

	From	To	Count	Threshold
Bin	0	1	3	1
Bin	1	0	168	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	214	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	11079	1
Bin	1	0	11244	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	20129	1
Bin	1	0	20294	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	341276	1
Bin	1	0	341441	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	440	1
Bin	1	0	605	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 253:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	11432	1
Bin	True	False	60	1
Bin	True	True	11079	1

"=" expression on line 253:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	11845	1
Bin	True	11139	1

"=" expression on line 253:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	473	1
Bin	True	22511	1

"=" expression on line 266:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	2685	1
Bin	True	1485	1

"or" expression on line 276:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	21029	1
Bin	False	True	11079	1
Bin	True	False	8810	1

"=" expression on line 276:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	32108	1
Bin	True	8810	1

"=" expression on line 276:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	29839	1
Bin	True	11079	1

"=" expression on line 278:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	20789	1
Bin	True	240	1

"and" expression on lines 287 to 289:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	2863	1
Bin	True	False	999	1
Bin	True	True	77	1

"and" expression on lines 287 to 288:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	17814	1
Bin	True	False	1259	1
Bin	True	True	1076	1

"=" expression on line 287:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	42382	1
Bin	True	2335	1

"=" expression on line 288:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	25827	1
Bin	True	18890	1

"=" expression on line 289:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	41777	1
Bin	True	2940	1

"=" expression on line 301:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	34408890	1
Bin	True	760504	1

"and" expression on line 312:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	93	1
Bin	True	False	116	1
Bin	True	True	23	1

"=" expression on line 312:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	774	1
Bin	True	139	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	797	1
Bin	True	116	1

"and" expression on line 315:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	189	1
Bin	True	False	2722	1
Bin	True	True	206	1

"=" expression on line 315:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	3389	1
Bin	True	2928	1

"=" expression on line 315:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	5922	1
Bin	True	395	1

"and" expression on line 319:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	119	1
Bin	True	False	466	1
Bin	True	True	46	1

"=" expression on line 319:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	1153	1
Bin	True	512	1

"=" expression on line 319:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	1500	1
Bin	True	165	1

"and" expression on lines 323 to 324:

 (txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and (txtb_is_bb = '1') 
  <-----------------------LHS----------------------->       <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	10	1
Bin	True	False	2572	1
Bin	True	True	3	1

"or" expression on line 323:

 txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	3084	1
Bin	False	True	1158	1
Bin	True	False	1417	1

"=" expression on line 323:

txtb_hw_cmd.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	4242	1
Bin	True	1417	1

"=" expression on line 323:

txtb_hw_cmd.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	4501	1
Bin	True	1158	1

"=" expression on line 324:

txtb_is_bb = '1'

	Evaluated to	Count	Threshold
Bin	False	5646	1
Bin	True	13	1

"or" expression on line 328:

 abort_applied or buffer_skipped 
 <----LHS---->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	214	1
Bin	'0'	'1'	3	1
Bin	'1'	'0'	46	1

"and" expression on line 333:

 txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1' 
 <-------------LHS------------->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	29	1
Bin	True	False	55	1
Bin	True	True	22	1

"=" expression on line 333:

txtb_parity_error_valid_i = '1'

	Evaluated to	Count	Threshold
Bin	False	586	1
Bin	True	77	1

"=" expression on line 333:

mr_mode_txbbm = '1'

	Evaluated to	Count	Threshold
Bin	False	612	1
Bin	True	51	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 255:

Signal assignment statement on line 253:

Signal assignment statement on line 255:

If statement on lines 266 to 268:

Signal assignment statement on line 266:

Signal assignment statement on line 268:

If statement on lines 276 to 280:

Signal assignment statement on line 276:

Signal assignment statement on line 278:

Signal assignment statement on line 280:

If statement on lines 287 to 291:

Signal assignment statement on line 287:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 301 to 309:

Signal assignment statement on line 302:

Signal assignment statement on line 303:

Signal assignment statement on line 304:

Signal assignment statement on line 306:

Signal assignment statement on line 307:

Signal assignment statement on line 308:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

If statement on lines 315 to 317:

Signal assignment statement on line 315:

Signal assignment statement on line 317:

If statement on lines 319 to 321:

Signal assignment statement on line 319:

Signal assignment statement on line 321:

If statement on lines 323 to 326:

Signal assignment statement on line 323:

Signal assignment statement on line 326:

Signal assignment statement on line 328:

If statement on lines 333 to 335:

Signal assignment statement on line 333:

Signal assignment statement on line 335:

Signal assignment statement on line 423:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

"if" / "when" / "else" condition on line 266:

"if" / "when" / "else" condition on line 276:

"if" / "when" / "else" condition on line 278:

"if" / "when" / "else" condition on lines 287 to 289:

"if" / "when" / "else" condition on line 301:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 312:

"if" / "when" / "else" condition on line 315:

"if" / "when" / "else" condition on line 319:

"if" / "when" / "else" condition on lines 323 to 324:

"if" / "when" / "else" condition on line 333:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port: