NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CRC_CALC_15_INST	100.0 % (14/14)	100.0 % (14/14)	100.0 % (108/108)	100.0 % (21/21)	N.A.	N.A.	100.0 % (157/157)
CRC_CALC_17_RX_INST	100.0 % (14/14)	100.0 % (14/14)	100.0 % (120/120)	100.0 % (21/21)	N.A.	N.A.	100.0 % (169/169)
CRC_CALC_21_RX_INST	100.0 % (14/14)	100.0 % (14/14)	100.0 % (144/144)	100.0 % (21/21)	N.A.	N.A.	100.0 % (193/193)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST	100.0 % (26/26)	100.0 % (20/20)	100.0 % (152/152)	100.0 % (30/30)	N.A.	N.A.	100.0 % (228/228)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

210:    init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD) 
211:                            else 
212:                        '0';

Count: 3460
Threshold: 1

Signal assignment statement:

210: init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD)
Count: 1730
Threshold: 1

Signal assignment statement:

212: '0';
Count: 1730
Threshold: 1

If statement:

214:    init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD) 
215:                            else 
216:                        '0';

Count: 3460
Threshold: 1

Signal assignment statement:

214: init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD)
Count: 1730
Threshold: 1

Signal assignment statement:

216: '0';
Count: 1730
Threshold: 1

If statement:

222:    crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1') 
223:                                     else 
224:                         data_tx_wbs;

Count: 4232030
Threshold: 1

Signal assignment statement:

222: crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1')
Count: 2141452
Threshold: 1

Signal assignment statement:

224: data_tx_wbs;
Count: 2090578
Threshold: 1

If statement:

226:    crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1') 
227:                                     else 
228:                         trig_tx_wbs;

Count: 44131626
Threshold: 1

Signal assignment statement:

226: crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1')
Count: 31920014
Threshold: 1

Signal assignment statement:

228: trig_tx_wbs;
Count: 12211612
Threshold: 1

If statement:

234:    crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1') 
235:                                  else 
236:                      data_tx_nbs;

Count: 4236326
Threshold: 1

Signal assignment statement:

234: crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1')
Count: 2142464
Threshold: 1

Signal assignment statement:

236: data_tx_nbs;
Count: 2093862
Threshold: 1

If statement:

238:    crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1') 
239:                                  else 
240:                      trig_tx_nbs;

Count: 42179668
Threshold: 1

Signal assignment statement:

238: crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1')
Count: 30518508
Threshold: 1

Signal assignment statement:

240: trig_tx_nbs;
Count: 11661160
Threshold: 1

If statement:

249:    crc_ena_15   <= '1' when (crc_enable = '1') 
250:                        else 
251:                    '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT) 
252:                        else 
253:                    '0';

Count: 3080993
Threshold: 1

Signal assignment statement:

249: crc_ena_15 <= '1' when (crc_enable = '1')
Count: 2444006
Threshold: 1

Signal assignment statement:

251: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)
Count: 744
Threshold: 1

Signal assignment statement:

253: '0';
Count: 636243
Threshold: 1

If statement:

255:    crc_ena_17_21  <= '1' when (crc_enable = '1') 
256:                          else 
257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT) 
258:                          else 
259:                      '0';

Count: 3113826
Threshold: 1

Signal assignment statement:

255: crc_ena_17_21 <= '1' when (crc_enable = '1')
Count: 2429017
Threshold: 1

Signal assignment statement:

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)

Count: 36810
Threshold: 1

Signal assignment statement:

259: '0';
Count: 647999
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

210: init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD)

	Evaluated to	Count	Threshold
Bin	True	1730	1
Bin	False	1730	1

"if" / "when" / "else" condition:

214: init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD)

	Evaluated to	Count	Threshold
Bin	True	1730	1
Bin	False	1730	1

"if" / "when" / "else" condition:

222: crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	2141452	1
Bin	False	2090578	1

"if" / "when" / "else" condition:

226: crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	31920014	1
Bin	False	12211612	1

"if" / "when" / "else" condition:

234: crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	2142464	1
Bin	False	2093862	1

"if" / "when" / "else" condition:

238: crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	30518508	1
Bin	False	11661160	1

"if" / "when" / "else" condition:

249: crc_ena_15 <= '1' when (crc_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	2444006	1
Bin	False	636987	1

"if" / "when" / "else" condition:

251: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	True	744	1
Bin	False	636243	1

"if" / "when" / "else" condition:

255: crc_ena_17_21 <= '1' when (crc_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	2429017	1
Bin	False	684809	1

"if" / "when" / "else" condition:

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	True	36810	1
Bin	False	647999	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

MR_SETTINGS_NISOFD

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	1730	1

Port:

DATA_TX_WBS

	From	To	Count	Threshold
Bin	0	1	635351	1
Bin	1	0	633753	1

Port:

DATA_TX_NBS

	From	To	Count	Threshold
Bin	0	1	644444	1
Bin	1	0	642846	1

Port:

DATA_RX_WBS

	From	To	Count	Threshold
Bin	0	1	1396008	1
Bin	1	0	1397599	1

Port:

DATA_RX_NBS

	From	To	Count	Threshold
Bin	0	1	1391188	1
Bin	1	0	1389588	1

Port:

TRIG_TX_WBS

	From	To	Count	Threshold
Bin	0	1	11079571	1
Bin	1	0	11081170	1

Port:

TRIG_TX_NBS

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

TRIG_RX_WBS

	From	To	Count	Threshold
Bin	0	1	10955682	1
Bin	1	0	10957282	1

Port:

TRIG_RX_NBS

	From	To	Count	Threshold
Bin	0	1	10015414	1
Bin	1	0	10017014	1

Port:

CRC_ENABLE

	From	To	Count	Threshold
Bin	0	1	55285	1
Bin	1	0	56885	1

Port:

CRC_SPEC_ENABLE

	From	To	Count	Threshold
Bin	0	1	112536	1
Bin	1	0	114132	1

Port:

CRC_CALC_FROM_RX

	From	To	Count	Threshold
Bin	0	1	83068	1
Bin	1	0	84659	1

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold
Bin	0	1	112514	1
Bin	1	0	114114	1

Port:

CRC_15(14)

	From	To	Count	Threshold
Bin	0	1	1452642	1
Bin	1	0	1454241	1

Port:

CRC_15(13)

	From	To	Count	Threshold
Bin	0	1	1404381	1
Bin	1	0	1405979	1

Port:

CRC_15(12)

	From	To	Count	Threshold
Bin	0	1	1416815	1
Bin	1	0	1418414	1

Port:

CRC_15(11)

	From	To	Count	Threshold
Bin	0	1	1431040	1
Bin	1	0	1432636	1

Port:

CRC_15(10)

	From	To	Count	Threshold
Bin	0	1	1444591	1
Bin	1	0	1446189	1

Port:

CRC_15(9)

	From	To	Count	Threshold
Bin	0	1	1438246	1
Bin	1	0	1439842	1

Port:

CRC_15(8)

	From	To	Count	Threshold
Bin	0	1	1452223	1
Bin	1	0	1453819	1

Port:

CRC_15(7)

	From	To	Count	Threshold
Bin	0	1	1489085	1
Bin	1	0	1490683	1

Port:

CRC_15(6)

	From	To	Count	Threshold
Bin	0	1	1428572	1
Bin	1	0	1430168	1

Port:

CRC_15(5)

	From	To	Count	Threshold
Bin	0	1	1442138	1
Bin	1	0	1443734	1

Port:

CRC_15(4)

	From	To	Count	Threshold
Bin	0	1	1454104	1
Bin	1	0	1455703	1

Port:

CRC_15(3)

	From	To	Count	Threshold
Bin	0	1	1453743	1
Bin	1	0	1455342	1

Port:

CRC_15(2)

	From	To	Count	Threshold
Bin	0	1	1440570	1
Bin	1	0	1442165	1

Port:

CRC_15(1)

	From	To	Count	Threshold
Bin	0	1	1456437	1
Bin	1	0	1458034	1

Port:

CRC_15(0)

	From	To	Count	Threshold
Bin	0	1	1470076	1
Bin	1	0	1471674	1

Port:

CRC_17(16)

	From	To	Count	Threshold
Bin	0	1	1734039	1
Bin	1	0	1735633	1

Port:

CRC_17(15)

	From	To	Count	Threshold
Bin	0	1	1744508	1
Bin	1	0	1746106	1

Port:

CRC_17(14)

	From	To	Count	Threshold
Bin	0	1	1759054	1
Bin	1	0	1760651	1

Port:

CRC_17(13)

	From	To	Count	Threshold
Bin	0	1	1757156	1
Bin	1	0	1758753	1

Port:

CRC_17(12)

	From	To	Count	Threshold
Bin	0	1	1695908	1
Bin	1	0	1697506	1

Port:

CRC_17(11)

	From	To	Count	Threshold
Bin	0	1	1710517	1
Bin	1	0	1712115	1

Port:

CRC_17(10)

	From	To	Count	Threshold
Bin	0	1	1657718	1
Bin	1	0	1659317	1

Port:

CRC_17(9)

	From	To	Count	Threshold
Bin	0	1	1671362	1
Bin	1	0	1672959	1

Port:

CRC_17(8)

	From	To	Count	Threshold
Bin	0	1	1685982	1
Bin	1	0	1687581	1

Port:

CRC_17(7)

	From	To	Count	Threshold
Bin	0	1	1699437	1
Bin	1	0	1701036	1

Port:

CRC_17(6)

	From	To	Count	Threshold
Bin	0	1	1713617	1
Bin	1	0	1715217	1

Port:

CRC_17(5)

	From	To	Count	Threshold
Bin	0	1	1713382	1
Bin	1	0	1714978	1

Port:

CRC_17(4)

	From	To	Count	Threshold
Bin	0	1	1725540	1
Bin	1	0	1727138	1

Port:

CRC_17(3)

	From	To	Count	Threshold
Bin	0	1	1744070	1
Bin	1	0	1745668	1

Port:

CRC_17(2)

	From	To	Count	Threshold
Bin	0	1	1713985	1
Bin	1	0	1715584	1

Port:

CRC_17(1)

	From	To	Count	Threshold
Bin	0	1	1729286	1
Bin	1	0	1730885	1

Port:

CRC_17(0)

	From	To	Count	Threshold
Bin	0	1	1757719	1
Bin	1	0	1759317	1

Port:

CRC_21(20)

	From	To	Count	Threshold
Bin	0	1	1738348	1
Bin	1	0	1739941	1

Port:

CRC_21(19)

	From	To	Count	Threshold
Bin	0	1	1694492	1
Bin	1	0	1696089	1

Port:

CRC_21(18)

	From	To	Count	Threshold
Bin	0	1	1709182	1
Bin	1	0	1710780	1

Port:

CRC_21(17)

	From	To	Count	Threshold
Bin	0	1	1723668	1
Bin	1	0	1725266	1

Port:

CRC_21(16)

	From	To	Count	Threshold
Bin	0	1	1736428	1
Bin	1	0	1738027	1

Port:

CRC_21(15)

	From	To	Count	Threshold
Bin	0	1	1749537	1
Bin	1	0	1751135	1

Port:

CRC_21(14)

	From	To	Count	Threshold
Bin	0	1	1762507	1
Bin	1	0	1764105	1

Port:

CRC_21(13)

	From	To	Count	Threshold
Bin	0	1	1777446	1
Bin	1	0	1779044	1

Port:

CRC_21(12)

	From	To	Count	Threshold
Bin	0	1	1718146	1
Bin	1	0	1719743	1

Port:

CRC_21(11)

	From	To	Count	Threshold
Bin	0	1	1733293	1
Bin	1	0	1734892	1

Port:

CRC_21(10)

	From	To	Count	Threshold
Bin	0	1	1723964	1
Bin	1	0	1725560	1

Port:

CRC_21(9)

	From	To	Count	Threshold
Bin	0	1	1737663	1
Bin	1	0	1739261	1

Port:

CRC_21(8)

	From	To	Count	Threshold
Bin	0	1	1753350	1
Bin	1	0	1754945	1

Port:

CRC_21(7)

	From	To	Count	Threshold
Bin	0	1	1768568	1
Bin	1	0	1770168	1

Port:

CRC_21(6)

	From	To	Count	Threshold
Bin	0	1	1710305	1
Bin	1	0	1711902	1

Port:

CRC_21(5)

	From	To	Count	Threshold
Bin	0	1	1724000	1
Bin	1	0	1725597	1

Port:

CRC_21(4)

	From	To	Count	Threshold
Bin	0	1	1737131	1
Bin	1	0	1738729	1

Port:

CRC_21(3)

	From	To	Count	Threshold
Bin	0	1	1753239	1
Bin	1	0	1754837	1

Port:

CRC_21(2)

	From	To	Count	Threshold
Bin	0	1	1752204	1
Bin	1	0	1753800	1

Port:

CRC_21(1)

	From	To	Count	Threshold
Bin	0	1	1764851	1
Bin	1	0	1766449	1

Port:

CRC_21(0)

	From	To	Count	Threshold
Bin	0	1	1777838	1
Bin	1	0	1779434	1

Signal:

INIT_VECT_MSB_17

	From	To	Count	Threshold
Bin	0	1	1730	1
Bin	1	0	1730	1

Signal:

INIT_VECT_MSB_21

	From	To	Count	Threshold
Bin	0	1	1730	1
Bin	1	0	1730	1

Signal:

CRC_17_21_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1387496	1
Bin	1	0	1385896	1

Signal:

CRC_17_21_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11043148	1
Bin	1	0	11044748	1

Signal:

CRC_15_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1386117	1
Bin	1	0	1384517	1

Signal:

CRC_15_TRIGGER

	From	To	Count	Threshold
Bin	0	1	10305150	1
Bin	1	0	10306749	1

Signal:

CRC_ENA_15

	From	To	Count	Threshold
Bin	0	1	55285	1
Bin	1	0	56885	1

Signal:

CRC_ENA_17_21

	From	To	Count	Threshold
Bin	0	1	61272	1
Bin	1	0	62872	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

210: init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD)

	Evaluated to	Count	Threshold
Bin	False	1730	1
Bin	True	1730	1

"=" expression

214: init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD)

	Evaluated to	Count	Threshold
Bin	False	1730	1
Bin	True	1730	1

"=" expression

222: crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	False	2090578	1
Bin	True	2141452	1

"=" expression

226: crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	False	12211612	1
Bin	True	31920014	1

"=" expression

234: crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	False	2093862	1
Bin	True	2142464	1

"=" expression

238: crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	False	11661160	1
Bin	True	30518508	1

"=" expression

249: crc_ena_15 <= '1' when (crc_enable = '1')

	Evaluated to	Count	Threshold
Bin	False	636987	1
Bin	True	2444006	1

"=" expression

251: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	False	523707	1
Bin	True	113280	1

"=" expression

251: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	False	413546	1
Bin	True	223441	1

"and" expression

251:                    '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT) 
                                  <--------LHS-------->     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	222697	1
Bin	True	False	112536	1
Bin	True	True	744	1

"=" expression

255: crc_ena_17_21 <= '1' when (crc_enable = '1')

	Evaluated to	Count	Threshold
Bin	False	684809	1
Bin	True	2429017	1

"=" expression

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	False	535463	1
Bin	True	149346	1

"=" expression

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	False	420096	1
Bin	True	264713	1

"and" expression

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT) 
                                    <--------LHS-------->     <-----------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	227903	1
Bin	True	False	112536	1
Bin	True	True	36810	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

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Port:

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