NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CRC_CALC_15_INST	100.0 % (15/15)	100.0 % (14/14)	100.0 % (108/108)	100.0 % (21/21)	N.A.	N.A.	100.0 % (158/158)
CRC_CALC_17_RX_INST	100.0 % (15/15)	100.0 % (14/14)	100.0 % (120/120)	100.0 % (21/21)	N.A.	N.A.	100.0 % (170/170)
CRC_CALC_21_RX_INST	100.0 % (15/15)	100.0 % (14/14)	100.0 % (144/144)	100.0 % (21/21)	N.A.	N.A.	100.0 % (194/194)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CRC_CALC_15_INST

100.0 % (15/15)

100.0 % (14/14)

100.0 % (108/108)

100.0 % (21/21)

N.A.

100.0 % (158/158)

CRC_CALC_17_RX_INST

100.0 % (15/15)

100.0 % (14/14)

100.0 % (120/120)

100.0 % (21/21)

N.A.

100.0 % (170/170)

CRC_CALC_21_RX_INST

100.0 % (15/15)

100.0 % (14/14)

100.0 % (144/144)

100.0 % (21/21)

N.A.

100.0 % (194/194)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST	100.0 % (26/26)	100.0 % (20/20)	100.0 % (152/152)	100.0 % (30/30)	N.A.	N.A.	100.0 % (228/228)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST

100.0 % (26/26)

100.0 % (20/20)

100.0 % (152/152)

100.0 % (30/30)

N.A.

100.0 % (228/228)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 210 to 212:

210:    init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD) 
211:                            else 
212:                        '0';

Count: 3462
Threshold: 1

Signal assignment statement on line 210:

210: init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD)
Count: 1731
Threshold: 1

Signal assignment statement on line 212:

212: '0';
Count: 1731
Threshold: 1

If statement on lines 214 to 216:

214:    init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD) 
215:                            else 
216:                        '0';

Count: 3462
Threshold: 1

Signal assignment statement on line 214:

214: init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD)
Count: 1731
Threshold: 1

Signal assignment statement on line 216:

216: '0';
Count: 1731
Threshold: 1

If statement on lines 222 to 224:

222:    crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1') 
223:                                     else 
224:                         data_tx_wbs;

Count: 4234673
Threshold: 1

Signal assignment statement on line 222:

222: crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1')
Count: 2155248
Threshold: 1

Signal assignment statement on line 224:

224: data_tx_wbs;
Count: 2079425
Threshold: 1

If statement on lines 226 to 228:

226:    crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1') 
227:                                     else 
228:                         trig_tx_wbs;

Count: 45515208
Threshold: 1

Signal assignment statement on line 226:

226: crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1')
Count: 33318764
Threshold: 1

Signal assignment statement on line 228:

228: trig_tx_wbs;
Count: 12196444
Threshold: 1

If statement on lines 234 to 236:

234:    crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1') 
235:                                  else 
236:                      data_tx_nbs;

Count: 4243588
Threshold: 1

Signal assignment statement on line 234:

234: crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1')
Count: 2156498
Threshold: 1

Signal assignment statement on line 236:

236: data_tx_nbs;
Count: 2087090
Threshold: 1

If statement on lines 238 to 240:

238:    crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1') 
239:                                  else 
240:                      trig_tx_nbs;

Count: 43563752
Threshold: 1

Signal assignment statement on line 238:

238: crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1')
Count: 31912891
Threshold: 1

Signal assignment statement on line 240:

240: trig_tx_nbs;
Count: 11650861
Threshold: 1

If statement on lines 249 to 253:

249:    crc_ena_15   <= '1' when (crc_enable = '1') 
250:                        else 
251:                    '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT) 
252:                        else 
253:                    '0';

Count: 3091037
Threshold: 1

Signal assignment statement on line 249:

249: crc_ena_15 <= '1' when (crc_enable = '1')
Count: 2447247
Threshold: 1

Signal assignment statement on line 251:

251: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)
Count: 744
Threshold: 1

Signal assignment statement on line 253:

253: '0';
Count: 643046
Threshold: 1

If statement on lines 255 to 259:

255:    crc_ena_17_21  <= '1' when (crc_enable = '1') 
256:                          else 
257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT) 
258:                          else 
259:                      '0';

Count: 3119499
Threshold: 1

Signal assignment statement on line 255:

255: crc_ena_17_21 <= '1' when (crc_enable = '1')
Count: 2430015
Threshold: 1

Signal assignment statement on line 257:

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)

Count: 36826
Threshold: 1

Signal assignment statement on line 259:

259: '0';
Count: 652658
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 210:

210: init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD)

	Evaluated to	Count	Threshold
Bin	True	1731	1
Bin	False	1731	1

"if" / "when" / "else" condition on line 214:

214: init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD)

	Evaluated to	Count	Threshold
Bin	True	1731	1
Bin	False	1731	1

"if" / "when" / "else" condition on line 222:

222: crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	2155248	1
Bin	False	2079425	1

"if" / "when" / "else" condition on line 226:

226: crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	33318764	1
Bin	False	12196444	1

"if" / "when" / "else" condition on line 234:

234: crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	2156498	1
Bin	False	2087090	1

"if" / "when" / "else" condition on line 238:

238: crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	31912891	1
Bin	False	11650861	1

"if" / "when" / "else" condition on line 249:

249: crc_ena_15 <= '1' when (crc_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	2447247	1
Bin	False	643790	1

"if" / "when" / "else" condition on line 251:

251: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	True	744	1
Bin	False	643046	1

"if" / "when" / "else" condition on line 255:

255: crc_ena_17_21 <= '1' when (crc_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	2430015	1
Bin	False	689484	1

"if" / "when" / "else" condition on line 257:

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	True	36826	1
Bin	False	652658	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_NISOFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_TX_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_TX_NBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_RX_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_RX_NBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG_TX_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG_TX_NBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG_RX_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG_RX_NBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CRC_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CRC_SPEC_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CRC_CALC_FROM_RX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CRC_15

	Element	From	To	Count	Threshold
Bin	(14)	0	1	1456224	1
Bin	(14)	1	0	1457824	1
Bin	(13)	0	1	1412724	1
Bin	(13)	1	0	1414324	1
Bin	(12)	0	1	1427215	1
Bin	(12)	1	0	1428815	1
Bin	(11)	0	1	1440985	1
Bin	(11)	1	0	1442580	1
Bin	(10)	0	1	1455761	1
Bin	(10)	1	0	1457360	1
Bin	(9)	0	1	1446457	1
Bin	(9)	1	0	1448054	1
Bin	(8)	0	1	1461592	1
Bin	(8)	1	0	1463189	1
Bin	(7)	0	1	1492415	1
Bin	(7)	1	0	1494015	1
Bin	(6)	0	1	1426024	1
Bin	(6)	1	0	1427621	1
Bin	(5)	0	1	1440703	1
Bin	(5)	1	0	1442299	1
Bin	(4)	0	1	1453240	1
Bin	(4)	1	0	1454838	1
Bin	(3)	0	1	1455932	1
Bin	(3)	1	0	1457530	1
Bin	(2)	0	1	1446410	1
Bin	(2)	1	0	1448008	1
Bin	(1)	0	1	1462137	1
Bin	(1)	1	0	1463734	1
Bin	(0)	0	1	1474486	1
Bin	(0)	1	0	1476084	1

Port:

CRC_17

	Element	From	To	Count	Threshold
Bin	(16)	0	1	1743319	1
Bin	(16)	1	0	1744913	1
Bin	(15)	0	1	1753557	1
Bin	(15)	1	0	1755155	1
Bin	(14)	0	1	1766867	1
Bin	(14)	1	0	1768465	1
Bin	(13)	0	1	1762999	1
Bin	(13)	1	0	1764595	1
Bin	(12)	0	1	1700069	1
Bin	(12)	1	0	1701667	1
Bin	(11)	0	1	1716955	1
Bin	(11)	1	0	1718553	1
Bin	(10)	0	1	1661649	1
Bin	(10)	1	0	1663248	1
Bin	(9)	0	1	1675901	1
Bin	(9)	1	0	1677499	1
Bin	(8)	0	1	1688782	1
Bin	(8)	1	0	1690380	1
Bin	(7)	0	1	1702291	1
Bin	(7)	1	0	1703889	1
Bin	(6)	0	1	1717785	1
Bin	(6)	1	0	1719384	1
Bin	(5)	0	1	1718205	1
Bin	(5)	1	0	1719801	1
Bin	(4)	0	1	1732556	1
Bin	(4)	1	0	1734153	1
Bin	(3)	0	1	1752646	1
Bin	(3)	1	0	1754243	1
Bin	(2)	0	1	1715867	1
Bin	(2)	1	0	1717464	1
Bin	(1)	0	1	1730969	1
Bin	(1)	1	0	1732566	1
Bin	(0)	0	1	1768915	1
Bin	(0)	1	0	1770512	1

Port:

CRC_21

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1747719	1
Bin	(20)	1	0	1749311	1
Bin	(19)	0	1	1699622	1
Bin	(19)	1	0	1701219	1
Bin	(18)	0	1	1716066	1
Bin	(18)	1	0	1717663	1
Bin	(17)	0	1	1729728	1
Bin	(17)	1	0	1731328	1
Bin	(16)	0	1	1743409	1
Bin	(16)	1	0	1745008	1
Bin	(15)	0	1	1756358	1
Bin	(15)	1	0	1757957	1
Bin	(14)	0	1	1768901	1
Bin	(14)	1	0	1770498	1
Bin	(13)	0	1	1783918	1
Bin	(13)	1	0	1785513	1
Bin	(12)	0	1	1732017	1
Bin	(12)	1	0	1733614	1
Bin	(11)	0	1	1745487	1
Bin	(11)	1	0	1747087	1
Bin	(10)	0	1	1733386	1
Bin	(10)	1	0	1734982	1
Bin	(9)	0	1	1746619	1
Bin	(9)	1	0	1748216	1
Bin	(8)	0	1	1761088	1
Bin	(8)	1	0	1762684	1
Bin	(7)	0	1	1776191	1
Bin	(7)	1	0	1777791	1
Bin	(6)	0	1	1709060	1
Bin	(6)	1	0	1710658	1
Bin	(5)	0	1	1723265	1
Bin	(5)	1	0	1724863	1
Bin	(4)	0	1	1736710	1
Bin	(4)	1	0	1738310	1
Bin	(3)	0	1	1762520	1
Bin	(3)	1	0	1764117	1
Bin	(2)	0	1	1758156	1
Bin	(2)	1	0	1759752	1
Bin	(1)	0	1	1770759	1
Bin	(1)	1	0	1772359	1
Bin	(0)	0	1	1784893	1
Bin	(0)	1	0	1786489	1

Signal:

INIT_VECT_MSB_17

	From	To	Count	Threshold
Bin	0	1	1731	1
Bin	1	0	1731	1

Signal:

INIT_VECT_MSB_21

	From	To	Count	Threshold
Bin	0	1	1731	1
Bin	1	0	1731	1

Signal:

CRC_17_21_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1388899	1
Bin	1	0	1387299	1

Signal:

CRC_17_21_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11384444	1
Bin	1	0	11386045	1

Signal:

CRC_15_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1389713	1
Bin	1	0	1388113	1

Signal:

CRC_15_TRIGGER

	From	To	Count	Threshold
Bin	0	1	10646614	1
Bin	1	0	10648214	1

Signal:

CRC_ENA_15

	From	To	Count	Threshold
Bin	0	1	55762	1
Bin	1	0	57363	1

Signal:

CRC_ENA_17_21

	From	To	Count	Threshold
Bin	0	1	61750	1
Bin	1	0	63351	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 210:

mr_settings_nisofd = ISO_FD

	Evaluated to	Count	Threshold
Bin	False	1731	1
Bin	True	1731	1

"=" expression on line 214:

mr_settings_nisofd = ISO_FD

	Evaluated to	Count	Threshold
Bin	False	1731	1
Bin	True	1731	1

"=" expression on line 222:

crc_calc_from_rx = '1'

	Evaluated to	Count	Threshold
Bin	False	2079425	1
Bin	True	2155248	1

"=" expression on line 226:

crc_calc_from_rx = '1'

	Evaluated to	Count	Threshold
Bin	False	12196444	1
Bin	True	33318764	1

"=" expression on line 234:

crc_calc_from_rx = '1'

	Evaluated to	Count	Threshold
Bin	False	2087090	1
Bin	True	2156498	1

"=" expression on line 238:

crc_calc_from_rx = '1'

	Evaluated to	Count	Threshold
Bin	False	11650861	1
Bin	True	31912891	1

"=" expression on line 249:

crc_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	643790	1
Bin	True	2447247	1

"and" expression on line 251:

 crc_spec_enable = '1' and crc_15_data_in = DOMINANT 
 <--------LHS-------->     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	224309	1
Bin	True	False	113491	1
Bin	True	True	744	1

"=" expression on line 251:

crc_spec_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	529555	1
Bin	True	114235	1

"=" expression on line 251:

crc_15_data_in = DOMINANT

	Evaluated to	Count	Threshold
Bin	False	418737	1
Bin	True	225053	1

"=" expression on line 255:

crc_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	689484	1
Bin	True	2430015	1

"and" expression on line 257:

 crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT 
 <--------LHS-------->     <-----------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	228682	1
Bin	True	False	113491	1
Bin	True	True	36826	1

"=" expression on line 257:

crc_spec_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	539167	1
Bin	True	150317	1

"=" expression on line 257:

crc_17_21_data_in = DOMINANT

	Evaluated to	Count	Threshold
Bin	False	423976	1
Bin	True	265508	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 210 to 212:

Signal assignment statement on line 210:

Signal assignment statement on line 212:

If statement on lines 214 to 216:

Signal assignment statement on line 214:

Signal assignment statement on line 216:

If statement on lines 222 to 224:

Signal assignment statement on line 222:

Signal assignment statement on line 224:

If statement on lines 226 to 228:

Signal assignment statement on line 226:

Signal assignment statement on line 228:

If statement on lines 234 to 236:

Signal assignment statement on line 234:

Signal assignment statement on line 236:

If statement on lines 238 to 240:

Signal assignment statement on line 238:

Signal assignment statement on line 240:

If statement on lines 249 to 253:

Signal assignment statement on line 249:

Signal assignment statement on line 251:

Signal assignment statement on line 253:

If statement on lines 255 to 259:

Signal assignment statement on line 255:

Signal assignment statement on line 257:

Signal assignment statement on line 259:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 210:

"if" / "when" / "else" condition on line 214:

"if" / "when" / "else" condition on line 222:

"if" / "when" / "else" condition on line 226:

"if" / "when" / "else" condition on line 234:

"if" / "when" / "else" condition on line 238:

"if" / "when" / "else" condition on line 249:

"if" / "when" / "else" condition on line 251:

"if" / "when" / "else" condition on line 255:

"if" / "when" / "else" condition on line 257:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 210: