NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.RX_DATA_ACCESS_SIGNALLER_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (3/3)	N.A.	N.A.	100.0 % (26/26)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.RX_DATA_ACCESS_SIGNALLER_COMP

100.0 % (3/3)

100.0 % (2/2)

100.0 % (18/18)

100.0 % (3/3)

N.A.

100.0 % (26/26)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Excluded due to: Exclude file

Signal assignment statement on line 124:

124: '0';
Count: 0
Threshold: 1

Covered statements:

If statement on lines 122 to 124:

122:    read_signal  <= (read and cs) when (be /= BE_ZEROES) 
123:                                  else 
124:                              '0';

Count: 55157806
Threshold: 1

Signal assignment statement on line 122:

122: read_signal <= (read and cs) when (be /= BE_ZEROES)
Count: 55157806
Threshold: 1

Uncovered branches:

Excluded branches:

"if" / "when" / "else" condition on line 122:

122: read_signal <= (read and cs) when (be /= BE_ZEROES)

	Evaluated to	Count	Threshold	Excluded due to
Bin	False	0	1	Exclude file

Covered branches:

"if" / "when" / "else" condition on line 122:

122: read_signal <= (read and cs) when (be /= BE_ZEROES)

	Evaluated to	Count	Threshold
Bin	True	55157806	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

READ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

READ_SIGNAL

	From	To	Count	Threshold
Bin	0	1	51790	1
Bin	1	0	53391	1

Uncovered expressions:

Excluded expressions:

"and" expression on line 122:

 read and cs 
 LHS>    RHS

	LHS	RHS	Count	Threshold	Excluded due to
Bin	'0'	'1'	0	1	Exclude file

Covered expressions:

"and" expression on line 122:

 read and cs 
 LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'1'	'0'	26418314	1
Bin	'1'	'1'	51790	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.RX_DATA_ACCESS_SIGNALLER_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Signal assignment statement on line 124:

Covered statements:

If statement on lines 122 to 124:

Signal assignment statement on line 122:

Uncovered branches:

Excluded branches:

"if" / "when" / "else" condition on line 122:

Covered branches:

"if" / "when" / "else" condition on line 122:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Uncovered expressions:

Excluded expressions:

"and" expression on line 122:

Covered expressions:

"and" expression on line 122:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: