NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.RX_DATA_ACCESS_SIGNALLER_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/read_access_signaler.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.RX_DATA_ACCESS_SIGNALLER_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (3/3)	N.A.	N.A.	100.0 % (26/26)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Excluded due to: Exclude file

Signal assignment statement:

124: '0';
Count: 0
Threshold: 1

Covered statements:

If statement:

122:    read_signal  <= (read and cs) when (be /= BE_ZEROES) 
123:                                  else 
124:                              '0';

Count: 55694732
Threshold: 1

Signal assignment statement:

122: read_signal <= (read and cs) when (be /= BE_ZEROES)
Count: 55694732
Threshold: 1

Uncovered branches:

Excluded branches:

"if" / "when" / "else" condition:

122: read_signal <= (read and cs) when (be /= BE_ZEROES)

	Evaluated to	Count	Threshold	Excluded due to
Bin	False	0	1	Exclude file

Covered branches:

"if" / "when" / "else" condition:

122: read_signal <= (read and cs) when (be /= BE_ZEROES)

	Evaluated to	Count	Threshold
Bin	True	55694732	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	31028760	1
Bin	1	0	31030360	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	51733	1
Bin	1	0	53333	1

Port:

READ

	From	To	Count	Threshold
Bin	0	1	26704188	1
Bin	1	0	1089845	1

Port:

BE(3)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Port:

BE(2)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Port:

BE(1)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Port:

BE(0)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Port:

READ_SIGNAL

	From	To	Count	Threshold
Bin	0	1	51733	1
Bin	1	0	53333	1

Uncovered expressions:

Excluded expressions:

"and" expression

122:    read_signal  <= (read and cs) when (be /= BE_ZEROES) 
                         LHS>    RHS

	LHS	RHS	Count	Threshold	Excluded due to
Bin	'0'	'1'	0	1	Exclude file

Covered expressions:

"and" expression

122:    read_signal  <= (read and cs) when (be /= BE_ZEROES) 
                         LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'1'	'0'	26704188	1
Bin	'1'	'1'	51733	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.RX_DATA_ACCESS_SIGNALLER_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/read_access_signaler.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Signal assignment statement:

Covered statements:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

"if" / "when" / "else" condition:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Uncovered expressions:

Excluded expressions:

"and" expression

Covered expressions:

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: