NVC code coverage report

Signal assignment statement on line 208:

208:    txtb_port_b_data_out <= txtb_port_b_data_out_i; 
Count: 3637
Threshold: 1

---

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0'; 
Count: 1602
Threshold: 1

---

Signal assignment statement on line 277:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
Count: 66
Threshold: 1

---

Signal assignment statement on line 280:

280:               '0'; 
Count: 1536
Threshold: 1

---

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 10156506
Threshold: 1

---

Signal assignment statement on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
Count: 10150523
Threshold: 1

---

Signal assignment statement on line 285:

285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 5983
Threshold: 1

---

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb; 
Count: 95794
Threshold: 1

---

Signal assignment statement on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
Count: 94844
Threshold: 1

---

Signal assignment statement on line 289:

289:                           mr_tst_control_twrstb; 
Count: 950
Threshold: 1

---

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata; 
Count: 705524
Threshold: 1

---

Signal assignment statement on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
Count: 702192
Threshold: 1

---

Signal assignment statement on line 293:

293:                          mr_tst_wdata_tst_wdata; 
Count: 3332
Threshold: 1

---

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 85890
Threshold: 1

---

Signal assignment statement on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
Count: 84640
Threshold: 1

---

Signal assignment statement on line 298:

298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 1250
Threshold: 1

---

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0'); 
Count: 3934
Threshold: 1

---

Signal assignment statement on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
Count: 534
Threshold: 1

---

Signal assignment statement on line 302:

302:                                     (others => '0'); 
Count: 3400
Threshold: 1

"if" / "when" / "else" condition on lines 277 to 278:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 

	Evaluated to	Count	Threshold
Bin	True	66	1
Bin	False	1536	1

---

"if" / "when" / "else" condition on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	10150523	1
Bin	False	5983	1

---

"if" / "when" / "else" condition on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	94844	1
Bin	False	950	1

---

"if" / "when" / "else" condition on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	702192	1
Bin	False	3332	1

---

"if" / "when" / "else" condition on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	84640	1
Bin	False	1250	1

---

"if" / "when" / "else" condition on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 

	Evaluated to	Count	Threshold
Bin	True	534	1
Bin	False	3400	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_ADDR

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_MTGT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_WDATA_TST_WDATA

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_BE

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

Port:

 MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	121	1
Bin	(31)	1	0	286	1
Bin	(30)	0	1	116	1
Bin	(30)	1	0	281	1
Bin	(29)	0	1	115	1
Bin	(29)	1	0	280	1
Bin	(28)	0	1	122	1
Bin	(28)	1	0	287	1
Bin	(27)	0	1	124	1
Bin	(27)	1	0	289	1
Bin	(26)	0	1	117	1
Bin	(26)	1	0	282	1
Bin	(25)	0	1	123	1
Bin	(25)	1	0	288	1
Bin	(24)	0	1	120	1
Bin	(24)	1	0	285	1
Bin	(23)	0	1	131	1
Bin	(23)	1	0	296	1
Bin	(22)	0	1	126	1
Bin	(22)	1	0	291	1
Bin	(21)	0	1	128	1
Bin	(21)	1	0	293	1
Bin	(20)	0	1	123	1
Bin	(20)	1	0	288	1
Bin	(19)	0	1	112	1
Bin	(19)	1	0	277	1
Bin	(18)	0	1	128	1
Bin	(18)	1	0	293	1
Bin	(17)	0	1	128	1
Bin	(17)	1	0	293	1
Bin	(16)	0	1	113	1
Bin	(16)	1	0	278	1
Bin	(15)	0	1	122	1
Bin	(15)	1	0	287	1
Bin	(14)	0	1	122	1
Bin	(14)	1	0	287	1
Bin	(13)	0	1	124	1
Bin	(13)	1	0	289	1
Bin	(12)	0	1	122	1
Bin	(12)	1	0	287	1
Bin	(11)	0	1	123	1
Bin	(11)	1	0	288	1
Bin	(10)	0	1	121	1
Bin	(10)	1	0	286	1
Bin	(9)	0	1	118	1
Bin	(9)	1	0	283	1
Bin	(8)	0	1	110	1
Bin	(8)	1	0	275	1
Bin	(7)	0	1	122	1
Bin	(7)	1	0	287	1
Bin	(6)	0	1	117	1
Bin	(6)	1	0	282	1
Bin	(5)	0	1	123	1
Bin	(5)	1	0	288	1
Bin	(4)	0	1	127	1
Bin	(4)	1	0	292	1
Bin	(3)	0	1	124	1
Bin	(3)	1	0	289	1
Bin	(2)	0	1	121	1
Bin	(2)	1	0	286	1
Bin	(1)	0	1	121	1
Bin	(1)	1	0	286	1
Bin	(0)	0	1	126	1
Bin	(0)	1	0	291	1

---

Port:

 TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	395	1
Bin	(31)	1	0	550	1
Bin	(30)	0	1	318	1
Bin	(30)	1	0	473	1
Bin	(29)	0	1	342	1
Bin	(29)	1	0	497	1
Bin	(28)	0	1	566	1
Bin	(28)	1	0	717	1
Bin	(27)	0	1	641	1
Bin	(27)	1	0	793	1
Bin	(26)	0	1	595	1
Bin	(26)	1	0	744	1
Bin	(25)	0	1	497	1
Bin	(25)	1	0	649	1
Bin	(24)	0	1	593	1
Bin	(24)	1	0	744	1
Bin	(23)	0	1	664	1
Bin	(23)	1	0	815	1
Bin	(22)	0	1	637	1
Bin	(22)	1	0	787	1
Bin	(21)	0	1	690	1
Bin	(21)	1	0	840	1
Bin	(20)	0	1	703	1
Bin	(20)	1	0	855	1
Bin	(19)	0	1	526	1
Bin	(19)	1	0	674	1
Bin	(18)	0	1	501	1
Bin	(18)	1	0	651	1
Bin	(17)	0	1	501	1
Bin	(17)	1	0	654	1
Bin	(16)	0	1	411	1
Bin	(16)	1	0	566	1
Bin	(15)	0	1	574	1
Bin	(15)	1	0	726	1
Bin	(14)	0	1	462	1
Bin	(14)	1	0	615	1
Bin	(13)	0	1	479	1
Bin	(13)	1	0	631	1
Bin	(12)	0	1	633	1
Bin	(12)	1	0	785	1
Bin	(11)	0	1	545	1
Bin	(11)	1	0	700	1
Bin	(10)	0	1	419	1
Bin	(10)	1	0	571	1
Bin	(9)	0	1	744	1
Bin	(9)	1	0	889	1
Bin	(8)	0	1	574	1
Bin	(8)	1	0	728	1
Bin	(7)	0	1	871	1
Bin	(7)	1	0	1014	1
Bin	(6)	0	1	898	1
Bin	(6)	1	0	1042	1
Bin	(5)	0	1	470	1
Bin	(5)	1	0	622	1
Bin	(4)	0	1	716	1
Bin	(4)	1	0	868	1
Bin	(3)	0	1	731	1
Bin	(3)	1	0	878	1
Bin	(2)	0	1	583	1
Bin	(2)	1	0	729	1
Bin	(1)	0	1	705	1
Bin	(1)	1	0	857	1
Bin	(0)	0	1	608	1
Bin	(0)	1	0	754	1

---

Port:

 PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	440	1
Bin	1	0	605	1

---

Signal:

 TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	101691	1
Bin	(4)	1	0	4945434	1
Bin	(3)	0	1	136075	1
Bin	(3)	1	0	4911040	1
Bin	(2)	0	1	116596	1
Bin	(2)	1	0	4930653	1
Bin	(1)	0	1	4800147	1
Bin	(1)	1	0	247392	1
Bin	(0)	0	1	3690509	1
Bin	(0)	1	0	1357621	1

---

Signal:

 TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11306	1
Bin	1	0	11495	1

---

Signal:

 TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	23196	1
Bin	(31)	1	0	325451	1
Bin	(30)	0	1	23919	1
Bin	(30)	1	0	324726	1
Bin	(29)	0	1	23611	1
Bin	(29)	1	0	325036	1
Bin	(28)	0	1	30327	1
Bin	(28)	1	0	318324	1
Bin	(27)	0	1	28630	1
Bin	(27)	1	0	320027	1
Bin	(26)	0	1	30166	1
Bin	(26)	1	0	318483	1
Bin	(25)	0	1	29668	1
Bin	(25)	1	0	318979	1
Bin	(24)	0	1	27595	1
Bin	(24)	1	0	321054	1
Bin	(23)	0	1	26827	1
Bin	(23)	1	0	321826	1
Bin	(22)	0	1	27277	1
Bin	(22)	1	0	321384	1
Bin	(21)	0	1	24892	1
Bin	(21)	1	0	323767	1
Bin	(20)	0	1	27077	1
Bin	(20)	1	0	321586	1
Bin	(19)	0	1	40000	1
Bin	(19)	1	0	308655	1
Bin	(18)	0	1	45775	1
Bin	(18)	1	0	302880	1
Bin	(17)	0	1	45247	1
Bin	(17)	1	0	303413	1
Bin	(16)	0	1	88123	1
Bin	(16)	1	0	260531	1
Bin	(15)	0	1	24314	1
Bin	(15)	1	0	324333	1
Bin	(14)	0	1	28216	1
Bin	(14)	1	0	320443	1
Bin	(13)	0	1	25185	1
Bin	(13)	1	0	323476	1
Bin	(12)	0	1	26197	1
Bin	(12)	1	0	322466	1
Bin	(11)	0	1	46073	1
Bin	(11)	1	0	302584	1
Bin	(10)	0	1	48341	1
Bin	(10)	1	0	300326	1
Bin	(9)	0	1	55975	1
Bin	(9)	1	0	292674	1
Bin	(8)	0	1	55462	1
Bin	(8)	1	0	293187	1
Bin	(7)	0	1	50611	1
Bin	(7)	1	0	298032	1
Bin	(6)	0	1	48519	1
Bin	(6)	1	0	300140	1
Bin	(5)	0	1	50447	1
Bin	(5)	1	0	298212	1
Bin	(4)	0	1	55196	1
Bin	(4)	1	0	293461	1
Bin	(3)	0	1	61939	1
Bin	(3)	1	0	286712	1
Bin	(2)	0	1	63992	1
Bin	(2)	1	0	284662	1
Bin	(1)	0	1	100643	1
Bin	(1)	1	0	248008	1
Bin	(0)	0	1	88195	1
Bin	(0)	1	0	260480	1

---

Signal:

 TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	3342	1
Bin	(4)	1	0	3507	1
Bin	(3)	0	1	179	1
Bin	(3)	1	0	344	1
Bin	(2)	0	1	5253	1
Bin	(2)	1	0	5418	1
Bin	(1)	0	1	4027	1
Bin	(1)	1	0	4027	1
Bin	(0)	0	1	11347	1
Bin	(0)	1	0	11512	1

---

Signal:

 TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	395	1
Bin	(31)	1	0	550	1
Bin	(30)	0	1	318	1
Bin	(30)	1	0	473	1
Bin	(29)	0	1	342	1
Bin	(29)	1	0	497	1
Bin	(28)	0	1	566	1
Bin	(28)	1	0	717	1
Bin	(27)	0	1	641	1
Bin	(27)	1	0	793	1
Bin	(26)	0	1	595	1
Bin	(26)	1	0	744	1
Bin	(25)	0	1	497	1
Bin	(25)	1	0	649	1
Bin	(24)	0	1	593	1
Bin	(24)	1	0	744	1
Bin	(23)	0	1	664	1
Bin	(23)	1	0	815	1
Bin	(22)	0	1	637	1
Bin	(22)	1	0	787	1
Bin	(21)	0	1	690	1
Bin	(21)	1	0	840	1
Bin	(20)	0	1	703	1
Bin	(20)	1	0	855	1
Bin	(19)	0	1	526	1
Bin	(19)	1	0	674	1
Bin	(18)	0	1	501	1
Bin	(18)	1	0	651	1
Bin	(17)	0	1	501	1
Bin	(17)	1	0	654	1
Bin	(16)	0	1	411	1
Bin	(16)	1	0	566	1
Bin	(15)	0	1	574	1
Bin	(15)	1	0	726	1
Bin	(14)	0	1	462	1
Bin	(14)	1	0	615	1
Bin	(13)	0	1	479	1
Bin	(13)	1	0	631	1
Bin	(12)	0	1	633	1
Bin	(12)	1	0	785	1
Bin	(11)	0	1	545	1
Bin	(11)	1	0	700	1
Bin	(10)	0	1	419	1
Bin	(10)	1	0	571	1
Bin	(9)	0	1	744	1
Bin	(9)	1	0	889	1
Bin	(8)	0	1	574	1
Bin	(8)	1	0	728	1
Bin	(7)	0	1	871	1
Bin	(7)	1	0	1014	1
Bin	(6)	0	1	898	1
Bin	(6)	1	0	1042	1
Bin	(5)	0	1	470	1
Bin	(5)	1	0	622	1
Bin	(4)	0	1	716	1
Bin	(4)	1	0	868	1
Bin	(3)	0	1	731	1
Bin	(3)	1	0	878	1
Bin	(2)	0	1	583	1
Bin	(2)	1	0	729	1
Bin	(1)	0	1	705	1
Bin	(1)	1	0	857	1
Bin	(0)	0	1	608	1
Bin	(0)	1	0	754	1

---

Signal:

 TST_ENA

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	231	1

---

Signal:

 PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	16	1
Bin	(20)	1	0	675	1
Bin	(19)	0	1	1	1
Bin	(19)	1	0	690	1
Bin	(18)	0	1	2	1
Bin	(18)	1	0	689	1
Bin	(17)	0	1	3	1
Bin	(17)	1	0	688	1
Bin	(16)	0	1	4	1
Bin	(16)	1	0	687	1
Bin	(15)	0	1	5	1
Bin	(15)	1	0	686	1
Bin	(14)	0	1	7	1
Bin	(14)	1	0	684	1
Bin	(13)	0	1	9	1
Bin	(13)	1	0	682	1
Bin	(12)	0	1	11	1
Bin	(12)	1	0	680	1
Bin	(11)	0	1	13	1
Bin	(11)	1	0	678	1
Bin	(10)	0	1	15	1
Bin	(10)	1	0	676	1
Bin	(9)	0	1	16	1
Bin	(9)	1	0	675	1
Bin	(8)	0	1	30	1
Bin	(8)	1	0	661	1
Bin	(7)	0	1	38	1
Bin	(7)	1	0	653	1
Bin	(6)	0	1	37	1
Bin	(6)	1	0	654	1
Bin	(5)	0	1	89	1
Bin	(5)	1	0	602	1
Bin	(4)	0	1	180	1
Bin	(4)	1	0	511	1
Bin	(3)	0	1	294	1
Bin	(3)	1	0	397	1
Bin	(2)	0	1	371	1
Bin	(2)	1	0	320	1
Bin	(1)	0	1	220	1
Bin	(1)	1	0	471	1
Bin	(0)	0	1	245	1
Bin	(0)	1	0	446	1

---

Signal:

 PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	956	1
Bin	1	0	809	1

---

Signal:

 PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	754	1
Bin	1	0	919	1

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1	Copy to Clipboard

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold
Bin	True	False	605	1
Bin	True	True	66	1

---

"=" expression on line 277:

 mr_tst_control_tmaena = '1' 

	Evaluated to	Count	Threshold
Bin	False	931	1
Bin	True	671	1

---

"=" expression on line 283:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	5983	1
Bin	True	10150523	1

---

"=" expression on line 287:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	950	1
Bin	True	94844	1

---

"=" expression on line 291:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	3332	1
Bin	True	702192	1

---

"=" expression on line 296:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	1250	1
Bin	True	84640	1

---

"=" expression on line 300:

 tst_ena = '1' 

	Evaluated to	Count	Threshold
Bin	False	3400	1
Bin	True	534	1