File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_odd.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- TXT Buffer - Odd index
71: --
72: -- Purpose:
73: -- Stores single frame for transmission in internal RAM. Accessed from Memory
74: -- registers via memory bus (to store frame) and SW commands.
75: --------------------------------------------------------------------------------
76:
77: Library ieee;
78: use ieee.std_logic_1164.all;
79: use ieee.numeric_std.ALL;
80: use ieee.math_real.ALL;
81:
82: Library ctu_can_fd_rtl;
83: use ctu_can_fd_rtl.can_constants_pkg.all;
84: use ctu_can_fd_rtl.can_types_pkg.all;
85:
86: use ctu_can_fd_rtl.CAN_FD_register_map.all;
87: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
88:
89: use ctu_can_fd_rtl.can_registers_pkg.all;
90:
91: entity txt_buffer_odd is
92: generic (
93: -- Number of TXT Buffers
94: G_TXT_BUFFER_COUNT : natural range 2 to 8;
95:
96: -- TXT Buffer ID
97: G_ID : natural;
98:
99: -- Technology type
100: G_TECHNOLOGY : natural;
101:
102: -- Support Parity Error
103: G_SUP_PARITY : boolean;
104:
105: -- TXT Buffer RAMs are resetable
106: G_RESET_TXT_BUF_RAM : boolean
107: );
108: port (
109: -------------------------------------------------------------------------------------------
110: -- Clock and Asynchronous reset
111: -------------------------------------------------------------------------------------------
112: clk_sys : in std_logic;
113: res_n : in std_logic;
114:
115: -------------------------------------------------------------------------------------------
116: -- DFT support
117: -------------------------------------------------------------------------------------------
118: scan_enable : in std_logic;
119:
120: -------------------------------------------------------------------------------------------
121: -- Memory Registers Interface
122: -------------------------------------------------------------------------------------------
123: -- Control signals
124: mr_mode_bmm : in std_logic;
125: mr_mode_rom : in std_logic;
126: mr_mode_txbbm : in std_logic;
127: mr_settings_tbfbo : in std_logic;
128: mr_settings_pchke : in std_logic;
129: mr_tx_command_txce : in std_logic;
130: mr_tx_command_txcr : in std_logic;
131: mr_tx_command_txca : in std_logic;
132: mr_tx_command_txbi : in std_logic;
133:
134: -- Memory Testability
135: mr_tst_control_tmaena : in std_logic;
136: mr_tst_control_twrstb : in std_logic;
137: mr_tst_dest_tst_addr : in std_logic_vector(4 downto 0);
138: mr_tst_dest_tst_mtgt : in std_logic_vector(3 downto 0);
139: mr_tst_wdata_tst_wdata : in std_logic_vector(31 downto 0);
140: mr_tst_rdata_tst_rdata : out std_logic_vector(31 downto 0);
141:
142: -- Port A - Write Bus
143: txtb_port_a_data_in : in std_logic_vector(31 downto 0);
144: txtb_port_a_parity : in std_logic;
145: txtb_port_a_address : in std_logic_vector(4 downto 0);
146: txtb_port_a_cs : in std_logic;
147: txtb_port_a_be : in std_logic_vector(3 downto 0);
148: txtb_state : out std_logic_vector(3 downto 0);
149:
150: -- TXT Buffer is backup buffer
151: txtb_is_bb : in std_logic;
152:
153: -------------------------------------------------------------------------------------------
154: -- Interrupt Manager Interface
155: -------------------------------------------------------------------------------------------
156: -- HW Command applied
157: txtb_hw_cmd_int : out std_logic;
158:
159: -------------------------------------------------------------------------------------------
160: -- CAN Core and TX Arbitrator Interface
161: -------------------------------------------------------------------------------------------
162: -- HW Commands
163: txtb_hw_cmd : in t_txtb_hw_cmd;
164:
165: -- HW commands chip select
166: txtb_hw_cmd_cs : in std_logic;
167:
168: -- TXT Buffer RAM data output
169: txtb_port_b_data_out : out std_logic_vector(31 downto 0);
170:
171: -- TXT Buffer RAM address
172: txtb_port_b_address : in std_logic_vector(4 downto 0);
173:
174: -- Clock enable to TXT Buffer port B
175: txtb_port_b_clk_en : in std_logic;
176:
177: -- Unit just turned bus off.
178: is_bus_off : in std_logic;
179:
180: -- TXT Buffer is available to be locked by CAN Core for transmission
181: txtb_available : out std_logic;
182:
183: -- TXT Buffer is in state for which its backup buffer can be used
184: txtb_allow_bb : out std_logic;
185:
186: -- Parity check valid
187: txtb_parity_check_valid : in std_logic;
188:
189: -- Parity error detected
190: txtb_parity_mismatch : out std_logic;
191:
192: -- Parity error really occured
193: txtb_parity_error_valid : out std_logic;
194:
195: -- Parity error in Backup buffer
196: txtb_bb_parity_error : out std_logic;
197:
198: -- Index of TXT Buffer which is being read
199: txtb_index_muxed : in natural range 0 to G_TXT_BUFFER_COUNT - 1
200: );
201: end entity;
202:
203: architecture rtl of txt_buffer_odd is
204:
205: -----------------------------------------------------------------------------------------------
206: -- Internal signals
207: -----------------------------------------------------------------------------------------------
208:
209: -- TXT Buffer memory protection
210: signal txtb_user_accessible : std_logic;
211:
212: -- Unmask TXT Buffer RAM output
213: signal txtb_unmask_data_ram : std_logic;
214:
215: -- Output of TXT Buffer RAM
216: signal txtb_port_b_data_out_i : std_logic_vector(31 downto 0);
217:
218: -- TXT Buffer parity error
219: signal txtb_parity_error_valid_i : std_logic;
220:
221: -- TXT Buffer SW commands - registered
222: signal mr_tx_command_txce_q : std_logic;
223: signal mr_tx_command_txcr_q : std_logic;
224: signal mr_tx_command_txca_q : std_logic;
225:
226: -- Auxiliarly signals
227: signal tx_command_txce_valid : std_logic;
228: signal tx_command_txcr_valid : std_logic;
229: signal abort_applied : std_logic;
230: signal buffer_skipped : std_logic;
231: signal abort_or_skipped : std_logic;
232:
233: -----------------------------------------------------------------------------------------------
234: -----------------------------------------------------------------------------------------------
235: -- RAM wrapper signals
236: -----------------------------------------------------------------------------------------------
237: -----------------------------------------------------------------------------------------------
238: signal txtb_port_a_write : std_logic;
239:
240: -- Clock enabled
241: signal txtb_ram_clk_en : std_logic;
242:
243: -- RAM clocks
244: signal clk_ram : std_logic;
245:
246: -- Parity check
247: signal parity_mismatch : std_logic;
248:
249: begin
250:
251: -- TXT Buffer RAM write signal
252: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
253: else
254: '0';
255:
256: -----------------------------------------------------------------------------------------------
257: -- Output of TXT Buffer RAM is masked when it is not valid. This has several reasons:
258: -- 1. RAM content is undefined, therefore before filling RAM, XXXs on output if further
259: -- comparator logic of TX Arbitrator will yell a lot. This saves from flood of simulation
260: -- warnings!
261: -- 2. CAN Core and TX Arbitrator should not be reading any data from TXT Buffer RAM when it is
262: -- not in Ready, TX in Progress or Abort in Progress (SW did not fill them yet). So we make
263: -- sure that they are not used somewhere when they might be undefined yet!
264: -----------------------------------------------------------------------------------------------
265: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
266: else
267: (others => '0');
268:
269: -----------------------------------------------------------------------------------------------
270: -- Clock gating for TXT Buffer RAM. Enable when:
271: -- 1. Read access from CAN core
272: -- 2. Write access from user
273: -- 3. Always in memory test mode, or in scan mode
274: -----------------------------------------------------------------------------------------------
275: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
276: else
277: '1' when (mr_tst_control_tmaena = '1')
278: else
279: '0';
280:
281: -----------------------------------------------------------------------------------------------
282: -- Parity error really occured (and STATUS[TXPE] can be set), only when TX Arbitrator or CAN
283: -- Core have really read from the TXT Buffer, otherwise the output might be rubbish (uninited
284: -- data, previous value).
285: -----------------------------------------------------------------------------------------------
286: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
287: txtb_parity_check_valid = '1' and
288: txtb_index_muxed = G_ID)
289: else
290: '0';
291:
292: txtb_parity_error_valid <= txtb_parity_error_valid_i;
293:
294:
295: -----------------------------------------------------------------------------------------------
296: -- Register the TXT Buffer commands -> Breaks paths from memory bus
297: -----------------------------------------------------------------------------------------------
298: sw_command_reg_proc : process(res_n, clk_sys)
299: begin
300: if (res_n = '0') then
301: mr_tx_command_txce_q <= '0';
302: mr_tx_command_txcr_q <= '0';
303: mr_tx_command_txca_q <= '0';
304: elsif (rising_edge(clk_sys)) then
305: mr_tx_command_txce_q <= mr_tx_command_txce;
306: mr_tx_command_txcr_q <= mr_tx_command_txcr;
307: mr_tx_command_txca_q <= mr_tx_command_txca;
308: end if;
309: end process;
310:
311: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
312: else
313: '0';
314: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
315: else
316: '0';
317:
318: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
319: else
320: '0';
321:
322: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
323: (txtb_is_bb = '1'))
324: else
325: '0';
326:
327: abort_or_skipped <= abort_applied or buffer_skipped;
328:
329: -----------------------------------------------------------------------------------------------
330: -- If parity error occurs in Backup Buffer during TXTB modes, then set STATUS[TXDPE] = 1.
331: -----------------------------------------------------------------------------------------------
332: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
333: else
334: '0';
335:
336: -----------------------------------------------------------------------------------------------
337: -- Clock gater for TXT Buffer RAM
338: -----------------------------------------------------------------------------------------------
339: clk_gate_txt_buffer_ram_comp : entity ctu_can_fd_rtl.clk_gate
340: generic map (
341: G_TECHNOLOGY => G_TECHNOLOGY
342: )
343: port map (
344: clk_in => clk_sys, -- IN
345: clk_en => txtb_ram_clk_en, -- IN
346: scan_enable => scan_enable, -- IN
347:
348: clk_out => clk_ram -- OUT
349: );
350:
351: -----------------------------------------------------------------------------------------------
352: -- RAM Memory of TXT Buffer
353: -----------------------------------------------------------------------------------------------
354: txt_buffer_ram_inst : entity ctu_can_fd_rtl.txt_buffer_ram
355: generic map (
356: G_ID => G_ID,
357: G_SUP_PARITY => G_SUP_PARITY,
358: G_RESET_TXT_BUF_RAM => G_RESET_TXT_BUF_RAM
359: )
360: port map (
361: -- Clock and Asynchronous reset
362: clk_sys => clk_ram, -- IN
363: res_n => res_n, -- IN
364:
365: -- Parity configuration
366: mr_settings_pchke => mr_settings_pchke, -- IN
367:
368: -- Memory testability
369: mr_tst_control_tmaena => mr_tst_control_tmaena, -- IN
370: mr_tst_control_twrstb => mr_tst_control_twrstb, -- IN
371: mr_tst_dest_tst_addr => mr_tst_dest_tst_addr, -- IN
372: mr_tst_dest_tst_mtgt => mr_tst_dest_tst_mtgt, -- IN
373: mr_tst_wdata_tst_wdata => mr_tst_wdata_tst_wdata, -- IN
374:
375: mr_tst_rdata_tst_rdata => mr_tst_rdata_tst_rdata, -- OUT
376:
377: -- Port A - Write (from Memory registers)
378: txtb_port_a_address => txtb_port_a_address, -- IN
379: txtb_port_a_data_in => txtb_port_a_data_in, -- IN
380: txtb_port_a_parity => txtb_port_a_parity, -- IN
381: txtb_port_a_write => txtb_port_a_write, -- IN
382: txtb_port_a_be => txtb_port_a_be, -- IN
383:
384: -- Port B - Read (from CAN Core)
385: txtb_port_b_address => txtb_port_b_address, -- IN
386: txtb_port_b_data_out => txtb_port_b_data_out_i, -- OUT
387:
388: -- Parity check
389: parity_mismatch => parity_mismatch -- OUT
390: );
391:
392: -----------------------------------------------------------------------------------------------
393: -- TXT Buffer FSM
394: -----------------------------------------------------------------------------------------------
395: txt_buffer_fsm_inst : entity ctu_can_fd_rtl.txt_buffer_fsm
396: port map (
397: clk_sys => clk_sys, -- IN
398: res_n => res_n, -- IN
399:
400: mr_mode_bmm => mr_mode_bmm, -- IN
401: mr_mode_rom => mr_mode_rom, -- IN
402: mr_settings_tbfbo => mr_settings_tbfbo, -- IN
403:
404: tx_command_txce_valid => tx_command_txce_valid, -- IN
405: tx_command_txcr_valid => tx_command_txcr_valid, -- IN
406: abort_applied => abort_applied, -- IN
407: abort_or_skipped => abort_or_skipped, -- IN
408:
409: txtb_hw_cmd => txtb_hw_cmd, -- IN
410: txtb_hw_cmd_cs => txtb_hw_cmd_cs, -- IN
411: is_bus_off => is_bus_off, -- IN
412: txtb_parity_error_valid => txtb_parity_error_valid_i, -- IN
413:
414: txtb_allow_bb => txtb_allow_bb, -- OUT
415: txtb_user_accessible => txtb_user_accessible, -- OUT
416: txtb_hw_cmd_int => txtb_hw_cmd_int, -- OUT
417: txtb_state => txtb_state, -- OUT
418: txtb_available => txtb_available, -- OUT
419: txtb_unmask_data_ram => txtb_unmask_data_ram -- OUT
420: );
421:
422: txtb_parity_mismatch <= parity_mismatch;
423:
424: -----------------------------------------------------------------------------------------------
425: -- Assertions
426: -----------------------------------------------------------------------------------------------
427:
428: -- psl default clock is rising_edge(clk_sys);
429:
430: -----------------------------------------------------------------------------------------------
431: -- Skipped shall never occur when TXT Buffer backup is not ready. It should
432: -- be satisfied by equal priority of "original" and "backup" buffer, and the
433: -- fact that SW commands are mirrored for Backup buffers.
434: --
435: -- psl txtb_no_skip_when_not_ready : assert always
436: -- (buffer_skipped = '1') -> (txtb_state = TXT_RDY)
437: -- report "Backup TXT Buffer skipped when not in 'Ready' state.";
438: -----------------------------------------------------------------------------------------------
439:
440: end architecture;