NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP.ADDR_DEC_GEN(29)

File:  /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP.ADDR_DEC_GEN(29) 100.0 % (3/3) 100.0 % (2/2) N.A. N.A. N.A. N.A. 100.0 % (5/5)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

144:        addr_dec_i(i) <= '1' when (address = addr_vect(h_ind downto l_ind)) 
145:                             else 
146:                         '0'; 
Count: 55591266
Threshold: 1

Signal assignment statement:

144:        addr_dec_i(i) <= '1' when (address = addr_vect(h_ind downto l_ind)) 
Count: 42600
Threshold: 1

Signal assignment statement:

146:                         '0'; 
Count: 55548666
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

144:        addr_dec_i(i) <= '1' when (address = addr_vect(h_ind downto l_ind)) 
Evaluated toCountThreshold
BinTrue426001
BinFalse555486661

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: