File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Purpose:
70: -- Generic address decoder!
71: --------------------------------------------------------------------------------
72: -- Revision History:
73: -- 14.10.2018 Created file
74: -- 07.12.2018 Added enable signal. Active only when enable is in logic 1,
75: -- otherwise disabled.
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: USE IEEE.std_logic_1164.all;
80: USE IEEE.numeric_std.ALL;
81:
82: entity address_decoder is
83: generic(
84:
85: -- Width of address input
86: constant address_width : natural;
87:
88: -- Number of address entries to decode
89: constant address_entries : natural;
90:
91: -- Addresses to be decoded joined to single address vector. This is
92: -- beneficial since there can be gaps in addresses between extra logic!
93: constant addr_vect : std_logic_vector;
94:
95: -- Choose betweed registered/ non-registered output
96: constant registered_out : boolean := false
97: );
98: port(
99: ------------------------------------------------------------------------
100: -- Clock and reset
101: ------------------------------------------------------------------------
102: signal clk_sys :in std_logic;
103: signal res_n :in std_logic;
104:
105: ------------------------------------------------------------------------
106: -- Address input
107: ------------------------------------------------------------------------
108: signal address :in std_logic_vector(address_width - 1 downto 0);
109:
110: ------------------------------------------------------------------------
111: -- Enable input
112: ------------------------------------------------------------------------
113: signal enable :in std_logic;
114:
115: ------------------------------------------------------------------------
116: -- Output, one-hot coded. In logic 1 for each valid address
117: ------------------------------------------------------------------------
118: signal addr_dec :out std_logic_vector(address_entries - 1 downto 0)
119: );
120:
121: end entity address_decoder;
122:
123:
124: architecture rtl of address_decoder is
125:
126: -- Internal one-hot coded signal of address decoder
127: signal addr_dec_i : std_logic_vector(
128: address_entries - 1 downto 0);
129:
130: -- Address after masking by enable input
131: signal addr_dec_enabled_i : std_logic_vector(
132: address_entries - 1 downto 0);
133:
134: begin
135:
136: ---------------------------------------------------------------------------
137: -- Combinational Address decoder
138: ---------------------------------------------------------------------------
139: addr_dec_gen : for i in 0 to address_entries - 1 generate
140: constant l_ind : natural := address_width * i;
141: constant h_ind : natural := (address_width * (i + 1)) - 1;
142: begin
143: addr_dec_i(i) <= '1' when (address = addr_vect(h_ind downto l_ind))
144: else
145: '0';
146: end generate addr_dec_gen;
147:
148:
149: ---------------------------------------------------------------------------
150: -- Address decoder enabled / disabled - masking
151: ---------------------------------------------------------------------------
152: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else
153: (OTHERS => '0');
154:
155:
156: ---------------------------------------------------------------------------
157: -- Registering / Not-registering output
158: ---------------------------------------------------------------------------
159: addr_dec_reg_true_gen : if (registered_out) generate
160: addr_dec_reg_proc : process(res_n, clk_sys)
161: begin
162: if (res_n = '0') then
163: addr_dec <= (OTHERS => '0');
164:
165: elsif (rising_edge(clk_sys)) then
166: addr_dec <= addr_dec_enabled_i;
167:
168: end if;
169: end process;
170: end generate addr_dec_reg_true_gen;
171:
172: addr_dec_reg_false_gen : if (not registered_out) generate
173: addr_dec <= addr_dec_enabled_i;
174: end generate addr_dec_reg_false_gen;
175:
176:
177: ---------------------------------------------------------------------------
178: -- Check that input vector length is correct.
179: ---------------------------------------------------------------------------
180: -- pragma translate_off
181: -- coverage off
182: assert (addr_vect'length = address_width * address_entries)
183: report "Invalid length of address vector: " &
184: integer'image(addr_vect'length) &
185: " Length should be: " &
186: integer'image(address_width * address_entries)
187: severity failure;
188: -- coverage on
189: -- pragma translate_on
190:
191: end architecture;