NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST.RST_REG_INST.RX_SHIFT_RES_REG_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST.RST_REG_INST.RX_SHIFT_RES_REG_INST	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

105:        if (arst = G_RESET_POLARITY) then 
106:            reg_q <= G_RST_VAL; 
107:        elsif (rising_edge(clk)) then 
108:            reg_q <= reg_d; 
109:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

106: reg_q <= G_RST_VAL;
Count: 2418499
Threshold: 1

Signal assignment statement:

108: reg_q <= reg_d;
Count: 526374300
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

105: if (arst = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

107: elsif (rising_edge(clk)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

ARST

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

CLK

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

REG_D

	From	To	Count	Threshold
Bin	0	1	14718	1
Bin	1	0	14708	1

Port:

REG_Q

	From	To	Count	Threshold
Bin	0	1	14717	1
Bin	1	0	14708	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

105: if (arst = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST.RST_REG_INST.RX_SHIFT_RES_REG_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: