| Current Instance | Statement | Branch | Toggle | Expression | FSM state | Functional | Average |
|---|---|---|---|---|---|---|---|
| CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.CLK_GATE_TXT_BUFFER_RAM_COMP.G_TECH_ASIC | 100.0 % (3/3) | 100.0 % (2/2) | N.A. | 100.0 % (8/8) | N.A. | N.A. | 100.0 % (13/13) |
| Statement | Branch | Toggle | Expression | FSM state | Functional |
|---|
113: if (clk_in = '0') then
114: clk_en_q <= clk_en or scan_enable;
115: end if; 114: clk_en_q <= clk_en or scan_enable; 119: clk_out <= clk_in AND clk_en_q; 113: if (clk_in = '0') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 530957302 | 1 |
| Bin | False | 531158156 | 1 |
clk_in = '0' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 531158156 | 1 |
| Bin | True | 530957302 | 1 |
clk_en or scan_enable
<LHS-> <---RHS---> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | '0' | '0' | 529875748 | 1 |
| Bin | '0' | '1' | 40 | 1 |
| Bin | '1' | '0' | 1081514 | 1 |
clk_in AND clk_en_q
<LHS-> <-RHS--> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | '0' | '1' | 1326298 | 1 |
| Bin | '1' | '0' | 529730001 | 1 |
| Bin | '1' | '1' | 1081554 | 1 |