File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Clock gate - Latch + AND based clock gate
71: --
72: -- If ASIC technology is chosen, gate clocks. Otherwise, do not gate. Latch is
73: -- without reset since ICGs do not usually have reset.
74: --------------------------------------------------------------------------------
75:
76: Library ieee;
77: use ieee.std_logic_1164.all;
78:
79: Library ctu_can_fd_rtl;
80: use ctu_can_fd_rtl.can_constants_pkg.all;
81:
82: entity clk_gate is
83: generic (
84: G_TECHNOLOGY : natural
85: );
86: port (
87: -- Clock input
88: clk_in : in std_logic;
89:
90: -- Clock Enable
91: clk_en : in std_logic;
92:
93: -- Scan Enable
94: scan_enable : in std_logic;
95:
96: -- Gated clocks
97: clk_out : out std_logic
98: );
99: end clk_gate;
100:
101: architecture rtl of clk_gate is
102:
103: signal clk_en_q : std_logic;
104:
105: begin
106:
107: g_tech_asic : if (G_TECHNOLOGY = C_TECH_ASIC) generate
108:
109: -- Latching enable - transparent in zero since we use AND gating
110: clk_en_latch_proc : process(clk_in, clk_en, scan_enable)
111: begin
112: if (clk_in = '0') then
113: clk_en_q <= clk_en or scan_enable;
114: end if;
115: end process;
116:
117: -- Gating
118: clk_out <= clk_in AND clk_en_q;
119:
120: end generate g_tech_asic;
121:
122:
123: g_tech_fpga : if (G_TECHNOLOGY = C_TECH_FPGA) generate
124:
125: -- Connect directly (always enabled, no gating)
126: clk_out <= clk_in;
127:
128: -- Drive just to avoid un-driven signals warning by Synplify
129: clk_en_q <= '1';
130:
131: end generate g_tech_fpga;
132:
133: assert (G_TECHNOLOGY = C_TECH_ASIC or G_TECHNOLOGY = C_TECH_FPGA);
134:
135: end rtl;