NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.REINTEGRATION_COUNTER_INST	100.0 % (13/13)	100.0 % (12/12)	100.0 % (46/46)	100.0 % (18/18)	N.A.	N.A.	100.0 % (89/89)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.REINTEGRATION_COUNTER_INST

100.0 % (13/13)

100.0 % (12/12)

100.0 % (46/46)

100.0 % (18/18)

N.A.

100.0 % (89/89)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 129 to 131:

129:    reinteg_ctr_d <= (others => '0') when (reinteg_ctr_clr = '1') 
130:                                     else 
131:                     reinteg_ctr_q + 1;

Count: 27243
Threshold: 1

Signal assignment statement on line 129:

129: reinteg_ctr_d <= (others => '0') when (reinteg_ctr_clr = '1')
Count: 187
Threshold: 1

Signal assignment statement on line 131:

131: reinteg_ctr_q + 1;
Count: 27056
Threshold: 1

If statement on lines 134 to 137:

134:    reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or 
135:                                (reinteg_ctr_enable = '1' and rx_trigger = '1')) 
136:                          else 
137:                      '0';

Count: 20723346
Threshold: 1

Signal assignment statement on line 134:

134: reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or
Count: 22313
Threshold: 1

Signal assignment statement on line 137:

137: '0';
Count: 20701033
Threshold: 1

If statement on lines 140 to 142:

140:    reinteg_ctr_expired <= '1' when (reinteg_ctr_q = 128) 
141:                               else 
142:                           '0';

Count: 25302
Threshold: 1

Signal assignment statement on line 140:

140: reinteg_ctr_expired <= '1' when (reinteg_ctr_q = 128)
Count: 170
Threshold: 1

Signal assignment statement on line 142:

142: '0';
Count: 25132
Threshold: 1

If statement on lines 149 to 155:

149:        if (res_n = '0') then 
150:            reinteg_ctr_q <= (others => '0'); 
...
154:            end if; 
155:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 150:

150: reinteg_ctr_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 152 to 154:

152:            if (reinteg_ctr_ce = '1') then 
153:                reinteg_ctr_q <= reinteg_ctr_d; 
154:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 153:

153: reinteg_ctr_q <= reinteg_ctr_d;
Count: 26736
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 129:

129: reinteg_ctr_d <= (others => '0') when (reinteg_ctr_clr = '1')

	Evaluated to	Count	Threshold
Bin	True	187	1
Bin	False	27056	1

"if" / "when" / "else" condition on lines 134 to 135:

134:    reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or 
135:                                (reinteg_ctr_enable = '1' and rx_trigger = '1'))

	Evaluated to	Count	Threshold
Bin	True	22313	1
Bin	False	20701033	1

"if" / "when" / "else" condition on line 140:

140: reinteg_ctr_expired <= '1' when (reinteg_ctr_q = 128)

	Evaluated to	Count	Threshold
Bin	True	170	1
Bin	False	25132	1

"if" / "when" / "else" condition on line 149:

149: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 151:

151: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 152:

152: if (reinteg_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	26736	1
Bin	False	543764942	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REINTEG_CTR_CLR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REINTEG_CTR_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

REINTEG_CTR_EXPIRED

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	1771	1

Signal:

REINTEG_CTR_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	170	1
Bin	(7)	1	0	1771	1
Bin	(6)	0	1	170	1
Bin	(6)	1	0	1771	1
Bin	(5)	0	1	340	1
Bin	(5)	1	0	1941	1
Bin	(4)	0	1	680	1
Bin	(4)	1	0	2281	1
Bin	(3)	0	1	1360	1
Bin	(3)	1	0	2961	1
Bin	(2)	0	1	2720	1
Bin	(2)	1	0	4321	1
Bin	(1)	0	1	5610	1
Bin	(1)	1	0	7211	1
Bin	(0)	0	1	12804	1
Bin	(0)	1	0	11203	1

Signal:

REINTEG_CTR_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	170	1
Bin	(7)	1	0	1771	1
Bin	(6)	0	1	170	1
Bin	(6)	1	0	1771	1
Bin	(5)	0	1	340	1
Bin	(5)	1	0	1941	1
Bin	(4)	0	1	680	1
Bin	(4)	1	0	2281	1
Bin	(3)	0	1	1360	1
Bin	(3)	1	0	2961	1
Bin	(2)	0	1	2720	1
Bin	(2)	1	0	4321	1
Bin	(1)	0	1	5440	1
Bin	(1)	1	0	7041	1
Bin	(0)	0	1	11050	1
Bin	(0)	1	0	12651	1

Signal:

REINTEG_CTR_CE

	From	To	Count	Threshold
Bin	0	1	22100	1
Bin	1	0	23701	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 129:

reinteg_ctr_clr = '1'

	Evaluated to	Count	Threshold
Bin	False	27056	1
Bin	True	187	1

"or" expression on lines 134 to 135:

 reinteg_ctr_clr = '1' or (reinteg_ctr_enable = '1' and rx_trigger = '1') 
 <--------LHS-------->     <--------------------RHS-------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	20701033	1
Bin	False	True	21930	1
Bin	True	False	383	1

"=" expression on line 134:

reinteg_ctr_clr = '1'

	Evaluated to	Count	Threshold
Bin	False	20722963	1
Bin	True	383	1

"and" expression on line 135:

 reinteg_ctr_enable = '1' and rx_trigger = '1' 
 <---------LHS---------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	10338266	1
Bin	True	False	21938	1
Bin	True	True	21930	1

"=" expression on line 135:

reinteg_ctr_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	20679478	1
Bin	True	43868	1

"=" expression on line 135:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	10363150	1
Bin	True	10360196	1

"=" expression on line 149:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 152:

reinteg_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543764942	1
Bin	True	26736	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.REINTEGRATION_COUNTER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 129 to 131:

Signal assignment statement on line 129:

Signal assignment statement on line 131:

If statement on lines 134 to 137:

Signal assignment statement on line 134:

Signal assignment statement on line 137:

If statement on lines 140 to 142:

Signal assignment statement on line 140:

Signal assignment statement on line 142:

If statement on lines 149 to 155:

Signal assignment statement on line 150:

If statement on lines 152 to 154:

Signal assignment statement on line 153:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 129:

"if" / "when" / "else" condition on lines 134 to 135:

"if" / "when" / "else" condition on line 140:

"if" / "when" / "else" condition on line 149:

"if" / "when" / "else" condition on line 151:

"if" / "when" / "else" condition on line 152:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 129:

"or" expression on lines 134 to 135:

"=" expression on line 134:

"and" expression on line 135:

"=" expression on line 135:

"=" expression on line 135:

"=" expression on line 149:

"=" expression on line 152:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: