NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.REINTEGRATION_COUNTER_INST	100.0 % (13/13)	100.0 % (12/12)	100.0 % (46/46)	100.0 % (18/18)	N.A.	N.A.	100.0 % (89/89)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

129:    reinteg_ctr_d <= (others => '0') when (reinteg_ctr_clr = '1') 
130:                                     else 
131:                     reinteg_ctr_q + 1;

Count: 27240
Threshold: 1

Signal assignment statement:

129: reinteg_ctr_d <= (others => '0') when (reinteg_ctr_clr = '1')
Count: 187
Threshold: 1

Signal assignment statement:

131: reinteg_ctr_q + 1;
Count: 27053
Threshold: 1

If statement:

134:    reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or 
135:                                (reinteg_ctr_enable = '1' and rx_trigger = '1')) 
136:                          else 
137:                      '0';

Count: 20034546
Threshold: 1

Signal assignment statement:

134: reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or
Count: 22313
Threshold: 1

Signal assignment statement:

137: '0';
Count: 20012233
Threshold: 1

If statement:

140:    reinteg_ctr_expired <= '1' when (reinteg_ctr_q = 128) 
141:                               else 
142:                           '0';

Count: 25300
Threshold: 1

Signal assignment statement:

140: reinteg_ctr_expired <= '1' when (reinteg_ctr_q = 128)
Count: 170
Threshold: 1

Signal assignment statement:

142: '0';
Count: 25130
Threshold: 1

If statement:

149:        if (res_n = '0') then 
150:            reinteg_ctr_q <= (others => '0'); 
...
154:            end if; 
155:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

150: reinteg_ctr_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

152:            if (reinteg_ctr_ce = '1') then 
153:                reinteg_ctr_q <= reinteg_ctr_d; 
154:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

153: reinteg_ctr_q <= reinteg_ctr_d;
Count: 26736
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

129: reinteg_ctr_d <= (others => '0') when (reinteg_ctr_clr = '1')

	Evaluated to	Count	Threshold
Bin	True	187	1
Bin	False	27053	1

"if" / "when" / "else" condition:

134:    reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or 
135:                                (reinteg_ctr_enable = '1' and rx_trigger = '1'))

	Evaluated to	Count	Threshold
Bin	True	22313	1
Bin	False	20012233	1

"if" / "when" / "else" condition:

140: reinteg_ctr_expired <= '1' when (reinteg_ctr_q = 128)

	Evaluated to	Count	Threshold
Bin	True	170	1
Bin	False	25130	1

"if" / "when" / "else" condition:

149: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

151: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

152: if (reinteg_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	26736	1
Bin	False	526347564	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

REINTEG_CTR_CLR

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	1770	1

Port:

REINTEG_CTR_ENABLE

	From	To	Count	Threshold
Bin	0	1	21938	1
Bin	1	0	23538	1

Port:

RX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	10015414	1
Bin	1	0	10017014	1

Port:

REINTEG_CTR_EXPIRED

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	1770	1

Signal:

REINTEG_CTR_D(7)

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	1770	1

Signal:

REINTEG_CTR_D(6)

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	1770	1

Signal:

REINTEG_CTR_D(5)

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	1940	1

Signal:

REINTEG_CTR_D(4)

	From	To	Count	Threshold
Bin	0	1	680	1
Bin	1	0	2280	1

Signal:

REINTEG_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	1360	1
Bin	1	0	2960	1

Signal:

REINTEG_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	2720	1
Bin	1	0	4320	1

Signal:

REINTEG_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	5610	1
Bin	1	0	7210	1

Signal:

REINTEG_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	12803	1
Bin	1	0	11203	1

Signal:

REINTEG_CTR_Q(7)

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	1770	1

Signal:

REINTEG_CTR_Q(6)

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	1770	1

Signal:

REINTEG_CTR_Q(5)

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	1940	1

Signal:

REINTEG_CTR_Q(4)

	From	To	Count	Threshold
Bin	0	1	680	1
Bin	1	0	2280	1

Signal:

REINTEG_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	1360	1
Bin	1	0	2960	1

Signal:

REINTEG_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	2720	1
Bin	1	0	4320	1

Signal:

REINTEG_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	5440	1
Bin	1	0	7040	1

Signal:

REINTEG_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	11050	1
Bin	1	0	12650	1

Signal:

REINTEG_CTR_CE

	From	To	Count	Threshold
Bin	0	1	22100	1
Bin	1	0	23700	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

129: reinteg_ctr_d <= (others => '0') when (reinteg_ctr_clr = '1')

	Evaluated to	Count	Threshold
Bin	False	27053	1
Bin	True	187	1

"=" expression

134: reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or

	Evaluated to	Count	Threshold
Bin	False	20034163	1
Bin	True	383	1

"=" expression

135:                                (reinteg_ctr_enable = '1' and rx_trigger = '1'))

	Evaluated to	Count	Threshold
Bin	False	19990678	1
Bin	True	43868	1

"=" expression

135:                                (reinteg_ctr_enable = '1' and rx_trigger = '1'))

	Evaluated to	Count	Threshold
Bin	False	10018749	1
Bin	True	10015797	1

"and" expression

135:                                (reinteg_ctr_enable = '1' and rx_trigger = '1')) 
                                     <---------LHS---------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	9993867	1
Bin	True	False	21938	1
Bin	True	True	21930	1

"or" expression

134:    reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or 
135:                                (reinteg_ctr_enable = '1' and rx_trigger = '1'))

	LHS	RHS	Count	Threshold
Bin	False	False	20012233	1
Bin	False	True	21930	1
Bin	True	False	383	1

"=" expression

149: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

152: if (reinteg_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526347564	1
Bin	True	26736	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.REINTEGRATION_COUNTER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/reintegration_counter.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"=" expression

"=" expression

"and" expression

"or" expression

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: