NVC code coverage report

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
RX_SHIFT_RES_REG_INST	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
MUX2_RES_TST_INST	100.0 % (3/3)	100.0 % (2/2)	100.0 % (8/8)	N.A.	N.A.	N.A.	100.0 % (13/13)

Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

RX_SHIFT_RES_REG_INST

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

MUX2_RES_TST_INST

100.0 % (3/3)

100.0 % (2/2)

100.0 % (8/8)

N.A.

100.0 % (13/13)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TRV_DELAY_MEASUREMENT_INST.TRV_DELAY_RST_REG_INST	N.A.	N.A.	100.0 % (12/12)	N.A.	N.A.	N.A.	100.0 % (12/12)

Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TRV_DELAY_MEASUREMENT_INST.TRV_DELAY_RST_REG_INST

N.A.

100.0 % (12/12)

N.A.

100.0 % (12/12)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

ARST

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

D

	From	To	Count	Threshold
Bin	0	1	14871	1
Bin	1	0	13271	1

Port:

Q

	From	To	Count	Threshold
Bin	0	1	21352	1
Bin	1	0	21343	1

Port:

SCAN_ENABLE

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Signal:

Q_I

	From	To	Count	Threshold
Bin	0	1	21352	1
Bin	1	0	21343	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TRV_DELAY_MEASUREMENT_INST.TRV_DELAY_RST_REG_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_reg.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: