File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/trv_delay_meas.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Transcevier delay measurement.
71: --
72: -- Purpose:
73: -- Measures Transceiver delay and calculates position of secondary sampling
74: -- point.
75: --
76: -- Measurement is started by and edge on TX Data and Stopped by an edge on
77: -- RX Data. Measurement is performed only when it is enabled by Protocol
78: -- Control, otherwise measured values remain unchanged.
79: --
80: -- Secondary sampling point is shadowed during measurement and propagated to
81: -- output after the measurement. Data are loaded to output register upon the
82: -- end of transceiver delay measurement and kept stable till the end of next
83: -- measurement. Configurable offset "ssp_offset" is implemented.
84: --
85: -- Shadowed value is muxed based on "mr_ssp_cfg_ssp_src":
86: -- 1. Measured value + configured offset.
87: -- 2. Configured offset only.
88: --
89: -- Circuit has following diagram:
90: --
91: -- SSP Delay select
92: -- ------------------------------------+
93: -- |
94: -- Start Measurement |
95: -- ------------| |
96: -- | |
97: -- Stop | |
98: -- Measur. | |
99: -- ------ | |
100: -- | | |
101: -- v v | Shadow registers
102: -- +--------------+ | load
103: -- | Measurement +-------------------------------------------+
104: -- | Flag | | |
105: -- +------+-------+ | |
106: -- | | |
107: -- | Measurement progress | v
108: -- | | |----------| TRV
109: -- | ------------|------------------| Shadow | Delay
110: -- | | | | register |-------->
111: -- +------v-------+ Transceiver XX | |----------|
112: -- | Transceiver | Delay | X v |
113: -- | Delay +-------+-----> | X |
114: -- | Counter | | | X v
115: -- +--------------+ +--v--+ | X |------------| |----------| SSP
116: -- SSP offset | | | X | | | Shadow | Offset
117: -- -------------------> | + +--> | X+-| Saturation |->+ register |------->
118: -- | | | X | | | |
119: -- +-----+ | X |------------| |----------|
120: -- | X
121: -- | X
122: -- XX
123: --
124: --------------------------------------------------------------------------------
125:
126: Library ieee;
127: use ieee.std_logic_1164.all;
128: use ieee.numeric_std.ALL;
129:
130: Library ctu_can_fd_rtl;
131: use ctu_can_fd_rtl.can_constants_pkg.all;
132: use ctu_can_fd_rtl.can_types_pkg.all;
133:
134: use ctu_can_fd_rtl.CAN_FD_register_map.all;
135: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
136:
137: entity trv_delay_measurement is
138: generic (
139: -- Width (number of bits) in transceiver delay measurement counter
140: G_TRV_CTR_WIDTH : natural;
141:
142: -- Width of SSP position
143: G_SSP_POS_WIDTH : natural;
144:
145: -- Width of SSP offset
146: G_SSP_OFFSET_WIDTH : natural;
147:
148: -- Saturation level for size of SSP_delay. This is to make sure that if there is smaller
149: -- shift register for secondary sampling point we don't address outside of this register.
150: G_SSP_SATURATION_LVL : natural
151: );
152: port (
153: -------------------------------------------------------------------------------------------
154: -- Clock and Asynchronous reset
155: -------------------------------------------------------------------------------------------
156: clk_sys :in std_logic;
157: res_n :in std_logic;
158:
159: -------------------------------------------------------------------------------------------
160: -- DFT support
161: -------------------------------------------------------------------------------------------
162: scan_enable :in std_logic;
163:
164: -------------------------------------------------------------------------------------------
165: -- Transceiver Delay measurement control
166: -------------------------------------------------------------------------------------------
167: -- Start measurement (on TX Edge)
168: edge_tx_valid :in std_logic;
169:
170: -- Stop measurement (on RX Edge)
171: edge_rx_valid :in std_logic;
172:
173: -- Transmitter delay measurement enabled (by Protocol control)
174: tran_delay_meas :in std_logic;
175:
176: -------------------------------------------------------------------------------------------
177: -- Memory registers interface
178: -------------------------------------------------------------------------------------------
179: -- Secondary sampling point offset
180: mr_ssp_cfg_ssp_offset :in std_logic_vector(G_SSP_OFFSET_WIDTH - 1 downto 0);
181:
182: -- Source of secondary sampling point (Measured, Offset, Measured and Offset)
183: mr_ssp_cfg_ssp_src :in std_logic_vector(1 downto 0);
184:
185: -------------------------------------------------------------------------------------------
186: -- Status outputs
187: -------------------------------------------------------------------------------------------
188: -- Shadowed value of Transceiver delay. Updated when measurement ends.
189: trv_delay_shadowed :out std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
190:
191: -- Shadowed value of SSP configuration. Updated when measurement ends.
192: ssp_delay_shadowed :out std_logic_vector(G_SSP_POS_WIDTH - 1 downto 0)
193: );
194: end entity;
195:
196: architecture rtl of trv_delay_measurement is
197:
198: -- Transceiver delay measurement progress register
199: signal trv_meas_progress_d : std_logic;
200: signal trv_meas_progress_q : std_logic;
201:
202: -- Delayed value of trv_meas_progress to detect when measurement has ended
203: -- and load ssp_offset shadow register.
204: signal trv_meas_progress_del : std_logic;
205:
206: -------------------------------------------------------------------------------------------
207: -- Transceiver delay counter
208: -------------------------------------------------------------------------------------------
209: signal trv_delay_ctr_q : std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
210: signal trv_delay_ctr_d : std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
211: signal trv_delay_ctr_add : std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
212:
213: -- Reset for the counter
214: signal trv_delay_ctr_rst_d : std_logic;
215: signal trv_delay_ctr_rst_q_scan : std_logic;
216:
217: constant C_TRV_DEL_SAT : std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0) :=
218: std_logic_vector(to_unsigned(255, G_TRV_CTR_WIDTH));
219:
220: constant C_SSP_SAT_LVL_VECT : std_logic_vector(G_SSP_POS_WIDTH - 1 downto 0) :=
221: std_logic_vector(to_unsigned(G_SSP_SATURATION_LVL, G_SSP_POS_WIDTH));
222:
223: -- Load shadow register to output
224: signal ssp_shadow_ce : std_logic;
225:
226: -------------------------------------------------------------------------------------------
227: -- Shadowed value of transceiver delay counter
228: -------------------------------------------------------------------------------------------
229: -- Note that output counter is one bit wider than width of counter since
230: -- output value can be addition of two values of trv_ctr_width size and
231: -- we want to avoid overflow.
232: signal ssp_delay : std_logic_vector(G_SSP_POS_WIDTH - 1 downto 0);
233:
234: -- Measured transceiver value + trv_offset
235: signal trv_delay_sum : std_logic_vector(G_SSP_POS_WIDTH - 1 downto 0);
236:
237: begin
238:
239: -------------------------------------------------------------------------------------------
240: -- Next value of transceiver delay measurment flag:
241: -- 1. Clear immediately when measurement is disabled.
242: -- 2. Start measurement when enabled and "edge_tx_valid"
243: -- 3. Stop measurement when enabled and "edge_rx_valid"
244: -- 4. Keep value otherwise.
245: -------------------------------------------------------------------------------------------
246: trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else
247: '1' when (edge_tx_valid = '1') else
248: '0' when (edge_rx_valid = '1') else
249: trv_meas_progress_q;
250:
251: -------------------------------------------------------------------------------------------
252: -- Register for transceiver delay measurement progress flag.
253: -------------------------------------------------------------------------------------------
254: trv_delay_prog_proc : process(res_n, clk_sys)
255: begin
256: if (res_n = '0') then
257: trv_meas_progress_q <= '0';
258: trv_meas_progress_del <= '0';
259: elsif (rising_edge(clk_sys)) then
260: trv_meas_progress_q <= trv_meas_progress_d;
261: trv_meas_progress_del <= trv_meas_progress_q;
262: end if;
263: end process;
264:
265: -------------------------------------------------------------------------------------------
266: -- Reset counter for transceiver delay upon start of measurement.
267: -------------------------------------------------------------------------------------------
268: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')
269: else
270: '1';
271:
272: -------------------------------------------------------------------------------------------
273: -- Pipeline reset for shift registers to avoid glitches!
274: -------------------------------------------------------------------------------------------
275: trv_delay_rst_reg_inst : entity ctu_can_fd_rtl.rst_reg
276: generic map (
277: G_RESET_POLARITY => '0'
278: )
279: port map(
280: -- Clock and Reset
281: clk => clk_sys, -- IN
282: arst => res_n, -- IN
283:
284: -- Flip flop input / output
285: d => trv_delay_ctr_rst_d, -- IN
286: q => trv_delay_ctr_rst_q_scan, -- OUT
287:
288: -- Scan mode control
289: scan_enable => scan_enable -- IN
290: );
291:
292: -------------------------------------------------------------------------------------------
293: -- Combinationally incremented value of trv_delay counter by 1.
294: -------------------------------------------------------------------------------------------
295: trv_delay_ctr_add <= std_logic_vector(unsigned(trv_delay_ctr_q) + 1);
296:
297: -- Saturate when counter reaches 127, do not add anymore to avoid overflow!
298: trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT)
299: else
300: trv_delay_ctr_add;
301:
302: -------------------------------------------------------------------------------------------
303: -- Register for transceiver delay measurement progress flag.
304: -------------------------------------------------------------------------------------------
305: trv_del_ctr_proc : process(clk_sys, trv_delay_ctr_rst_q_scan)
306: begin
307: if (trv_delay_ctr_rst_q_scan = '0') then
308: trv_delay_ctr_q(0) <= '1';
309: trv_delay_ctr_q(G_TRV_CTR_WIDTH - 1 downto 1) <= (others => '0');
310:
311: elsif (rising_edge(clk_sys)) then
312:
313: -- Increment the counter if the measurement is in progress
314: if (trv_meas_progress_q = '1') then
315: trv_delay_ctr_q <= trv_delay_ctr_d;
316: end if;
317: end if;
318: end process;
319:
320: -------------------------------------------------------------------------------------------
321: -- Combinationally adding ssp_offset and trv_delay_ctr_q. These are one bit wider to cover
322: -- possible overflow!
323: -------------------------------------------------------------------------------------------
324: trv_delay_sum <= std_logic_vector(('0' & unsigned(trv_delay_ctr_q)) +
325: ('0' & unsigned(mr_ssp_cfg_ssp_offset)));
326:
327: -------------------------------------------------------------------------------------------
328: -- Multiplexor for selected secondary sampling point delay. Selects:
329: -- 1. Measured trv_delay + ssp_offset
330: -- 2. ssp_offset only.
331: -------------------------------------------------------------------------------------------
332: with mr_ssp_cfg_ssp_src select ssp_delay <=
333: trv_delay_sum when SSP_SRC_MEAS_N_OFFSET,
334: '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET,
335: (others => '0') when others;
336:
337: -------------------------------------------------------------------------------------------
338: -- SSP Shadow register. Both values are captured at the end of measurement.
339: -- 1. Transceiver Delay - Only measured value
340: -- 2. SSP Offset - Selected between measured, measured + offset, offset.
341: -------------------------------------------------------------------------------------------
342: ssp_shadow_reg_proc : process(res_n, clk_sys)
343: begin
344: if (res_n = '0') then
345: ssp_delay_shadowed <= (others => '0');
346: trv_delay_shadowed <= (others => '0');
347:
348: elsif (rising_edge(clk_sys)) then
349: if (ssp_shadow_ce = '1') then
350: ssp_delay_shadowed <= ssp_delay;
351: trv_delay_shadowed <= trv_delay_ctr_q;
352: end if;
353: end if;
354: end process;
355:
356: -------------------------------------------------------------------------------------------
357: -- Load shadow register for secondary sampling point after the end of secondary sampling
358: -- point measurement. This must be after the measurement has already ended so that last
359: -- value is taken, not the value decremented by 1!
360: -------------------------------------------------------------------------------------------
361: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')
362: else
363: '0';
364:
365: -- coverage off
366: assert (G_TRV_CTR_WIDTH <= G_SSP_POS_WIDTH)
367: report "SSP Position width must be higher or equal to trv counter width!"
368: severity error;
369: -- coverage on
370:
371: -------------------------------------------------------------------------------------------
372: -- Assertions and Functional coverge
373: -------------------------------------------------------------------------------------------
374: -- psl default clock is rising_edge(clk_sys);
375:
376: -- psl trv_delay_ctr_sat_asrt : assert never
377: -- (unsigned(trv_delay_ctr_q) > unsigned(C_TRV_DEL_SAT));
378:
379: -- psl ssp_offset_sat_asrt : assert never
380: -- (unsigned(ssp_delay_shadowed) > to_unsigned(G_SSP_SATURATION_LVL, G_SSP_POS_WIDTH));
381:
382: end architecture;