NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TRV_DELAY_RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

TRV_DELAY_RST_REG_INST

100.0 % (6/6)

100.0 % (28/28)

100.0 % (2/2)

N.A.

100.0 % (42/42)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TRV_DELAY_MEASUREMENT_INST	100.0 % (36/36)	100.0 % (31/31)	100.0 % (162/162)	100.0 % (30/30)	N.A.	N.A.	100.0 % (259/259)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TRV_DELAY_MEASUREMENT_INST

100.0 % (36/36)

100.0 % (31/31)

100.0 % (162/162)

100.0 % (30/30)

N.A.

100.0 % (259/259)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 247 to 250:

247:    trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else 
248:                           '1' when (edge_tx_valid = '1') else 
249:                           '0' when (edge_rx_valid = '1') else 
250:                           trv_meas_progress_q;

Count: 4175182
Threshold: 1

Signal assignment statement on line 247:

247: trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else
Count: 4025522
Threshold: 1

Signal assignment statement on line 248:

248: '1' when (edge_tx_valid = '1') else
Count: 26022
Threshold: 1

Signal assignment statement on line 249:

249: '0' when (edge_rx_valid = '1') else
Count: 42417
Threshold: 1

Signal assignment statement on line 250:

250: trv_meas_progress_q;
Count: 81221
Threshold: 1

If statement on lines 257 to 263:

257:        if (res_n = '0') then 
258:            trv_meas_progress_q     <= '0'; 
...
262:            trv_meas_progress_del   <= trv_meas_progress_q; 
263:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 258:

258: trv_meas_progress_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 259:

259: trv_meas_progress_del <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 261:

261: trv_meas_progress_q <= trv_meas_progress_d;
Count: 543791678
Threshold: 1

Signal assignment statement on line 262:

262: trv_meas_progress_del <= trv_meas_progress_q;
Count: 543791678
Threshold: 1

If statement on lines 269 to 271:

269:    trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1') 
270:                               else 
271:                           '1';

Count: 1346841
Threshold: 1

Signal assignment statement on line 269:

269: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')
Count: 13011
Threshold: 1

Signal assignment statement on line 271:

271: '1';
Count: 1333830
Threshold: 1

Signal assignment statement on line 296:

296: trv_delay_ctr_add <= std_logic_vector(unsigned(trv_delay_ctr_q) + 1);
Count: 41482
Threshold: 1

If statement on lines 299 to 301:

299:    trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT) 
300:                                     else 
301:                      trv_delay_ctr_add;

Count: 82964
Threshold: 1

Signal assignment statement on line 299:

299: trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT)
Count: 30
Threshold: 1

Signal assignment statement on line 301:

301: trv_delay_ctr_add;
Count: 82934
Threshold: 1

If statement on lines 308 to 318:

308:        if (trv_delay_ctr_rst_q_scan = '0') then 
309:            trv_delay_ctr_q(0) <= '1'; 
...
317:            end if; 
318:        end if;

Count: 1090044227
Threshold: 1

Signal assignment statement on line 309:

309: trv_delay_ctr_q(0) <= '1';
Count: 2476882
Threshold: 1

Signal assignment statement on line 310:

310: trv_delay_ctr_q(G_TRV_CTR_WIDTH - 1 downto 1) <= (others => '0');
Count: 2476882
Threshold: 1

If statement on lines 315 to 317:

315:            if (trv_meas_progress_q = '1') then 
316:                trv_delay_ctr_q <= trv_delay_ctr_d; 
317:            end if;

Count: 543772184
Threshold: 1

Signal assignment statement on line 316:

316: trv_delay_ctr_q <= trv_delay_ctr_d;
Count: 25425
Threshold: 1

Signal assignment statement on lines 325 to 326:

325:    trv_delay_sum <= std_logic_vector(('0' & unsigned(trv_delay_ctr_q)) + 
326:                                      ('0' & unsigned(mr_ssp_cfg_ssp_offset)));

Count: 49559
Threshold: 1

Sequential statement on lines 333 to 336:

333:    with mr_ssp_cfg_ssp_src select ssp_delay <= 
334:                  trv_delay_sum when SSP_SRC_MEAS_N_OFFSET, 
335:    '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET, 
336:                (others => '0') when others;

Count: 56475
Threshold: 1

Signal assignment statement on line 334:

334: trv_delay_sum when SSP_SRC_MEAS_N_OFFSET,
Count: 34530
Threshold: 1

Signal assignment statement on line 335:

335: '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET,
Count: 2827
Threshold: 1

Signal assignment statement on line 336:

336: (others => '0') when others;
Count: 19118
Threshold: 1

If statement on lines 345 to 354:

345:        if (res_n = '0') then 
346:            ssp_delay_shadowed <= (others => '0'); 
...
353:            end if; 
354:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 346:

346: ssp_delay_shadowed <= (others => '0');
Count: 2424883
Threshold: 1

Signal assignment statement on line 347:

347: trv_delay_shadowed <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 350 to 353:

350:            if (ssp_shadow_ce = '1') then 
351:                ssp_delay_shadowed <= ssp_delay; 
352:                trv_delay_shadowed <= trv_delay_ctr_q; 
353:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 351:

351: ssp_delay_shadowed <= ssp_delay;
Count: 13011
Threshold: 1

Signal assignment statement on line 352:

352: trv_delay_shadowed <= trv_delay_ctr_q;
Count: 13011
Threshold: 1

If statement on lines 362 to 364:

362:    ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0') 
363:                         else 
364:                     '0';

Count: 56846
Threshold: 1

Signal assignment statement on line 362:

362: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')
Count: 13011
Threshold: 1

Signal assignment statement on line 364:

364: '0';
Count: 43835
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 247:

247: trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else

	Evaluated to	Count	Threshold
Bin	True	4025522	1
Bin	False	149660	1

"if" / "when" / "else" condition on line 248:

248: '1' when (edge_tx_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	26022	1
Bin	False	123638	1

"if" / "when" / "else" condition on line 249:

249: '0' when (edge_rx_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	42417	1
Bin	False	81221	1

"if" / "when" / "else" condition on line 257:

257: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 260:

260: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 269:

269: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	13011	1
Bin	False	1333830	1

"if" / "when" / "else" condition on line 299:

299: trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT)

	Evaluated to	Count	Threshold
Bin	True	30	1
Bin	False	82934	1

"if" / "when" / "else" condition on line 308:

308: if (trv_delay_ctr_rst_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2476882	1
Bin	False	1087567345	1

"if" / "when" / "else" condition on line 312:

312: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543772184	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 315:

315: if (trv_meas_progress_q = '1') then

	Evaluated to	Count	Threshold
Bin	True	25425	1
Bin	False	543746759	1

"case" / "with" / "select" choice on line 334:

334: trv_delay_sum when SSP_SRC_MEAS_N_OFFSET,

	Choice of	Count	Threshold
Bin	`SSP_SRC_MEAS_N_OFFSET`	34530	1

"case" / "with" / "select" choice on line 335:

335: '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET,

	Choice of	Count	Threshold
Bin	`SSP_SRC_OFFSET`	2827	1

"case" / "with" / "select" choice on line 336:

336: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	19118	1

"if" / "when" / "else" condition on line 345:

345: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 349:

349: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 350:

350: if (ssp_shadow_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	13011	1
Bin	False	543778667	1

"if" / "when" / "else" condition on line 362:

362: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')

	Evaluated to	Count	Threshold
Bin	True	13011	1
Bin	False	43835	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

EDGE_TX_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

EDGE_RX_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_DELAY_MEAS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SSP_CFG_SSP_OFFSET

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_SSP_CFG_SSP_SRC

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

TRV_DELAY_SHADOWED

	Element	From	To	Count	Threshold
Bin	(7)	0	1	19	1
Bin	(7)	1	0	1620	1
Bin	(6)	0	1	40	1
Bin	(6)	1	0	1641	1
Bin	(5)	0	1	73	1
Bin	(5)	1	0	1674	1
Bin	(4)	0	1	86	1
Bin	(4)	1	0	1687	1
Bin	(3)	0	1	75	1
Bin	(3)	1	0	1676	1
Bin	(2)	0	1	79	1
Bin	(2)	1	0	1680	1
Bin	(1)	0	1	2145	1
Bin	(1)	1	0	3746	1
Bin	(0)	0	1	56	1
Bin	(0)	1	0	1657	1

Port:

SSP_DELAY_SHADOWED

	Element	From	To	Count	Threshold
Bin	(8)	0	1	12	1
Bin	(8)	1	0	1613	1
Bin	(7)	0	1	31	1
Bin	(7)	1	0	1632	1
Bin	(6)	0	1	43	1
Bin	(6)	1	0	1644	1
Bin	(5)	0	1	65	1
Bin	(5)	1	0	1666	1
Bin	(4)	0	1	58	1
Bin	(4)	1	0	1659	1
Bin	(3)	0	1	267	1
Bin	(3)	1	0	1868	1
Bin	(2)	0	1	934	1
Bin	(2)	1	0	2535	1
Bin	(1)	0	1	241	1
Bin	(1)	1	0	1842	1
Bin	(0)	0	1	907	1
Bin	(0)	1	0	2508	1

Signal:

TRV_MEAS_PROGRESS_D

	From	To	Count	Threshold
Bin	0	1	13011	1
Bin	1	0	14612	1

Signal:

TRV_MEAS_PROGRESS_Q

	From	To	Count	Threshold
Bin	0	1	13011	1
Bin	1	0	14612	1

Signal:

TRV_MEAS_PROGRESS_DEL

	From	To	Count	Threshold
Bin	0	1	13011	1
Bin	1	0	14612	1

Signal:

TRV_DELAY_CTR_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	58	1
Bin	(7)	1	0	1630	1
Bin	(6)	0	1	154	1
Bin	(6)	1	0	1708	1
Bin	(5)	0	1	382	1
Bin	(5)	1	0	1899	1
Bin	(4)	0	1	798	1
Bin	(4)	1	0	2295	1
Bin	(3)	0	1	1581	1
Bin	(3)	1	0	3084	1
Bin	(2)	0	1	3155	1
Bin	(2)	1	0	4670	1
Bin	(1)	0	1	19142	1
Bin	(1)	1	0	20680	1
Bin	(0)	0	1	20774	1
Bin	(0)	1	0	19107	1

Signal:

TRV_DELAY_CTR_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	29	1
Bin	(7)	1	0	1630	1
Bin	(6)	0	1	79	1
Bin	(6)	1	0	1680	1
Bin	(5)	0	1	193	1
Bin	(5)	1	0	1794	1
Bin	(4)	0	1	400	1
Bin	(4)	1	0	2001	1
Bin	(3)	0	1	799	1
Bin	(3)	1	0	2400	1
Bin	(2)	0	1	1598	1
Bin	(2)	1	0	3199	1
Bin	(1)	0	1	4714	1
Bin	(1)	1	0	3113	1
Bin	(0)	0	1	19107	1
Bin	(0)	1	0	20708	1

Signal:

TRV_DELAY_CTR_ADD

	Element	From	To	Count	Threshold
Bin	(7)	0	1	29	1
Bin	(7)	1	0	1630	1
Bin	(6)	0	1	79	1
Bin	(6)	1	0	1680	1
Bin	(5)	0	1	193	1
Bin	(5)	1	0	1794	1
Bin	(4)	0	1	400	1
Bin	(4)	1	0	2001	1
Bin	(3)	0	1	799	1
Bin	(3)	1	0	2400	1
Bin	(2)	0	1	1598	1
Bin	(2)	1	0	3199	1
Bin	(1)	0	1	4714	1
Bin	(1)	1	0	3113	1
Bin	(0)	0	1	19107	1
Bin	(0)	1	0	20708	1

Signal:

TRV_DELAY_CTR_RST_D

	From	To	Count	Threshold
Bin	0	1	14612	1
Bin	1	0	13011	1

Signal:

TRV_DELAY_CTR_RST_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	21094	1
Bin	1	0	21083	1

Signal:

SSP_SHADOW_CE

	From	To	Count	Threshold
Bin	0	1	13011	1
Bin	1	0	14612	1

Signal:

SSP_DELAY

	Element	From	To	Count	Threshold
Bin	(8)	0	1	17	1
Bin	(8)	1	0	3219	1
Bin	(7)	0	1	53	1
Bin	(7)	1	0	3255	1
Bin	(6)	0	1	94	1
Bin	(6)	1	0	3296	1
Bin	(5)	0	1	204	1
Bin	(5)	1	0	3406	1
Bin	(4)	0	1	346	1
Bin	(4)	1	0	3548	1
Bin	(3)	0	1	4891	1
Bin	(3)	1	0	4902	1
Bin	(2)	0	1	4016	1
Bin	(2)	1	0	7217	1
Bin	(1)	0	1	7011	1
Bin	(1)	1	0	7022	1
Bin	(0)	0	1	15233	1
Bin	(0)	1	0	15245	1

Signal:

TRV_DELAY_SUM

	Element	From	To	Count	Threshold
Bin	(8)	0	1	26	1
Bin	(8)	1	0	1627	1
Bin	(7)	0	1	70	1
Bin	(7)	1	0	1671	1
Bin	(6)	0	1	133	1
Bin	(6)	1	0	1734	1
Bin	(5)	0	1	265	1
Bin	(5)	1	0	1866	1
Bin	(4)	0	1	469	1
Bin	(4)	1	0	2070	1
Bin	(3)	0	1	5130	1
Bin	(3)	1	0	3540	1
Bin	(2)	0	1	4479	1
Bin	(2)	1	0	6079	1
Bin	(1)	0	1	14724	1
Bin	(1)	1	0	13134	1
Bin	(0)	0	1	23104	1
Bin	(0)	1	0	21504	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 247:

tran_delay_meas = '0'

	Evaluated to	Count	Threshold
Bin	False	149660	1
Bin	True	4025522	1

"=" expression on line 248:

edge_tx_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	123638	1
Bin	True	26022	1

"=" expression on line 249:

edge_rx_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	81221	1
Bin	True	42417	1

"=" expression on line 257:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"and" expression on line 269:

 tran_delay_meas = '1' and edge_tx_valid = '1' 
 <--------LHS-------->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	620817	1
Bin	True	False	50202	1
Bin	True	True	13011	1

"=" expression on line 269:

tran_delay_meas = '1'

	Evaluated to	Count	Threshold
Bin	False	1283628	1
Bin	True	63213	1

"=" expression on line 269:

edge_tx_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	713013	1
Bin	True	633828	1

"=" expression on line 308:

trv_delay_ctr_rst_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087567345	1
Bin	True	2476882	1

"=" expression on line 315:

trv_meas_progress_q = '1'

	Evaluated to	Count	Threshold
Bin	False	543746759	1
Bin	True	25425	1

"=" expression on line 345:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 350:

ssp_shadow_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543778667	1
Bin	True	13011	1

"and" expression on line 362:

 (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0') 
  <-----------LHS----------->       <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	16213	1
Bin	True	False	13010	1
Bin	True	True	13011	1

"=" expression on line 362:

trv_meas_progress_del = '1'

	Evaluated to	Count	Threshold
Bin	False	30825	1
Bin	True	26021	1

"=" expression on line 362:

trv_meas_progress_q = '0'

	Evaluated to	Count	Threshold
Bin	False	27622	1
Bin	True	29224	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TRV_DELAY_MEASUREMENT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 247 to 250:

Signal assignment statement on line 247:

Signal assignment statement on line 248:

Signal assignment statement on line 249:

Signal assignment statement on line 250:

If statement on lines 257 to 263:

Signal assignment statement on line 258:

Signal assignment statement on line 259:

Signal assignment statement on line 261:

Signal assignment statement on line 262:

If statement on lines 269 to 271:

Signal assignment statement on line 269:

Signal assignment statement on line 271:

Signal assignment statement on line 296:

If statement on lines 299 to 301:

Signal assignment statement on line 299:

Signal assignment statement on line 301:

If statement on lines 308 to 318:

Signal assignment statement on line 309:

Signal assignment statement on line 310:

If statement on lines 315 to 317:

Signal assignment statement on line 316:

Signal assignment statement on lines 325 to 326:

Sequential statement on lines 333 to 336:

Signal assignment statement on line 334:

Signal assignment statement on line 335:

Signal assignment statement on line 336:

If statement on lines 345 to 354:

Signal assignment statement on line 346:

Signal assignment statement on line 347:

If statement on lines 350 to 353:

Signal assignment statement on line 351:

Signal assignment statement on line 352:

If statement on lines 362 to 364:

Signal assignment statement on line 362:

Signal assignment statement on line 364:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 247:

"if" / "when" / "else" condition on line 248:

"if" / "when" / "else" condition on line 249:

"if" / "when" / "else" condition on line 257:

"if" / "when" / "else" condition on line 260:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on line 299:

"if" / "when" / "else" condition on line 308:

"if" / "when" / "else" condition on line 312:

"if" / "when" / "else" condition on line 315:

"case" / "with" / "select" choice on line 334:

"case" / "with" / "select" choice on line 335:

"case" / "with" / "select" choice on line 336:

"if" / "when" / "else" condition on line 345:

"if" / "when" / "else" condition on line 349:

"if" / "when" / "else" condition on line 350:

"if" / "when" / "else" condition on line 362:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal: