NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TRV_DELAY_RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TRV_DELAY_MEASUREMENT_INST	100.0 % (36/36)	100.0 % (31/31)	100.0 % (162/162)	100.0 % (30/30)	N.A.	N.A.	100.0 % (259/259)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

247:    trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else 
248:                           '1' when (edge_tx_valid = '1') else 
249:                           '0' when (edge_rx_valid = '1') else 
250:                           trv_meas_progress_q;

Count: 4171244
Threshold: 1

Signal assignment statement:

247: trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else
Count: 4023236
Threshold: 1

Signal assignment statement:

248: '1' when (edge_tx_valid = '1') else
Count: 26542
Threshold: 1

Signal assignment statement:

249: '0' when (edge_rx_valid = '1') else
Count: 42415
Threshold: 1

Signal assignment statement:

250: trv_meas_progress_q;
Count: 79051
Threshold: 1

If statement:

257:        if (res_n = '0') then 
258:            trv_meas_progress_q     <= '0'; 
...
262:            trv_meas_progress_del   <= trv_meas_progress_q; 
263:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

258: trv_meas_progress_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

259: trv_meas_progress_del <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

261: trv_meas_progress_q <= trv_meas_progress_d;
Count: 526374300
Threshold: 1

Signal assignment statement:

262: trv_meas_progress_del <= trv_meas_progress_q;
Count: 526374300
Threshold: 1

If statement:

269:    trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1') 
270:                               else 
271:                           '1';

Count: 1345580
Threshold: 1

Signal assignment statement:

269: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')
Count: 13271
Threshold: 1

Signal assignment statement:

271: '1';
Count: 1332309
Threshold: 1

Signal assignment statement:

296: trv_delay_ctr_add <= std_logic_vector(unsigned(trv_delay_ctr_q) + 1);
Count: 42264
Threshold: 1

If statement:

299:    trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT) 
300:                                     else 
301:                      trv_delay_ctr_add;

Count: 84528
Threshold: 1

Signal assignment statement:

299: trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT)
Count: 30
Threshold: 1

Signal assignment statement:

301: trv_delay_ctr_add;
Count: 84498
Threshold: 1

If statement:

308:        if (trv_delay_ctr_rst_q_scan = '0') then 
309:            trv_delay_ctr_q(0) <= '1'; 
...
317:            end if; 
318:        end if;

Count: 1055203624
Threshold: 1

Signal assignment statement:

309: trv_delay_ctr_q(0) <= '1';
Count: 2471276
Threshold: 1

Signal assignment statement:

310: trv_delay_ctr_q(G_TRV_CTR_WIDTH - 1 downto 1) <= (others => '0');
Count: 2471276
Threshold: 1

If statement:

315:            if (trv_meas_progress_q = '1') then 
316:                trv_delay_ctr_q <= trv_delay_ctr_d; 
317:            end if;

Count: 526354547
Threshold: 1

Signal assignment statement:

316: trv_delay_ctr_q <= trv_delay_ctr_d;
Count: 25949
Threshold: 1

Signal assignment statement:

325:    trv_delay_sum <= std_logic_vector(('0' & unsigned(trv_delay_ctr_q)) + 
326:                                      ('0' & unsigned(mr_ssp_cfg_ssp_offset)));

Count: 50340
Threshold: 1

Sequential statement:

333:    with mr_ssp_cfg_ssp_src select ssp_delay <= 
334:                  trv_delay_sum when SSP_SRC_MEAS_N_OFFSET, 
335:    '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET, 
336:                (others => '0') when others;

Count: 57255
Threshold: 1

Signal assignment statement:

334: trv_delay_sum when SSP_SRC_MEAS_N_OFFSET,
Count: 34784
Threshold: 1

Signal assignment statement:

335: '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET,
Count: 2945
Threshold: 1

Signal assignment statement:

336: (others => '0') when others;
Count: 19526
Threshold: 1

If statement:

345:        if (res_n = '0') then 
346:            ssp_delay_shadowed <= (others => '0'); 
...
353:            end if; 
354:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

346: ssp_delay_shadowed <= (others => '0');
Count: 2418499
Threshold: 1

Signal assignment statement:

347: trv_delay_shadowed <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

350:            if (ssp_shadow_ce = '1') then 
351:                ssp_delay_shadowed <= ssp_delay; 
352:                trv_delay_shadowed <= trv_delay_ctr_q; 
353:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

351: ssp_delay_shadowed <= ssp_delay;
Count: 13271
Threshold: 1

Signal assignment statement:

352: trv_delay_shadowed <= trv_delay_ctr_q;
Count: 13271
Threshold: 1

If statement:

362:    ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0') 
363:                         else 
364:                     '0';

Count: 57883
Threshold: 1

Signal assignment statement:

362: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')
Count: 13271
Threshold: 1

Signal assignment statement:

364: '0';
Count: 44612
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

247: trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else

	Evaluated to	Count	Threshold
Bin	True	4023236	1
Bin	False	148008	1

"if" / "when" / "else" condition:

248: '1' when (edge_tx_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	26542	1
Bin	False	121466	1

"if" / "when" / "else" condition:

249: '0' when (edge_rx_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	42415	1
Bin	False	79051	1

"if" / "when" / "else" condition:

257: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

260: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

269: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	13271	1
Bin	False	1332309	1

"if" / "when" / "else" condition:

299: trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT)

	Evaluated to	Count	Threshold
Bin	True	30	1
Bin	False	84498	1

"if" / "when" / "else" condition:

308: if (trv_delay_ctr_rst_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2471276	1
Bin	False	1052732348	1

"if" / "when" / "else" condition:

312: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526354547	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

315: if (trv_meas_progress_q = '1') then

	Evaluated to	Count	Threshold
Bin	True	25949	1
Bin	False	526328598	1

"case" / "with" / "select" choice:

334: trv_delay_sum when SSP_SRC_MEAS_N_OFFSET,

	Choice of	Count	Threshold
Bin	`SSP_SRC_MEAS_N_OFFSET`	34784	1

"case" / "with" / "select" choice:

335: '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET,

	Choice of	Count	Threshold
Bin	`SSP_SRC_OFFSET`	2945	1

"case" / "with" / "select" choice:

336: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	19526	1

"if" / "when" / "else" condition:

345: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

349: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

350: if (ssp_shadow_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	13271	1
Bin	False	526361029	1

"if" / "when" / "else" condition:

362: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')

	Evaluated to	Count	Threshold
Bin	True	13271	1
Bin	False	44612	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SCAN_ENABLE

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

EDGE_TX_VALID

	From	To	Count	Threshold
Bin	0	1	635365	1
Bin	1	0	636965	1

Port:

EDGE_RX_VALID

	From	To	Count	Threshold
Bin	0	1	1399296	1
Bin	1	0	1400896	1

Port:

TRAN_DELAY_MEAS

	From	To	Count	Threshold
Bin	0	1	35025	1
Bin	1	0	36625	1

Port:

MR_SSP_CFG_SSP_OFFSET(7)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

MR_SSP_CFG_SSP_OFFSET(6)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

MR_SSP_CFG_SSP_OFFSET(5)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1644	1

Port:

MR_SSP_CFG_SSP_OFFSET(4)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1652	1

Port:

MR_SSP_CFG_SSP_OFFSET(3)

	From	To	Count	Threshold
Bin	0	1	4305	1
Bin	1	0	2715	1

Port:

MR_SSP_CFG_SSP_OFFSET(2)

	From	To	Count	Threshold
Bin	0	1	527	1
Bin	1	0	2127	1

Port:

MR_SSP_CFG_SSP_OFFSET(1)

	From	To	Count	Threshold
Bin	0	1	2899	1
Bin	1	0	1309	1

Port:

MR_SSP_CFG_SSP_OFFSET(0)

	From	To	Count	Threshold
Bin	0	1	2397	1
Bin	1	0	3997	1

Port:

MR_SSP_CFG_SSP_SRC(1)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1647	1

Port:

MR_SSP_CFG_SSP_SRC(0)

	From	To	Count	Threshold
Bin	0	1	817	1
Bin	1	0	2407	1

Port:

TRV_DELAY_SHADOWED(7)

	From	To	Count	Threshold
Bin	0	1	21	1
Bin	1	0	1621	1

Port:

TRV_DELAY_SHADOWED(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1642	1

Port:

TRV_DELAY_SHADOWED(5)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1668	1

Port:

TRV_DELAY_SHADOWED(4)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1683	1

Port:

TRV_DELAY_SHADOWED(3)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1681	1

Port:

TRV_DELAY_SHADOWED(2)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1687	1

Port:

TRV_DELAY_SHADOWED(1)

	From	To	Count	Threshold
Bin	0	1	2154	1
Bin	1	0	3754	1

Port:

TRV_DELAY_SHADOWED(0)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1656	1

Port:

SSP_DELAY_SHADOWED(8)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	1611	1

Port:

SSP_DELAY_SHADOWED(7)

	From	To	Count	Threshold
Bin	0	1	32	1
Bin	1	0	1632	1

Port:

SSP_DELAY_SHADOWED(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1642	1

Port:

SSP_DELAY_SHADOWED(5)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1666	1

Port:

SSP_DELAY_SHADOWED(4)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1657	1

Port:

SSP_DELAY_SHADOWED(3)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	1868	1

Port:

SSP_DELAY_SHADOWED(2)

	From	To	Count	Threshold
Bin	0	1	931	1
Bin	1	0	2531	1

Port:

SSP_DELAY_SHADOWED(1)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	1839	1

Port:

SSP_DELAY_SHADOWED(0)

	From	To	Count	Threshold
Bin	0	1	908	1
Bin	1	0	2508	1

Signal:

TRV_MEAS_PROGRESS_D

	From	To	Count	Threshold
Bin	0	1	13271	1
Bin	1	0	14871	1

Signal:

TRV_MEAS_PROGRESS_Q

	From	To	Count	Threshold
Bin	0	1	13271	1
Bin	1	0	14871	1

Signal:

TRV_MEAS_PROGRESS_DEL

	From	To	Count	Threshold
Bin	0	1	13271	1
Bin	1	0	14871	1

Signal:

TRV_DELAY_CTR_Q(7)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1630	1

Signal:

TRV_DELAY_CTR_Q(6)

	From	To	Count	Threshold
Bin	0	1	161	1
Bin	1	0	1713	1

Signal:

TRV_DELAY_CTR_Q(5)

	From	To	Count	Threshold
Bin	0	1	386	1
Bin	1	0	1903	1

Signal:

TRV_DELAY_CTR_Q(4)

	From	To	Count	Threshold
Bin	0	1	811	1
Bin	1	0	2305	1

Signal:

TRV_DELAY_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	1613	1
Bin	1	0	3113	1

Signal:

TRV_DELAY_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	3227	1
Bin	1	0	4734	1

Signal:

TRV_DELAY_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	19536	1
Bin	1	0	21061	1

Signal:

TRV_DELAY_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	21163	1
Bin	1	0	19501	1

Signal:

TRV_DELAY_CTR_D(7)

	From	To	Count	Threshold
Bin	0	1	30	1
Bin	1	0	1630	1

Signal:

TRV_DELAY_CTR_D(6)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1683	1

Signal:

TRV_DELAY_CTR_D(5)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	1797	1

Signal:

TRV_DELAY_CTR_D(4)

	From	To	Count	Threshold
Bin	0	1	408	1
Bin	1	0	2008	1

Signal:

TRV_DELAY_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	816	1
Bin	1	0	2416	1

Signal:

TRV_DELAY_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	1635	1
Bin	1	0	3235	1

Signal:

TRV_DELAY_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	4784	1
Bin	1	0	3184	1

Signal:

TRV_DELAY_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	19501	1
Bin	1	0	21101	1

Signal:

TRV_DELAY_CTR_ADD(7)

	From	To	Count	Threshold
Bin	0	1	30	1
Bin	1	0	1630	1

Signal:

TRV_DELAY_CTR_ADD(6)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1683	1

Signal:

TRV_DELAY_CTR_ADD(5)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	1797	1

Signal:

TRV_DELAY_CTR_ADD(4)

	From	To	Count	Threshold
Bin	0	1	408	1
Bin	1	0	2008	1

Signal:

TRV_DELAY_CTR_ADD(3)

	From	To	Count	Threshold
Bin	0	1	816	1
Bin	1	0	2416	1

Signal:

TRV_DELAY_CTR_ADD(2)

	From	To	Count	Threshold
Bin	0	1	1635	1
Bin	1	0	3235	1

Signal:

TRV_DELAY_CTR_ADD(1)

	From	To	Count	Threshold
Bin	0	1	4784	1
Bin	1	0	3184	1

Signal:

TRV_DELAY_CTR_ADD(0)

	From	To	Count	Threshold
Bin	0	1	19501	1
Bin	1	0	21101	1

Signal:

TRV_DELAY_CTR_RST_D

	From	To	Count	Threshold
Bin	0	1	14871	1
Bin	1	0	13271	1

Signal:

TRV_DELAY_CTR_RST_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	21352	1
Bin	1	0	21343	1

Signal:

SSP_SHADOW_CE

	From	To	Count	Threshold
Bin	0	1	13271	1
Bin	1	0	14871	1

Signal:

SSP_DELAY(8)

	From	To	Count	Threshold
Bin	0	1	16	1
Bin	1	0	3216	1

Signal:

SSP_DELAY(7)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	3252	1

Signal:

SSP_DELAY(6)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	3294	1

Signal:

SSP_DELAY(5)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	3395	1

Signal:

SSP_DELAY(4)

	From	To	Count	Threshold
Bin	0	1	338	1
Bin	1	0	3538	1

Signal:

SSP_DELAY(3)

	From	To	Count	Threshold
Bin	0	1	4871	1
Bin	1	0	4881	1

Signal:

SSP_DELAY(2)

	From	To	Count	Threshold
Bin	0	1	3847	1
Bin	1	0	7047	1

Signal:

SSP_DELAY(1)

	From	To	Count	Threshold
Bin	0	1	6805	1
Bin	1	0	6815	1

Signal:

SSP_DELAY(0)

	From	To	Count	Threshold
Bin	0	1	15361	1
Bin	1	0	15371	1

Signal:

TRV_DELAY_SUM(8)

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	1624	1

Signal:

TRV_DELAY_SUM(7)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1669	1

Signal:

TRV_DELAY_SUM(6)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	1740	1

Signal:

TRV_DELAY_SUM(5)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	1868	1

Signal:

TRV_DELAY_SUM(4)

	From	To	Count	Threshold
Bin	0	1	480	1
Bin	1	0	2080	1

Signal:

TRV_DELAY_SUM(3)

	From	To	Count	Threshold
Bin	0	1	5145	1
Bin	1	0	3555	1

Signal:

TRV_DELAY_SUM(2)

	From	To	Count	Threshold
Bin	0	1	4382	1
Bin	1	0	5982	1

Signal:

TRV_DELAY_SUM(1)

	From	To	Count	Threshold
Bin	0	1	14657	1
Bin	1	0	13067	1

Signal:

TRV_DELAY_SUM(0)

	From	To	Count	Threshold
Bin	0	1	23498	1
Bin	1	0	21898	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

247: trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else

	Evaluated to	Count	Threshold
Bin	False	148008	1
Bin	True	4023236	1

"=" expression

248: '1' when (edge_tx_valid = '1') else

	Evaluated to	Count	Threshold
Bin	False	121466	1
Bin	True	26542	1

"=" expression

249: '0' when (edge_rx_valid = '1') else

	Evaluated to	Count	Threshold
Bin	False	79051	1
Bin	True	42415	1

"=" expression

257: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

269: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	1284013	1
Bin	True	61567	1

"=" expression

269: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	710215	1
Bin	True	635365	1

"and" expression

269:    trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1') 
                                         <--------LHS-------->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	622094	1
Bin	True	False	48296	1
Bin	True	True	13271	1

"=" expression

308: if (trv_delay_ctr_rst_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052732348	1
Bin	True	2471276	1

"=" expression

315: if (trv_meas_progress_q = '1') then

	Evaluated to	Count	Threshold
Bin	False	526328598	1
Bin	True	25949	1

"=" expression

345: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

350: if (ssp_shadow_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526361029	1
Bin	True	13271	1

"=" expression

362: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')

	Evaluated to	Count	Threshold
Bin	False	31342	1
Bin	True	26541	1

"=" expression

362: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')

	Evaluated to	Count	Threshold
Bin	False	28141	1
Bin	True	29742	1

"and" expression

362:    ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0') 
                                   <-----------LHS----------->       <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	16471	1
Bin	True	False	13270	1
Bin	True	True	13271	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TRV_DELAY_MEASUREMENT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/trv_delay_meas.vhd

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