NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CAN_RX_SIG_SYNC_INST	100.0 % (5/5)	100.0 % (4/4)	100.0 % (10/10)	100.0 % (2/2)	N.A.	N.A.	100.0 % (21/21)
TRV_DELAY_MEASUREMENT_INST	100.0 % (42/42)	100.0 % (37/37)	100.0 % (190/190)	100.0 % (32/32)	N.A.	N.A.	100.0 % (301/301)
DATA_EDGE_DETECTOR_INST	100.0 % (17/17)	100.0 % (12/12)	100.0 % (28/28)	100.0 % (35/35)	N.A.	N.A.	100.0 % (92/92)
SHIFT_REGS_RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
TX_TRIGGER_REG_INST	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
SSP_GENERATOR_INST	100.0 % (55/55)	100.0 % (56/56)	100.0 % (262/262)	100.0 % (65/65)	N.A.	N.A.	100.0 % (438/438)
TX_DATA_CACHE_INST	100.0 % (15/15)	100.0 % (18/18)	100.0 % (60/60)	100.0 % (12/12)	N.A.	N.A.	100.0 % (105/105)
BIT_ERR_DETECTOR_INST	100.0 % (24/24)	100.0 % (24/24)	100.0 % (38/38)	100.0 % (56/56)	N.A.	N.A.	100.0 % (142/142)
SAMPLE_MUX_INST	100.0 % (10/10)	100.0 % (10/10)	100.0 % (24/24)	100.0 % (6/6)	N.A.	N.A.	100.0 % (50/50)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST	100.0 % (9/9)	100.0 % (6/6)	100.0 % (118/118)	100.0 % (7/7)	N.A.	N.A.	100.0 % (140/140)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

313:    shift_regs_res_d <= '0' when (ssp_reset = '1') else 
314:                        '1';

Count: 72760
Threshold: 1

Signal assignment statement:

313: shift_regs_res_d <= '0' when (ssp_reset = '1') else
Count: 34780
Threshold: 1

Signal assignment statement:

314: '1';
Count: 37980
Threshold: 1

If statement:

378:    ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else 
379:                  '0';

Count: 60360
Threshold: 1

Signal assignment statement:

378: ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else
Count: 4206
Threshold: 1

Signal assignment statement:

379: '0';
Count: 56154
Threshold: 1

If statement:

386:    tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE) 
387:                          else 
388:                      '0';

Count: 22141883
Threshold: 1

Signal assignment statement:

386: tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE)
Count: 189570
Threshold: 1

Signal assignment statement:

388: '0';
Count: 21952313
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

313: shift_regs_res_d <= '0' when (ssp_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	34780	1
Bin	False	37980	1

"if" / "when" / "else" condition:

378: ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	4206	1
Bin	False	56154	1

"if" / "when" / "else" condition:

386: tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE)

	Evaluated to	Count	Threshold
Bin	True	189570	1
Bin	False	21952313	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SCAN_ENABLE

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

CAN_RX

	From	To	Count	Threshold
Bin	0	1	1409503	1
Bin	1	0	1407903	1

Port:

CAN_TX

	From	To	Count	Threshold
Bin	0	1	635336	1
Bin	1	0	633738	1

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

MR_SSP_CFG_SSP_OFFSET(7)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

MR_SSP_CFG_SSP_OFFSET(6)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

MR_SSP_CFG_SSP_OFFSET(5)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1644	1

Port:

MR_SSP_CFG_SSP_OFFSET(4)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1652	1

Port:

MR_SSP_CFG_SSP_OFFSET(3)

	From	To	Count	Threshold
Bin	0	1	4305	1
Bin	1	0	2715	1

Port:

MR_SSP_CFG_SSP_OFFSET(2)

	From	To	Count	Threshold
Bin	0	1	527	1
Bin	1	0	2127	1

Port:

MR_SSP_CFG_SSP_OFFSET(1)

	From	To	Count	Threshold
Bin	0	1	2899	1
Bin	1	0	1309	1

Port:

MR_SSP_CFG_SSP_OFFSET(0)

	From	To	Count	Threshold
Bin	0	1	2397	1
Bin	1	0	3997	1

Port:

MR_SSP_CFG_SSP_SRC(1)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1647	1

Port:

MR_SSP_CFG_SSP_SRC(0)

	From	To	Count	Threshold
Bin	0	1	817	1
Bin	1	0	2407	1

Port:

TRV_DELAY(7)

	From	To	Count	Threshold
Bin	0	1	21	1
Bin	1	0	1621	1

Port:

TRV_DELAY(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1642	1

Port:

TRV_DELAY(5)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1668	1

Port:

TRV_DELAY(4)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1683	1

Port:

TRV_DELAY(3)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1681	1

Port:

TRV_DELAY(2)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1687	1

Port:

TRV_DELAY(1)

	From	To	Count	Threshold
Bin	0	1	2154	1
Bin	1	0	3754	1

Port:

TRV_DELAY(0)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1656	1

Port:

RX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	22084127	1
Bin	1	0	22085727	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

SYNC_EDGE

	From	To	Count	Threshold
Bin	0	1	1555148	1
Bin	1	0	1556748	1

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	108871268	1
Bin	1	0	108872865	1

Port:

TX_DATA_WBS

	From	To	Count	Threshold
Bin	0	1	635336	1
Bin	1	0	633738	1

Port:

RX_DATA_WBS

	From	To	Count	Threshold
Bin	0	1	1400896	1
Bin	1	0	1399296	1

Port:

SP_CONTROL(1)

	From	To	Count	Threshold
Bin	0	1	4206	1
Bin	1	0	5806	1

Port:

SP_CONTROL(0)

	From	To	Count	Threshold
Bin	0	1	25548	1
Bin	1	0	27148	1

Port:

SSP_RESET

	From	To	Count	Threshold
Bin	0	1	34780	1
Bin	1	0	36380	1

Port:

TRAN_DELAY_MEAS

	From	To	Count	Threshold
Bin	0	1	35025	1
Bin	1	0	36625	1

Port:

BIT_ERR

	From	To	Count	Threshold
Bin	0	1	9381	1
Bin	1	0	10981	1

Port:

BTMC_RESET

	From	To	Count	Threshold
Bin	0	1	28129	1
Bin	1	0	29729	1

Port:

DBT_MEASURE_START

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Port:

GEN_FIRST_SSP

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Port:

BIT_ERR_ENABLE

	From	To	Count	Threshold
Bin	0	1	66912	1
Bin	1	0	65320	1

Signal:

DATA_RX_SYNCED

	From	To	Count	Threshold
Bin	0	1	1400896	1
Bin	1	0	1399296	1

Signal:

PREV_SAMPLE

	From	To	Count	Threshold
Bin	0	1	1390558	1
Bin	1	0	1388958	1

Signal:

SAMPLE_SEC

	From	To	Count	Threshold
Bin	0	1	190334	1
Bin	1	0	191934	1

Signal:

DATA_TX_DELAYED

	From	To	Count	Threshold
Bin	0	1	97563	1
Bin	1	0	95963	1

Signal:

EDGE_RX_VALID

	From	To	Count	Threshold
Bin	0	1	1399296	1
Bin	1	0	1400896	1

Signal:

EDGE_TX_VALID

	From	To	Count	Threshold
Bin	0	1	635365	1
Bin	1	0	636965	1

Signal:

SSP_DELAY(8)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	1611	1

Signal:

SSP_DELAY(7)

	From	To	Count	Threshold
Bin	0	1	32	1
Bin	1	0	1632	1

Signal:

SSP_DELAY(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1642	1

Signal:

SSP_DELAY(5)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1666	1

Signal:

SSP_DELAY(4)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1657	1

Signal:

SSP_DELAY(3)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	1868	1

Signal:

SSP_DELAY(2)

	From	To	Count	Threshold
Bin	0	1	931	1
Bin	1	0	2531	1

Signal:

SSP_DELAY(1)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	1839	1

Signal:

SSP_DELAY(0)

	From	To	Count	Threshold
Bin	0	1	908	1
Bin	1	0	2508	1

Signal:

TX_TRIGGER_Q

	From	To	Count	Threshold
Bin	0	1	11039962	1
Bin	1	0	11041561	1

Signal:

TX_TRIGGER_SSP

	From	To	Count	Threshold
Bin	0	1	189570	1
Bin	1	0	191170	1

Signal:

SHIFT_REGS_RES_D

	From	To	Count	Threshold
Bin	0	1	36380	1
Bin	1	0	34780	1

Signal:

SHIFT_REGS_RES_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	42860	1
Bin	1	0	42851	1

Signal:

SSP_ENABLE

	From	To	Count	Threshold
Bin	0	1	4206	1
Bin	1	0	5806	1

Uncovered expressions:

Excluded expressions:

"and" expression

386:    tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE) 
                                    <------LHS------->     <------------RHS------------>

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression

313: shift_regs_res_d <= '0' when (ssp_reset = '1') else

	Evaluated to	Count	Threshold
Bin	False	37980	1
Bin	True	34780	1

"=" expression

386: tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE)

	Evaluated to	Count	Threshold
Bin	False	11101921	1
Bin	True	11039962	1

"and" expression

386:    tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE) 
                                    <------LHS------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	True	False	10850392	1
Bin	True	True	189570	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

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Signal assignment statement:

Signal assignment statement:

If statement:

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If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

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