NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CAN_RX_SIG_SYNC_INST	100.0 % (5/5)	100.0 % (4/4)	100.0 % (10/10)	100.0 % (2/2)	N.A.	N.A.	100.0 % (21/21)
TRV_DELAY_MEASUREMENT_INST	100.0 % (42/42)	100.0 % (37/37)	100.0 % (190/190)	100.0 % (32/32)	N.A.	N.A.	100.0 % (301/301)
DATA_EDGE_DETECTOR_INST	100.0 % (19/19)	100.0 % (12/12)	100.0 % (28/28)	100.0 % (35/35)	N.A.	N.A.	100.0 % (94/94)
SHIFT_REGS_RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
TX_TRIGGER_REG_INST	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
SSP_GENERATOR_INST	100.0 % (55/55)	100.0 % (56/56)	100.0 % (262/262)	100.0 % (65/65)	N.A.	N.A.	100.0 % (438/438)
TX_DATA_CACHE_INST	100.0 % (15/15)	100.0 % (18/18)	100.0 % (60/60)	100.0 % (12/12)	N.A.	N.A.	100.0 % (105/105)
BIT_ERR_DETECTOR_INST	100.0 % (25/25)	100.0 % (24/24)	100.0 % (38/38)	100.0 % (56/56)	N.A.	N.A.	100.0 % (143/143)
SAMPLE_MUX_INST	100.0 % (11/11)	100.0 % (10/10)	100.0 % (24/24)	100.0 % (6/6)	N.A.	N.A.	100.0 % (51/51)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST	100.0 % (11/11)	100.0 % (6/6)	100.0 % (118/118)	100.0 % (7/7)	N.A.	N.A.	100.0 % (142/142)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement	Branch	Toggle	Expression	FSM state	Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 313 to 314:

313:    shift_regs_res_d <= '0' when (ssp_reset = '1') else 
314:                        '1';

Count: 69514
Threshold: 1

Signal assignment statement on line 313:

313: shift_regs_res_d <= '0' when (ssp_reset = '1') else
Count: 33156
Threshold: 1

Signal assignment statement on line 314:

314: '1';
Count: 36358
Threshold: 1

If statement on lines 378 to 379:

378:    ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else 
379:                  '0';

Count: 59768
Threshold: 1

Signal assignment statement on line 378:

378: ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else
Count: 3434
Threshold: 1

Signal assignment statement on line 379:

379: '0';
Count: 56334
Threshold: 1

If statement on lines 386 to 388:

386:    tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE) 
387:                          else 
388:                      '0';

Count: 22835256
Threshold: 1

Signal assignment statement on line 386:

386: tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE)
Count: 159398
Threshold: 1

Signal assignment statement on line 388:

388: '0';
Count: 22675858
Threshold: 1

Signal assignment statement on line 448:

448: can_tx <= tx_data_wbs;
Count: 1267598
Threshold: 1

Signal assignment statement on line 451:

451: rx_data_wbs <= data_rx_synced;
Count: 2805057
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 313:

313: shift_regs_res_d <= '0' when (ssp_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	33156	1
Bin	False	36358	1

"if" / "when" / "else" condition on line 378:

378: ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	3434	1
Bin	False	56334	1

"if" / "when" / "else" condition on line 386:

386: tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE)

	Evaluated to	Count	Threshold
Bin	True	159398	1
Bin	False	22675858	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CAN_RX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SSP_CFG_SSP_OFFSET

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_SSP_CFG_SSP_SRC

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TQ_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_DATA_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SSP_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_DELAY_MEAS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BTMC_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DBT_MEASURE_START

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

GEN_FIRST_SSP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BIT_ERR_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CAN_TX

	From	To	Count	Threshold
Bin	0	1	633797	1
Bin	1	0	632200	1

Port:

TRV_DELAY

	Element	From	To	Count	Threshold
Bin	(7)	0	1	19	1
Bin	(7)	1	0	1620	1
Bin	(6)	0	1	40	1
Bin	(6)	1	0	1641	1
Bin	(5)	0	1	73	1
Bin	(5)	1	0	1674	1
Bin	(4)	0	1	86	1
Bin	(4)	1	0	1687	1
Bin	(3)	0	1	75	1
Bin	(3)	1	0	1676	1
Bin	(2)	0	1	79	1
Bin	(2)	1	0	1680	1
Bin	(1)	0	1	2145	1
Bin	(1)	1	0	3746	1
Bin	(0)	0	1	56	1
Bin	(0)	1	0	1657	1

Port:

SYNC_EDGE

	From	To	Count	Threshold
Bin	0	1	1555192	1
Bin	1	0	1556793	1

Port:

RX_DATA_WBS

	From	To	Count	Threshold
Bin	0	1	1402528	1
Bin	1	0	1400928	1

Port:

BIT_ERR

	From	To	Count	Threshold
Bin	0	1	9785	1
Bin	1	0	11386	1

Signal:

DATA_RX_SYNCED

	From	To	Count	Threshold
Bin	0	1	1402528	1
Bin	1	0	1400928	1

Signal:

PREV_SAMPLE

	From	To	Count	Threshold
Bin	0	1	1392225	1
Bin	1	0	1390624	1

Signal:

SAMPLE_SEC

	From	To	Count	Threshold
Bin	0	1	160181	1
Bin	1	0	161782	1

Signal:

DATA_TX_DELAYED

	From	To	Count	Threshold
Bin	0	1	81893	1
Bin	1	0	80292	1

Signal:

EDGE_RX_VALID

	From	To	Count	Threshold
Bin	0	1	1400928	1
Bin	1	0	1402528	1

Signal:

EDGE_TX_VALID

	From	To	Count	Threshold
Bin	0	1	633828	1
Bin	1	0	635429	1

Signal:

SSP_DELAY

	Element	From	To	Count	Threshold
Bin	(8)	0	1	12	1
Bin	(8)	1	0	1613	1
Bin	(7)	0	1	31	1
Bin	(7)	1	0	1632	1
Bin	(6)	0	1	43	1
Bin	(6)	1	0	1644	1
Bin	(5)	0	1	65	1
Bin	(5)	1	0	1666	1
Bin	(4)	0	1	58	1
Bin	(4)	1	0	1659	1
Bin	(3)	0	1	267	1
Bin	(3)	1	0	1868	1
Bin	(2)	0	1	934	1
Bin	(2)	1	0	2535	1
Bin	(1)	0	1	241	1
Bin	(1)	1	0	1842	1
Bin	(0)	0	1	907	1
Bin	(0)	1	0	2508	1

Signal:

TX_TRIGGER_Q

	From	To	Count	Threshold
Bin	0	1	11386944	1
Bin	1	0	11388544	1

Signal:

TX_TRIGGER_SSP

	From	To	Count	Threshold
Bin	0	1	159398	1
Bin	1	0	160999	1

Signal:

SHIFT_REGS_RES_D

	From	To	Count	Threshold
Bin	0	1	34757	1
Bin	1	0	33156	1

Signal:

SHIFT_REGS_RES_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	41238	1
Bin	1	0	41227	1

Signal:

SSP_ENABLE

	From	To	Count	Threshold
Bin	0	1	3434	1
Bin	1	0	5035	1

Uncovered expressions:

Excluded expressions:

"and" expression on line 386:

 tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE 
 <------LHS------->     <------------RHS------------>

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression on line 313:

ssp_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	36358	1
Bin	True	33156	1

"and" expression on line 386:

 tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE 
 <------LHS------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	True	False	11227546	1
Bin	True	True	159398	1

"=" expression on line 386:

tx_trigger_q = '1'

	Evaluated to	Count	Threshold
Bin	False	11448312	1
Bin	True	11386944	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 313 to 314:

Signal assignment statement on line 313:

Signal assignment statement on line 314:

If statement on lines 378 to 379:

Signal assignment statement on line 378:

Signal assignment statement on line 379:

If statement on lines 386 to 388:

Signal assignment statement on line 386:

Signal assignment statement on line 388:

Signal assignment statement on line 448:

Signal assignment statement on line 451:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 313:

"if" / "when" / "else" condition on line 378:

"if" / "when" / "else" condition on line 386:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

"and" expression on line 386:

Covered expressions:

"=" expression on line 313:

"and" expression on line 386:

"=" expression on line 386:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: