NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(6)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(7)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_A_MASK_PRESENT_GEN_T.FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (58/58)	100.0 % (3/3)	N.A.	N.A.	100.0 % (62/62)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

140: wr_en <= write and cs;
Count: 156742
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	29063051	1
Bin	1	0	29063711	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	4612	1
Bin	1	0	3952	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	33296	1
Bin	1	0	755224	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	41814	1
Bin	1	0	746706	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	36216	1
Bin	1	0	752304	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	40217	1
Bin	1	0	748303	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	58401	1
Bin	1	0	730119	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	61314	1
Bin	1	0	727206	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	79096	1
Bin	1	0	709424	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	80705	1
Bin	1	0	707815	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	73302	1
Bin	1	0	73962	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	4079	1
Bin	1	0	4739	1

Port:

REG_VALUE(7)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	739	1

Port:

REG_VALUE(6)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	774	1

Port:

REG_VALUE(5)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	751	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	767	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	783	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	916	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	927	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	927	1

Signal:

REG_VALUE_R(7)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1735	1

Signal:

REG_VALUE_R(6)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	1700	1

Signal:

REG_VALUE_R(5)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	1723	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1707	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	1691	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	1558	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	1547	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	1547	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	4063	1
Bin	1	0	4723	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

140:    wr_en <= write and cs; 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	4079	1
Bin	'1'	'0'	73302	1
Bin	'1'	'1'	4063	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.FILTER_A_MASK_PRESENT_GEN_T.FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

Signal assignment statement:

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Port:

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Signal:

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Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: